Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1600706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

254441

1

T1

14

T2

335

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	629049	1			T1	41		T2	836		T3	59
values[0x0]	596370	1			T1	4		T2	783		T3	66
values[0x1]	629728	1			T1	37		T2	851		T3	68

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1236872	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

618275

1

T1

34

T2

802

T3

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29061	1			T2	43		T3	3		T7	5
valid_sources[0x01]	28732	1			T1	2		T2	29		T3	1
valid_sources[0x02]	28923	1			T1	2		T2	30		T3	3
valid_sources[0x03]	29860	1			T1	4		T2	44		T3	1
valid_sources[0x04]	28457	1			T2	41		T3	4		T9	37
valid_sources[0x05]	29278	1			T2	34		T3	2		T7	1
valid_sources[0x06]	29940	1			T1	3		T2	51		T3	1
valid_sources[0x07]	27880	1			T2	35		T3	2		T7	4
valid_sources[0x08]	28845	1			T1	4		T2	35		T3	3
valid_sources[0x09]	27929	1			T1	3		T2	39		T3	2
valid_sources[0x0a]	29626	1			T1	1		T2	44		T3	9
valid_sources[0x0b]	28758	1			T1	3		T2	37		T3	3
valid_sources[0x0c]	30162	1			T1	1		T2	41		T3	3
valid_sources[0x0d]	28699	1			T1	1		T2	35		T3	3
valid_sources[0x0e]	29962	1			T1	1		T2	35		T3	4
valid_sources[0x0f]	29252	1			T1	5		T2	50		T3	5
valid_sources[0x10]	28171	1			T1	3		T2	33		T3	1
valid_sources[0x11]	27572	1			T1	2		T2	37		T3	2
valid_sources[0x12]	28128	1			T1	3		T2	31		T3	7
valid_sources[0x13]	29370	1			T2	46		T3	4		T7	3
valid_sources[0x14]	29602	1			T1	2		T2	39		T3	9
valid_sources[0x15]	28832	1			T2	26		T3	4		T7	2
valid_sources[0x16]	27750	1			T1	1		T2	48		T3	2
valid_sources[0x17]	29493	1			T1	1		T2	33		T3	2
valid_sources[0x18]	29322	1			T1	1		T2	27		T3	2
valid_sources[0x19]	29115	1			T1	2		T2	44		T3	3
valid_sources[0x1a]	29533	1			T2	47		T7	6		T9	25
valid_sources[0x1b]	29778	1			T1	1		T2	30		T3	8
valid_sources[0x1c]	28706	1			T2	38		T3	7		T7	2
valid_sources[0x1d]	28861	1			T1	4		T2	38		T3	2
valid_sources[0x1e]	28710	1			T2	33		T3	4		T7	2
valid_sources[0x1f]	28152	1			T1	3		T2	40		T3	4
valid_sources[0x20]	28027	1			T2	40		T7	1		T9	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26421

1

T1

4

T2

33

T3

5

values[0x0]

all_enables

biggest_size

201419

1

T1

2

T2

274

T3

15

values[0x1]

all_enables

biggest_size

26601

1

T1

8

T2

28

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1617338	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264611

1

T1

9

T2

368

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	642822	1			T1	24		T2	885		T3	51
values[0x0]	594892	1			T1	2		T2	811		T3	62
values[0x1]	644235	1			T1	36		T2	880		T3	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1241948	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

640001

1

T1

29

T2

891

T3

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28916	1			T1	1		T2	43		T3	1
valid_sources[0x01]	28983	1			T1	4		T2	38		T3	5
valid_sources[0x02]	29178	1			T2	30		T3	3		T7	2
valid_sources[0x03]	28536	1			T2	41		T3	2		T7	2
valid_sources[0x04]	29449	1			T2	24		T3	2		T9	33
valid_sources[0x05]	29350	1			T2	53		T7	2		T9	36
valid_sources[0x06]	29111	1			T1	1		T2	28		T7	1
valid_sources[0x07]	29579	1			T1	3		T2	68		T3	1
valid_sources[0x08]	29484	1			T1	1		T2	34		T3	1
valid_sources[0x09]	29723	1			T1	1		T2	34		T3	3
valid_sources[0x0a]	29637	1			T1	2		T2	31		T3	6
valid_sources[0x0b]	29028	1			T1	1		T2	31		T3	2
valid_sources[0x0c]	28789	1			T1	1		T2	70		T3	6
valid_sources[0x0d]	29820	1			T2	26		T3	4		T7	1
valid_sources[0x0e]	29952	1			T2	49		T3	1		T7	6
valid_sources[0x0f]	29488	1			T2	73		T3	5		T9	20
valid_sources[0x10]	28789	1			T1	1		T2	32		T3	4
valid_sources[0x11]	29974	1			T2	50		T7	4		T9	29
valid_sources[0x12]	29021	1			T1	1		T2	37		T3	2
valid_sources[0x13]	29750	1			T1	2		T2	33		T3	5
valid_sources[0x14]	29846	1			T1	1		T2	56		T9	40
valid_sources[0x15]	29825	1			T1	2		T2	63		T3	3
valid_sources[0x16]	30367	1			T2	46		T9	18		T8	7
valid_sources[0x17]	29476	1			T1	1		T2	64		T3	5
valid_sources[0x18]	28849	1			T2	29		T3	7		T9	35
valid_sources[0x19]	29592	1			T2	30		T7	2		T9	25
valid_sources[0x1a]	29188	1			T1	1		T2	55		T3	1
valid_sources[0x1b]	29172	1			T1	1		T2	42		T3	6
valid_sources[0x1c]	29645	1			T1	1		T2	49		T3	2
valid_sources[0x1d]	29158	1			T2	52		T7	5		T9	28
valid_sources[0x1e]	29906	1			T1	1		T2	36		T3	5
valid_sources[0x1f]	28681	1			T1	2		T2	25		T3	6
valid_sources[0x20]	29577	1			T2	47		T3	2		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27730

1

T1

5

T2

36

T3

1

values[0x0]

all_enables

biggest_size

208910

1

T2

293

T3

21

T7

4

values[0x1]

all_enables

biggest_size

27971

1

T1

4

T2

39

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1616408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256589

1

T1

5

T2

338

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	635241	1			T1	31		T2	881		T3	53
values[0x0]	601798	1			T1	5		T2	816		T3	52
values[0x1]	635958	1			T1	28		T2	834		T3	70

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1248938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

624059

1

T1

32

T2

821

T3

52

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30045	1			T2	36		T3	1		T7	5
valid_sources[0x01]	28101	1			T1	1		T2	32		T3	2
valid_sources[0x02]	29153	1			T2	41		T3	1		T9	36
valid_sources[0x03]	28734	1			T2	42		T3	4		T9	19
valid_sources[0x04]	28581	1			T2	43		T3	3		T7	1
valid_sources[0x05]	29031	1			T1	1		T2	37		T3	1
valid_sources[0x06]	28895	1			T1	1		T2	31		T3	1
valid_sources[0x07]	28843	1			T2	35		T7	3		T9	51
valid_sources[0x08]	29480	1			T2	37		T3	2		T7	1
valid_sources[0x09]	29087	1			T2	54		T7	4		T9	8
valid_sources[0x0a]	29859	1			T1	2		T2	43		T3	1
valid_sources[0x0b]	29634	1			T2	50		T3	2		T7	2
valid_sources[0x0c]	29372	1			T2	47		T3	3		T7	3
valid_sources[0x0d]	29876	1			T1	3		T2	58		T3	6
valid_sources[0x0e]	29938	1			T2	43		T7	2		T9	28
valid_sources[0x0f]	29575	1			T2	39		T3	5		T7	4
valid_sources[0x10]	29231	1			T1	3		T2	41		T3	5
valid_sources[0x11]	29726	1			T1	2		T2	39		T3	4
valid_sources[0x12]	29792	1			T1	7		T2	42		T3	2
valid_sources[0x13]	29209	1			T2	45		T3	2		T7	2
valid_sources[0x14]	29279	1			T2	37		T3	4		T7	1
valid_sources[0x15]	29868	1			T2	38		T7	1		T9	21
valid_sources[0x16]	28048	1			T2	54		T3	4		T7	5
valid_sources[0x17]	29782	1			T2	37		T3	3		T7	1
valid_sources[0x18]	29207	1			T2	44		T3	6		T7	1
valid_sources[0x19]	28840	1			T1	1		T2	41		T3	1
valid_sources[0x1a]	28798	1			T2	31		T3	1		T7	2
valid_sources[0x1b]	29697	1			T2	42		T3	5		T7	1
valid_sources[0x1c]	28958	1			T2	32		T3	1		T7	4
valid_sources[0x1d]	29684	1			T1	1		T2	44		T3	4
valid_sources[0x1e]	29289	1			T1	2		T2	38		T3	3
valid_sources[0x1f]	28945	1			T2	36		T3	2		T7	3
valid_sources[0x20]	29744	1			T1	1		T2	48		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26867

1

T2

32

T3

1

T7

3

values[0x0]

all_enables

biggest_size

203039

1

T1

4

T2

277

T3

15

values[0x1]

all_enables

biggest_size

26683

1

T1

1

T2

29

T3

3