Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7850633	0	0
GntImpliesValid_A	2147483647	7850633	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7850633	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	450008889	0	0
ReadyAndValidImplyGrant_A	2147483647	7850633	0	0
ReqAndReadyImplyGrant_A	2147483647	7850633	0	0
ReqImpliesValid_A	2147483647	32762188	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	54846	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7850633	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189096	187776	0	0
T2	263544	263424	0	0
T3	10608120	10606920	0	0
T4	3006600	3005496	0	0
T7	1369968	1368984	0	0
T8	10316808	10316496	0	0
T9	206616	205872	0	0
T10	93576	92904	0	0
T11	2533824	2532528	0	0
T12	13360080	13358832	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7850633	0	0
T1	189096	2413	0	0
T2	263544	7576	0	0
T3	10608120	542	0	0
T4	3006600	11323	0	0
T7	1369968	3584	0	0
T8	10316808	452	0	0
T9	206616	5216	0	0
T10	93576	2105	0	0
T11	2533824	54330	0	0
T12	13360080	1275	0	0
T13	0	461	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7850633	0	0
T1	189096	2413	0	0
T2	263544	7576	0	0
T3	10608120	542	0	0
T4	3006600	11323	0	0
T7	1369968	3584	0	0
T8	10316808	452	0	0
T9	206616	5216	0	0
T10	93576	2105	0	0
T11	2533824	54330	0	0
T12	13360080	1275	0	0
T13	0	461	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189096	187776	0	0
T2	263544	263424	0	0
T3	10608120	10606920	0	0
T4	3006600	3005496	0	0
T7	1369968	1368984	0	0
T8	10316808	10316496	0	0
T9	206616	205872	0	0
T10	93576	92904	0	0
T11	2533824	2532528	0	0
T12	13360080	13358832	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189096	187776	0	0
T2	263544	263424	0	0
T3	10608120	10606920	0	0
T4	3006600	3005496	0	0
T7	1369968	1368984	0	0
T8	10316808	10316496	0	0
T9	206616	205872	0	0
T10	93576	92904	0	0
T11	2533824	2532528	0	0
T12	13360080	13358832	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7850633	0	0
T1	189096	2413	0	0
T2	263544	7576	0	0
T3	10608120	542	0	0
T4	3006600	11323	0	0
T7	1369968	3584	0	0
T8	10316808	452	0	0
T9	206616	5216	0	0
T10	93576	2105	0	0
T11	2533824	54330	0	0
T12	13360080	1275	0	0
T13	0	461	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	450008889	0	0
T1	189096	4736	0	0
T2	263544	7143	0	0
T3	10608120	370676	0	0
T4	3006600	123243	0	0
T7	1369968	75316	0	0
T8	10316808	542040	0	0
T9	206616	6005	0	0
T10	93576	2456	0	0
T11	2533824	43108	0	0
T12	13360080	912085	0	0
T13	0	225	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7850633	0	0
T1	189096	2413	0	0
T2	263544	7576	0	0
T3	10608120	542	0	0
T4	3006600	11323	0	0
T7	1369968	3584	0	0
T8	10316808	452	0	0
T9	206616	5216	0	0
T10	93576	2105	0	0
T11	2533824	54330	0	0
T12	13360080	1275	0	0
T13	0	461	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7850633	0	0
T1	189096	2413	0	0
T2	263544	7576	0	0
T3	10608120	542	0	0
T4	3006600	11323	0	0
T7	1369968	3584	0	0
T8	10316808	452	0	0
T9	206616	5216	0	0
T10	93576	2105	0	0
T11	2533824	54330	0	0
T12	13360080	1275	0	0
T13	0	461	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32762188	0	0
T1	189096	3037	0	0
T2	263544	8628	0	0
T3	10608120	896	0	0
T4	3006600	99774	0	0
T7	1369968	7511	0	0
T8	10316808	21271	0	0
T9	206616	6020	0	0
T10	93576	2396	0	0
T11	2533824	88729	0	0
T12	13360080	80347	0	0
T13	0	519	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	54846	0	21600
T1	15758	2	0	2
T2	21962	26	0	2
T3	884010	0	0	2
T4	250550	41	0	2
T7	114164	0	0	2
T8	859734	0	0	2
T9	17218	18	0	2
T10	7798	5	0	2
T11	211152	1471	0	2
T12	1113340	0	0	2
T13	0	4	0	0
T14	0	12	0	0
T15	0	1	0	0
T16	0	39	0	0
T17	0	23	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189096	187776	0	0
T2	263544	263424	0	0
T3	10608120	10606920	0	0
T4	3006600	3005496	0	0
T7	1369968	1368984	0	0
T8	10316808	10316496	0	0
T9	206616	205872	0	0
T10	93576	92904	0	0
T11	2533824	2532528	0	0
T12	13360080	13358832	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7850633	0	0
T1	189096	2413	0	0
T2	263544	7576	0	0
T3	10608120	542	0	0
T4	3006600	11323	0	0
T7	1369968	3584	0	0
T8	10316808	452	0	0
T9	206616	5216	0	0
T10	93576	2105	0	0
T11	2533824	54330	0	0
T12	13360080	1275	0	0
T13	0	461	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	874491	0	0
GntImpliesValid_A	415429174	874491	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	874491	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	11735672	0	0
ReadyAndValidImplyGrant_A	415429174	874491	0	0
ReqAndReadyImplyGrant_A	415429174	874491	0	0
ReqImpliesValid_A	415429174	2394317	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	874491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874491	0	0
T1	7879	264	0	0
T2	10981	856	0	0
T3	442005	61	0	0
T4	125275	1487	0	0
T7	57082	391	0	0
T8	429867	48	0	0
T9	8609	604	0	0
T10	3899	215	0	0
T11	105576	7458	0	0
T12	556670	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874491	0	0
T1	7879	264	0	0
T2	10981	856	0	0
T3	442005	61	0	0
T4	125275	1487	0	0
T7	57082	391	0	0
T8	429867	48	0	0
T9	8609	604	0	0
T10	3899	215	0	0
T11	105576	7458	0	0
T12	556670	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874491	0	0
T1	7879	264	0	0
T2	10981	856	0	0
T3	442005	61	0	0
T4	125275	1487	0	0
T7	57082	391	0	0
T8	429867	48	0	0
T9	8609	604	0	0
T10	3899	215	0	0
T11	105576	7458	0	0
T12	556670	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	11735672	0	0
T1	7879	217	0	0
T2	10981	622	0	0
T3	442005	248	0	0
T4	125275	5605	0	0
T7	57082	2777	0	0
T8	429867	16889	0	0
T9	8609	441	0	0
T10	3899	175	0	0
T11	105576	3950	0	0
T12	556670	33120	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874491	0	0
T1	7879	264	0	0
T2	10981	856	0	0
T3	442005	61	0	0
T4	125275	1487	0	0
T7	57082	391	0	0
T8	429867	48	0	0
T9	8609	604	0	0
T10	3899	215	0	0
T11	105576	7458	0	0
T12	556670	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874491	0	0
T1	7879	264	0	0
T2	10981	856	0	0
T3	442005	61	0	0
T4	125275	1487	0	0
T7	57082	391	0	0
T8	429867	48	0	0
T9	8609	604	0	0
T10	3899	215	0	0
T11	105576	7458	0	0
T12	556670	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2394317	0	0
T1	7879	312	0	0
T2	10981	1091	0	0
T3	442005	70	0	0
T4	125275	9633	0	0
T7	57082	651	0	0
T8	429867	391	0	0
T9	8609	768	0	0
T10	3899	256	0	0
T11	105576	10967	0	0
T12	556670	3617	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874491	0	0
T1	7879	264	0	0
T2	10981	856	0	0
T3	442005	61	0	0
T4	125275	1487	0	0
T7	57082	391	0	0
T8	429867	48	0	0
T9	8609	604	0	0
T10	3899	215	0	0
T11	105576	7458	0	0
T12	556670	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	891422	0	0
GntImpliesValid_A	415429174	891422	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	891422	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	11660217	0	0
ReadyAndValidImplyGrant_A	415429174	891422	0	0
ReqAndReadyImplyGrant_A	415429174	891422	0	0
ReqImpliesValid_A	415429174	2474502	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	891422	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	891422	0	0
T1	7879	246	0	0
T2	10981	854	0	0
T3	442005	57	0	0
T4	125275	1516	0	0
T7	57082	360	0	0
T8	429867	43	0	0
T9	8609	608	0	0
T10	3899	208	0	0
T11	105576	5792	0	0
T12	556670	151	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	891422	0	0
T1	7879	246	0	0
T2	10981	854	0	0
T3	442005	57	0	0
T4	125275	1516	0	0
T7	57082	360	0	0
T8	429867	43	0	0
T9	8609	608	0	0
T10	3899	208	0	0
T11	105576	5792	0	0
T12	556670	151	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	891422	0	0
T1	7879	246	0	0
T2	10981	854	0	0
T3	442005	57	0	0
T4	125275	1516	0	0
T7	57082	360	0	0
T8	429867	43	0	0
T9	8609	608	0	0
T10	3899	208	0	0
T11	105576	5792	0	0
T12	556670	151	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	11660217	0	0
T1	7879	203	0	0
T2	10981	601	0	0
T3	442005	243	0	0
T4	125275	7149	0	0
T7	57082	2752	0	0
T8	429867	12917	0	0
T9	8609	451	0	0
T10	3899	167	0	0
T11	105576	3448	0	0
T12	556670	43855	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	891422	0	0
T1	7879	246	0	0
T2	10981	854	0	0
T3	442005	57	0	0
T4	125275	1516	0	0
T7	57082	360	0	0
T8	429867	43	0	0
T9	8609	608	0	0
T10	3899	208	0	0
T11	105576	5792	0	0
T12	556670	151	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	891422	0	0
T1	7879	246	0	0
T2	10981	854	0	0
T3	442005	57	0	0
T4	125275	1516	0	0
T7	57082	360	0	0
T8	429867	43	0	0
T9	8609	608	0	0
T10	3899	208	0	0
T11	105576	5792	0	0
T12	556670	151	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2474502	0	0
T1	7879	290	0	0
T2	10981	1108	0	0
T3	442005	89	0	0
T4	125275	4103	0	0
T7	57082	534	0	0
T8	429867	1469	0	0
T9	8609	766	0	0
T10	3899	250	0	0
T11	105576	8137	0	0
T12	556670	4628	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	891422	0	0
T1	7879	246	0	0
T2	10981	854	0	0
T3	442005	57	0	0
T4	125275	1516	0	0
T7	57082	360	0	0
T8	429867	43	0	0
T9	8609	608	0	0
T10	3899	208	0	0
T11	105576	5792	0	0
T12	556670	151	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	218745	0	0
GntImpliesValid_A	415429174	218745	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	218745	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2926868	0	0
ReadyAndValidImplyGrant_A	415429174	218745	0	0
ReqAndReadyImplyGrant_A	415429174	218745	0	0
ReqImpliesValid_A	415429174	533292	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	218745	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	218745	0	0
T1	7879	65	0	0
T2	10981	225	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	14	0	0
T9	8609	144	0	0
T10	3899	59	0	0
T11	105576	617	0	0
T12	556670	34	0	0
T13	0	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	218745	0	0
T1	7879	65	0	0
T2	10981	225	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	14	0	0
T9	8609	144	0	0
T10	3899	59	0	0
T11	105576	617	0	0
T12	556670	34	0	0
T13	0	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	218745	0	0
T1	7879	65	0	0
T2	10981	225	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	14	0	0
T9	8609	144	0	0
T10	3899	59	0	0
T11	105576	617	0	0
T12	556670	34	0	0
T13	0	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2926868	0	0
T1	7879	66	0	0
T2	10981	209	0	0
T3	442005	50	0	0
T4	125275	1	0	0
T7	57082	735	0	0
T8	429867	5992	0	0
T9	8609	139	0	0
T10	3899	56	0	0
T11	105576	606	0	0
T12	556670	12954	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	218745	0	0
T1	7879	65	0	0
T2	10981	225	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	14	0	0
T9	8609	144	0	0
T10	3899	59	0	0
T11	105576	617	0	0
T12	556670	34	0	0
T13	0	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	218745	0	0
T1	7879	65	0	0
T2	10981	225	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	14	0	0
T9	8609	144	0	0
T10	3899	59	0	0
T11	105576	617	0	0
T12	556670	34	0	0
T13	0	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	533292	0	0
T1	7879	65	0	0
T2	10981	242	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	149	0	0
T8	429867	14	0	0
T9	8609	150	0	0
T10	3899	63	0	0
T11	105576	629	0	0
T12	556670	368	0	0
T13	0	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	218745	0	0
T1	7879	65	0	0
T2	10981	225	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	14	0	0
T9	8609	144	0	0
T10	3899	59	0	0
T11	105576	617	0	0
T12	556670	34	0	0
T13	0	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	228599	0	0
GntImpliesValid_A	415429174	228599	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	228599	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2942968	0	0
ReadyAndValidImplyGrant_A	415429174	228599	0	0
ReqAndReadyImplyGrant_A	415429174	228599	0	0
ReqImpliesValid_A	415429174	559350	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	228599	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	228599	0	0
T1	7879	76	0	0
T2	10981	165	0	0
T3	442005	28	0	0
T4	125275	562	0	0
T7	57082	101	0	0
T8	429867	12	0	0
T9	8609	130	0	0
T10	3899	62	0	0
T11	105576	1102	0	0
T12	556670	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	228599	0	0
T1	7879	76	0	0
T2	10981	165	0	0
T3	442005	28	0	0
T4	125275	562	0	0
T7	57082	101	0	0
T8	429867	12	0	0
T9	8609	130	0	0
T10	3899	62	0	0
T11	105576	1102	0	0
T12	556670	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	228599	0	0
T1	7879	76	0	0
T2	10981	165	0	0
T3	442005	28	0	0
T4	125275	562	0	0
T7	57082	101	0	0
T8	429867	12	0	0
T9	8609	130	0	0
T10	3899	62	0	0
T11	105576	1102	0	0
T12	556670	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2942968	0	0
T1	7879	76	0	0
T2	10981	161	0	0
T3	442005	125	0	0
T4	125275	454	0	0
T7	57082	778	0	0
T8	429867	4188	0	0
T9	8609	125	0	0
T10	3899	58	0	0
T11	105576	1001	0	0
T12	556670	12552	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	228599	0	0
T1	7879	76	0	0
T2	10981	165	0	0
T3	442005	28	0	0
T4	125275	562	0	0
T7	57082	101	0	0
T8	429867	12	0	0
T9	8609	130	0	0
T10	3899	62	0	0
T11	105576	1102	0	0
T12	556670	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	228599	0	0
T1	7879	76	0	0
T2	10981	165	0	0
T3	442005	28	0	0
T4	125275	562	0	0
T7	57082	101	0	0
T8	429867	12	0	0
T9	8609	130	0	0
T10	3899	62	0	0
T11	105576	1102	0	0
T12	556670	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	559350	0	0
T1	7879	77	0	0
T2	10981	170	0	0
T3	442005	48	0	0
T4	125275	5909	0	0
T7	57082	132	0	0
T8	429867	96	0	0
T9	8609	136	0	0
T10	3899	67	0	0
T11	105576	1204	0	0
T12	556670	980	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	228599	0	0
T1	7879	76	0	0
T2	10981	165	0	0
T3	442005	28	0	0
T4	125275	562	0	0
T7	57082	101	0	0
T8	429867	12	0	0
T9	8609	130	0	0
T10	3899	62	0	0
T11	105576	1102	0	0
T12	556670	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	220955	0	0
GntImpliesValid_A	415429174	220955	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	220955	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	5507030	0	0
ReadyAndValidImplyGrant_A	415429174	220955	0	0
ReqAndReadyImplyGrant_A	415429174	220955	0	0
ReqImpliesValid_A	415429174	1212567	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	220955	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	220955	0	0
T1	7879	61	0	0
T2	10981	211	0	0
T3	442005	19	0	0
T4	125275	329	0	0
T7	57082	125	0	0
T8	429867	21	0	0
T9	8609	134	0	0
T10	3899	60	0	0
T11	105576	1544	0	0
T12	556670	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	220955	0	0
T1	7879	61	0	0
T2	10981	211	0	0
T3	442005	19	0	0
T4	125275	329	0	0
T7	57082	125	0	0
T8	429867	21	0	0
T9	8609	134	0	0
T10	3899	60	0	0
T11	105576	1544	0	0
T12	556670	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	220955	0	0
T1	7879	61	0	0
T2	10981	211	0	0
T3	442005	19	0	0
T4	125275	329	0	0
T7	57082	125	0	0
T8	429867	21	0	0
T9	8609	134	0	0
T10	3899	60	0	0
T11	105576	1544	0	0
T12	556670	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	5507030	0	0
T1	7879	277	0	0
T2	10981	624	0	0
T3	442005	196	0	0
T4	125275	1839	0	0
T7	57082	1629	0	0
T8	429867	2036	0	0
T9	8609	664	0	0
T10	3899	277	0	0
T11	105576	5797	0	0
T12	556670	53360	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	220955	0	0
T1	7879	61	0	0
T2	10981	211	0	0
T3	442005	19	0	0
T4	125275	329	0	0
T7	57082	125	0	0
T8	429867	21	0	0
T9	8609	134	0	0
T10	3899	60	0	0
T11	105576	1544	0	0
T12	556670	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	220955	0	0
T1	7879	61	0	0
T2	10981	211	0	0
T3	442005	19	0	0
T4	125275	329	0	0
T7	57082	125	0	0
T8	429867	21	0	0
T9	8609	134	0	0
T10	3899	60	0	0
T11	105576	1544	0	0
T12	556670	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	1212567	0	0
T1	7879	114	0	0
T2	10981	326	0	0
T3	442005	31	0	0
T4	125275	12114	0	0
T7	57082	221	0	0
T8	429867	21	0	0
T9	8609	236	0	0
T10	3899	117	0	0
T11	105576	8042	0	0
T12	556670	8660	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	220955	0	0
T1	7879	61	0	0
T2	10981	211	0	0
T3	442005	19	0	0
T4	125275	329	0	0
T7	57082	125	0	0
T8	429867	21	0	0
T9	8609	134	0	0
T10	3899	60	0	0
T11	105576	1544	0	0
T12	556670	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	210648	0	0
GntImpliesValid_A	415429174	210648	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	210648	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	5058178	0	0
ReadyAndValidImplyGrant_A	415429174	210648	0	0
ReqAndReadyImplyGrant_A	415429174	210648	0	0
ReqImpliesValid_A	415429174	1071907	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	210648	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210648	0	0
T1	7879	64	0	0
T2	10981	235	0	0
T3	442005	15	0	0
T4	125275	487	0	0
T7	57082	106	0	0
T8	429867	18	0	0
T9	8609	144	0	0
T10	3899	62	0	0
T11	105576	573	0	0
T12	556670	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210648	0	0
T1	7879	64	0	0
T2	10981	235	0	0
T3	442005	15	0	0
T4	125275	487	0	0
T7	57082	106	0	0
T8	429867	18	0	0
T9	8609	144	0	0
T10	3899	62	0	0
T11	105576	573	0	0
T12	556670	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210648	0	0
T1	7879	64	0	0
T2	10981	235	0	0
T3	442005	15	0	0
T4	125275	487	0	0
T7	57082	106	0	0
T8	429867	18	0	0
T9	8609	144	0	0
T10	3899	62	0	0
T11	105576	573	0	0
T12	556670	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	5058178	0	0
T1	7879	1526	0	0
T2	10981	743	0	0
T3	442005	173	0	0
T4	125275	348	0	0
T7	57082	1593	0	0
T8	429867	5803	0	0
T9	8609	727	0	0
T10	3899	307	0	0
T11	105576	3519	0	0
T12	556670	6595	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210648	0	0
T1	7879	64	0	0
T2	10981	235	0	0
T3	442005	15	0	0
T4	125275	487	0	0
T7	57082	106	0	0
T8	429867	18	0	0
T9	8609	144	0	0
T10	3899	62	0	0
T11	105576	573	0	0
T12	556670	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210648	0	0
T1	7879	64	0	0
T2	10981	235	0	0
T3	442005	15	0	0
T4	125275	487	0	0
T7	57082	106	0	0
T8	429867	18	0	0
T9	8609	144	0	0
T10	3899	62	0	0
T11	105576	573	0	0
T12	556670	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	1071907	0	0
T1	7879	236	0	0
T2	10981	310	0	0
T3	442005	15	0	0
T4	125275	6291	0	0
T7	57082	194	0	0
T8	429867	715	0	0
T9	8609	212	0	0
T10	3899	93	0	0
T11	105576	719	0	0
T12	556670	177	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210648	0	0
T1	7879	64	0	0
T2	10981	235	0	0
T3	442005	15	0	0
T4	125275	487	0	0
T7	57082	106	0	0
T8	429867	18	0	0
T9	8609	144	0	0
T10	3899	62	0	0
T11	105576	573	0	0
T12	556670	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	213874	0	0
GntImpliesValid_A	415429174	213874	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	213874	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	5055265	0	0
ReadyAndValidImplyGrant_A	415429174	213874	0	0
ReqAndReadyImplyGrant_A	415429174	213874	0	0
ReqImpliesValid_A	415429174	1082642	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	213874	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213874	0	0
T1	7879	58	0	0
T2	10981	193	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	18	0	0
T9	8609	133	0	0
T10	3899	65	0	0
T11	105576	2039	0	0
T12	556670	36	0	0
T13	0	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213874	0	0
T1	7879	58	0	0
T2	10981	193	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	18	0	0
T9	8609	133	0	0
T10	3899	65	0	0
T11	105576	2039	0	0
T12	556670	36	0	0
T13	0	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213874	0	0
T1	7879	58	0	0
T2	10981	193	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	18	0	0
T9	8609	133	0	0
T10	3899	65	0	0
T11	105576	2039	0	0
T12	556670	36	0	0
T13	0	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	5055265	0	0
T1	7879	376	0	0
T2	10981	594	0	0
T3	442005	291	0	0
T4	125275	0	0	0
T7	57082	2809	0	0
T8	429867	3507	0	0
T9	8609	987	0	0
T10	3899	303	0	0
T11	105576	5866	0	0
T12	556670	30797	0	0
T13	0	225	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213874	0	0
T1	7879	58	0	0
T2	10981	193	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	18	0	0
T9	8609	133	0	0
T10	3899	65	0	0
T11	105576	2039	0	0
T12	556670	36	0	0
T13	0	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213874	0	0
T1	7879	58	0	0
T2	10981	193	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	18	0	0
T9	8609	133	0	0
T10	3899	65	0	0
T11	105576	2039	0	0
T12	556670	36	0	0
T13	0	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	1082642	0	0
T1	7879	96	0	0
T2	10981	267	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	158	0	0
T8	429867	309	0	0
T9	8609	262	0	0
T10	3899	99	0	0
T11	105576	12345	0	0
T12	556670	2298	0	0
T13	0	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213874	0	0
T1	7879	58	0	0
T2	10981	193	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	100	0	0
T8	429867	18	0	0
T9	8609	133	0	0
T10	3899	65	0	0
T11	105576	2039	0	0
T12	556670	36	0	0
T13	0	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	207503	0	0
GntImpliesValid_A	415429174	207503	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	207503	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	4800027	0	0
ReadyAndValidImplyGrant_A	415429174	207503	0	0
ReqAndReadyImplyGrant_A	415429174	207503	0	0
ReqImpliesValid_A	415429174	1022929	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	207503	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	207503	0	0
T1	7879	72	0	0
T2	10981	195	0	0
T3	442005	14	0	0
T4	125275	407	0	0
T7	57082	105	0	0
T8	429867	7	0	0
T9	8609	112	0	0
T10	3899	62	0	0
T11	105576	1716	0	0
T12	556670	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	207503	0	0
T1	7879	72	0	0
T2	10981	195	0	0
T3	442005	14	0	0
T4	125275	407	0	0
T7	57082	105	0	0
T8	429867	7	0	0
T9	8609	112	0	0
T10	3899	62	0	0
T11	105576	1716	0	0
T12	556670	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	207503	0	0
T1	7879	72	0	0
T2	10981	195	0	0
T3	442005	14	0	0
T4	125275	407	0	0
T7	57082	105	0	0
T8	429867	7	0	0
T9	8609	112	0	0
T10	3899	62	0	0
T11	105576	1716	0	0
T12	556670	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	4800027	0	0
T1	7879	1022	0	0
T2	10981	784	0	0
T3	442005	225	0	0
T4	125275	644	0	0
T7	57082	1381	0	0
T8	429867	593	0	0
T9	8609	533	0	0
T10	3899	255	0	0
T11	105576	5843	0	0
T12	556670	14661	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	207503	0	0
T1	7879	72	0	0
T2	10981	195	0	0
T3	442005	14	0	0
T4	125275	407	0	0
T7	57082	105	0	0
T8	429867	7	0	0
T9	8609	112	0	0
T10	3899	62	0	0
T11	105576	1716	0	0
T12	556670	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	207503	0	0
T1	7879	72	0	0
T2	10981	195	0	0
T3	442005	14	0	0
T4	125275	407	0	0
T7	57082	105	0	0
T8	429867	7	0	0
T9	8609	112	0	0
T10	3899	62	0	0
T11	105576	1716	0	0
T12	556670	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	1022929	0	0
T1	7879	306	0	0
T2	10981	301	0	0
T3	442005	40	0	0
T4	125275	5885	0	0
T7	57082	170	0	0
T8	429867	190	0	0
T9	8609	164	0	0
T10	3899	88	0	0
T11	105576	5191	0	0
T12	556670	993	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	207503	0	0
T1	7879	72	0	0
T2	10981	195	0	0
T3	442005	14	0	0
T4	125275	407	0	0
T7	57082	105	0	0
T8	429867	7	0	0
T9	8609	112	0	0
T10	3899	62	0	0
T11	105576	1716	0	0
T12	556670	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	219165	0	0
GntImpliesValid_A	415429174	219165	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	219165	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2877088	0	0
ReadyAndValidImplyGrant_A	415429174	219165	0	0
ReqAndReadyImplyGrant_A	415429174	219165	0	0
ReqImpliesValid_A	415429174	526023	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	219165	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219165	0	0
T1	7879	55	0	0
T2	10981	195	0	0
T3	442005	18	0	0
T4	125275	996	0	0
T7	57082	94	0	0
T8	429867	13	0	0
T9	8609	129	0	0
T10	3899	72	0	0
T11	105576	539	0	0
T12	556670	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219165	0	0
T1	7879	55	0	0
T2	10981	195	0	0
T3	442005	18	0	0
T4	125275	996	0	0
T7	57082	94	0	0
T8	429867	13	0	0
T9	8609	129	0	0
T10	3899	72	0	0
T11	105576	539	0	0
T12	556670	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219165	0	0
T1	7879	55	0	0
T2	10981	195	0	0
T3	442005	18	0	0
T4	125275	996	0	0
T7	57082	94	0	0
T8	429867	13	0	0
T9	8609	129	0	0
T10	3899	72	0	0
T11	105576	539	0	0
T12	556670	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2877088	0	0
T1	7879	54	0	0
T2	10981	189	0	0
T3	442005	76	0	0
T4	125275	1382	0	0
T7	57082	789	0	0
T8	429867	5490	0	0
T9	8609	123	0	0
T10	3899	66	0	0
T11	105576	528	0	0
T12	556670	11106	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219165	0	0
T1	7879	55	0	0
T2	10981	195	0	0
T3	442005	18	0	0
T4	125275	996	0	0
T7	57082	94	0	0
T8	429867	13	0	0
T9	8609	129	0	0
T10	3899	72	0	0
T11	105576	539	0	0
T12	556670	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219165	0	0
T1	7879	55	0	0
T2	10981	195	0	0
T3	442005	18	0	0
T4	125275	996	0	0
T7	57082	94	0	0
T8	429867	13	0	0
T9	8609	129	0	0
T10	3899	72	0	0
T11	105576	539	0	0
T12	556670	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	526023	0	0
T1	7879	57	0	0
T2	10981	202	0	0
T3	442005	25	0	0
T4	125275	10268	0	0
T7	57082	115	0	0
T8	429867	13	0	0
T9	8609	136	0	0
T10	3899	79	0	0
T11	105576	551	0	0
T12	556670	1440	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219165	0	0
T1	7879	55	0	0
T2	10981	195	0	0
T3	442005	18	0	0
T4	125275	996	0	0
T7	57082	94	0	0
T8	429867	13	0	0
T9	8609	129	0	0
T10	3899	72	0	0
T11	105576	539	0	0
T12	556670	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	224102	0	0
GntImpliesValid_A	415429174	224102	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	224102	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2935576	0	0
ReadyAndValidImplyGrant_A	415429174	224102	0	0
ReqAndReadyImplyGrant_A	415429174	224102	0	0
ReqImpliesValid_A	415429174	585817	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	224102	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	224102	0	0
T1	7879	74	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	94	0	0
T8	429867	16	0	0
T9	8609	153	0	0
T10	3899	58	0	0
T11	105576	1113	0	0
T12	556670	44	0	0
T13	0	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	224102	0	0
T1	7879	74	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	94	0	0
T8	429867	16	0	0
T9	8609	153	0	0
T10	3899	58	0	0
T11	105576	1113	0	0
T12	556670	44	0	0
T13	0	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	224102	0	0
T1	7879	74	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	94	0	0
T8	429867	16	0	0
T9	8609	153	0	0
T10	3899	58	0	0
T11	105576	1113	0	0
T12	556670	44	0	0
T13	0	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2935576	0	0
T1	7879	72	0	0
T2	10981	198	0	0
T3	442005	60	0	0
T4	125275	1	0	0
T7	57082	667	0	0
T8	429867	6135	0	0
T9	8609	146	0	0
T10	3899	55	0	0
T11	105576	548	0	0
T12	556670	16912	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	224102	0	0
T1	7879	74	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	94	0	0
T8	429867	16	0	0
T9	8609	153	0	0
T10	3899	58	0	0
T11	105576	1113	0	0
T12	556670	44	0	0
T13	0	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	224102	0	0
T1	7879	74	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	94	0	0
T8	429867	16	0	0
T9	8609	153	0	0
T10	3899	58	0	0
T11	105576	1113	0	0
T12	556670	44	0	0
T13	0	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	585817	0	0
T1	7879	77	0	0
T2	10981	219	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	102	0	0
T8	429867	550	0	0
T9	8609	161	0	0
T10	3899	62	0	0
T11	105576	1679	0	0
T12	556670	146	0	0
T13	0	54	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	224102	0	0
T1	7879	74	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	94	0	0
T8	429867	16	0	0
T9	8609	153	0	0
T10	3899	58	0	0
T11	105576	1113	0	0
T12	556670	44	0	0
T13	0	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	222815	0	0
GntImpliesValid_A	415429174	222815	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	222815	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2934008	0	0
ReadyAndValidImplyGrant_A	415429174	222815	0	0
ReqAndReadyImplyGrant_A	415429174	222815	0	0
ReqImpliesValid_A	415429174	560003	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	222815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	222815	0	0
T1	7879	61	0	0
T2	10981	187	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	91	0	0
T8	429867	19	0	0
T9	8609	122	0	0
T10	3899	79	0	0
T11	105576	1124	0	0
T12	556670	33	0	0
T13	0	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	222815	0	0
T1	7879	61	0	0
T2	10981	187	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	91	0	0
T8	429867	19	0	0
T9	8609	122	0	0
T10	3899	79	0	0
T11	105576	1124	0	0
T12	556670	33	0	0
T13	0	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	222815	0	0
T1	7879	61	0	0
T2	10981	187	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	91	0	0
T8	429867	19	0	0
T9	8609	122	0	0
T10	3899	79	0	0
T11	105576	1124	0	0
T12	556670	33	0	0
T13	0	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2934008	0	0
T1	7879	62	0	0
T2	10981	179	0	0
T3	442005	88	0	0
T4	125275	1	0	0
T7	57082	659	0	0
T8	429867	5995	0	0
T9	8609	118	0	0
T10	3899	71	0	0
T11	105576	1005	0	0
T12	556670	10645	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	222815	0	0
T1	7879	61	0	0
T2	10981	187	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	91	0	0
T8	429867	19	0	0
T9	8609	122	0	0
T10	3899	79	0	0
T11	105576	1124	0	0
T12	556670	33	0	0
T13	0	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	222815	0	0
T1	7879	61	0	0
T2	10981	187	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	91	0	0
T8	429867	19	0	0
T9	8609	122	0	0
T10	3899	79	0	0
T11	105576	1124	0	0
T12	556670	33	0	0
T13	0	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	560003	0	0
T1	7879	61	0	0
T2	10981	196	0	0
T3	442005	19	0	0
T4	125275	0	0	0
T7	57082	112	0	0
T8	429867	19	0	0
T9	8609	127	0	0
T10	3899	88	0	0
T11	105576	1244	0	0
T12	556670	602	0	0
T13	0	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	222815	0	0
T1	7879	61	0	0
T2	10981	187	0	0
T3	442005	18	0	0
T4	125275	0	0	0
T7	57082	91	0	0
T8	429867	19	0	0
T9	8609	122	0	0
T10	3899	79	0	0
T11	105576	1124	0	0
T12	556670	33	0	0
T13	0	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	215112	0	0
GntImpliesValid_A	415429174	215112	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	215112	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2980740	0	0
ReadyAndValidImplyGrant_A	415429174	215112	0	0
ReqAndReadyImplyGrant_A	415429174	215112	0	0
ReqImpliesValid_A	415429174	531969	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	215112	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	215112	0	0
T1	7879	71	0	0
T2	10981	216	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	88	0	0
T8	429867	20	0	0
T9	8609	166	0	0
T10	3899	72	0	0
T11	105576	1098	0	0
T12	556670	28	0	0
T13	0	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	215112	0	0
T1	7879	71	0	0
T2	10981	216	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	88	0	0
T8	429867	20	0	0
T9	8609	166	0	0
T10	3899	72	0	0
T11	105576	1098	0	0
T12	556670	28	0	0
T13	0	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	215112	0	0
T1	7879	71	0	0
T2	10981	216	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	88	0	0
T8	429867	20	0	0
T9	8609	166	0	0
T10	3899	72	0	0
T11	105576	1098	0	0
T12	556670	28	0	0
T13	0	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2980740	0	0
T1	7879	70	0	0
T2	10981	193	0	0
T3	442005	75	0	0
T4	125275	1	0	0
T7	57082	538	0	0
T8	429867	6665	0	0
T9	8609	156	0	0
T10	3899	70	0	0
T11	105576	725	0	0
T12	556670	10554	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	215112	0	0
T1	7879	71	0	0
T2	10981	216	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	88	0	0
T8	429867	20	0	0
T9	8609	166	0	0
T10	3899	72	0	0
T11	105576	1098	0	0
T12	556670	28	0	0
T13	0	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	215112	0	0
T1	7879	71	0	0
T2	10981	216	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	88	0	0
T8	429867	20	0	0
T9	8609	166	0	0
T10	3899	72	0	0
T11	105576	1098	0	0
T12	556670	28	0	0
T13	0	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	531969	0	0
T1	7879	73	0	0
T2	10981	240	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	125	0	0
T8	429867	1720	0	0
T9	8609	177	0	0
T10	3899	75	0	0
T11	105576	1472	0	0
T12	556670	947	0	0
T13	0	58	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	215112	0	0
T1	7879	71	0	0
T2	10981	216	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	88	0	0
T8	429867	20	0	0
T9	8609	166	0	0
T10	3899	72	0	0
T11	105576	1098	0	0
T12	556670	28	0	0
T13	0	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	206475	0	0
GntImpliesValid_A	415429174	206475	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	206475	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	3022851	0	0
ReadyAndValidImplyGrant_A	415429174	206475	0	0
ReqAndReadyImplyGrant_A	415429174	206475	0	0
ReqImpliesValid_A	415429174	535943	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	206475	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	206475	0	0
T1	7879	85	0	0
T2	10981	217	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	99	0	0
T8	429867	11	0	0
T9	8609	156	0	0
T10	3899	49	0	0
T11	105576	1509	0	0
T12	556670	30	0	0
T13	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	206475	0	0
T1	7879	85	0	0
T2	10981	217	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	99	0	0
T8	429867	11	0	0
T9	8609	156	0	0
T10	3899	49	0	0
T11	105576	1509	0	0
T12	556670	30	0	0
T13	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	206475	0	0
T1	7879	85	0	0
T2	10981	217	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	99	0	0
T8	429867	11	0	0
T9	8609	156	0	0
T10	3899	49	0	0
T11	105576	1509	0	0
T12	556670	30	0	0
T13	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	3022851	0	0
T1	7879	84	0	0
T2	10981	210	0	0
T3	442005	77	0	0
T4	125275	1	0	0
T7	57082	647	0	0
T8	429867	3394	0	0
T9	8609	149	0	0
T10	3899	48	0	0
T11	105576	947	0	0
T12	556670	10194	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	206475	0	0
T1	7879	85	0	0
T2	10981	217	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	99	0	0
T8	429867	11	0	0
T9	8609	156	0	0
T10	3899	49	0	0
T11	105576	1509	0	0
T12	556670	30	0	0
T13	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	206475	0	0
T1	7879	85	0	0
T2	10981	217	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	99	0	0
T8	429867	11	0	0
T9	8609	156	0	0
T10	3899	49	0	0
T11	105576	1509	0	0
T12	556670	30	0	0
T13	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	535943	0	0
T1	7879	87	0	0
T2	10981	225	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	130	0	0
T8	429867	498	0	0
T9	8609	164	0	0
T10	3899	51	0	0
T11	105576	2072	0	0
T12	556670	113	0	0
T13	0	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	206475	0	0
T1	7879	85	0	0
T2	10981	217	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	99	0	0
T8	429867	11	0	0
T9	8609	156	0	0
T10	3899	49	0	0
T11	105576	1509	0	0
T12	556670	30	0	0
T13	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	210044	0	0
GntImpliesValid_A	415429174	210044	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	210044	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2919885	0	0
ReadyAndValidImplyGrant_A	415429174	210044	0	0
ReqAndReadyImplyGrant_A	415429174	210044	0	0
ReqImpliesValid_A	415429174	526642	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	210044	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210044	0	0
T1	7879	71	0	0
T2	10981	188	0	0
T3	442005	11	0	0
T4	125275	416	0	0
T7	57082	89	0	0
T8	429867	11	0	0
T9	8609	155	0	0
T10	3899	57	0	0
T11	105576	607	0	0
T12	556670	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210044	0	0
T1	7879	71	0	0
T2	10981	188	0	0
T3	442005	11	0	0
T4	125275	416	0	0
T7	57082	89	0	0
T8	429867	11	0	0
T9	8609	155	0	0
T10	3899	57	0	0
T11	105576	607	0	0
T12	556670	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210044	0	0
T1	7879	71	0	0
T2	10981	188	0	0
T3	442005	11	0	0
T4	125275	416	0	0
T7	57082	89	0	0
T8	429867	11	0	0
T9	8609	155	0	0
T10	3899	57	0	0
T11	105576	607	0	0
T12	556670	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2919885	0	0
T1	7879	70	0	0
T2	10981	180	0	0
T3	442005	52	0	0
T4	125275	883	0	0
T7	57082	657	0	0
T8	429867	3250	0	0
T9	8609	143	0	0
T10	3899	58	0	0
T11	105576	595	0	0
T12	556670	10186	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210044	0	0
T1	7879	71	0	0
T2	10981	188	0	0
T3	442005	11	0	0
T4	125275	416	0	0
T7	57082	89	0	0
T8	429867	11	0	0
T9	8609	155	0	0
T10	3899	57	0	0
T11	105576	607	0	0
T12	556670	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210044	0	0
T1	7879	71	0	0
T2	10981	188	0	0
T3	442005	11	0	0
T4	125275	416	0	0
T7	57082	89	0	0
T8	429867	11	0	0
T9	8609	155	0	0
T10	3899	57	0	0
T11	105576	607	0	0
T12	556670	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	526642	0	0
T1	7879	73	0	0
T2	10981	197	0	0
T3	442005	11	0	0
T4	125275	3948	0	0
T7	57082	122	0	0
T8	429867	11	0	0
T9	8609	168	0	0
T10	3899	57	0	0
T11	105576	620	0	0
T12	556670	863	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	210044	0	0
T1	7879	71	0	0
T2	10981	188	0	0
T3	442005	11	0	0
T4	125275	416	0	0
T7	57082	89	0	0
T8	429867	11	0	0
T9	8609	155	0	0
T10	3899	57	0	0
T11	105576	607	0	0
T12	556670	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	221374	0	0
GntImpliesValid_A	415429174	221374	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	221374	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2929643	0	0
ReadyAndValidImplyGrant_A	415429174	221374	0	0
ReqAndReadyImplyGrant_A	415429174	221374	0	0
ReqImpliesValid_A	415429174	523624	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	221374	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	221374	0	0
T1	7879	63	0	0
T2	10981	210	0	0
T3	442005	10	0	0
T4	125275	386	0	0
T7	57082	91	0	0
T8	429867	10	0	0
T9	8609	116	0	0
T10	3899	57	0	0
T11	105576	2138	0	0
T12	556670	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	221374	0	0
T1	7879	63	0	0
T2	10981	210	0	0
T3	442005	10	0	0
T4	125275	386	0	0
T7	57082	91	0	0
T8	429867	10	0	0
T9	8609	116	0	0
T10	3899	57	0	0
T11	105576	2138	0	0
T12	556670	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	221374	0	0
T1	7879	63	0	0
T2	10981	210	0	0
T3	442005	10	0	0
T4	125275	386	0	0
T7	57082	91	0	0
T8	429867	10	0	0
T9	8609	116	0	0
T10	3899	57	0	0
T11	105576	2138	0	0
T12	556670	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2929643	0	0
T1	7879	63	0	0
T2	10981	200	0	0
T3	442005	49	0	0
T4	125275	779	0	0
T7	57082	606	0	0
T8	429867	3653	0	0
T9	8609	111	0	0
T10	3899	54	0	0
T11	105576	1515	0	0
T12	556670	10319	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	221374	0	0
T1	7879	63	0	0
T2	10981	210	0	0
T3	442005	10	0	0
T4	125275	386	0	0
T7	57082	91	0	0
T8	429867	10	0	0
T9	8609	116	0	0
T10	3899	57	0	0
T11	105576	2138	0	0
T12	556670	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	221374	0	0
T1	7879	63	0	0
T2	10981	210	0	0
T3	442005	10	0	0
T4	125275	386	0	0
T7	57082	91	0	0
T8	429867	10	0	0
T9	8609	116	0	0
T10	3899	57	0	0
T11	105576	2138	0	0
T12	556670	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	523624	0	0
T1	7879	64	0	0
T2	10981	221	0	0
T3	442005	10	0	0
T4	125275	3703	0	0
T7	57082	91	0	0
T8	429867	10	0	0
T9	8609	122	0	0
T10	3899	61	0	0
T11	105576	2762	0	0
T12	556670	1813	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	221374	0	0
T1	7879	63	0	0
T2	10981	210	0	0
T3	442005	10	0	0
T4	125275	386	0	0
T7	57082	91	0	0
T8	429867	10	0	0
T9	8609	116	0	0
T10	3899	57	0	0
T11	105576	2138	0	0
T12	556670	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	219112	0	0
GntImpliesValid_A	415429174	219112	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	219112	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2894872	0	0
ReadyAndValidImplyGrant_A	415429174	219112	0	0
ReqAndReadyImplyGrant_A	415429174	219112	0	0
ReqImpliesValid_A	415429174	572843	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	219112	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219112	0	0
T1	7879	71	0	0
T2	10981	205	0	0
T3	442005	14	0	0
T4	125275	547	0	0
T7	57082	94	0	0
T8	429867	10	0	0
T9	8609	138	0	0
T10	3899	59	0	0
T11	105576	1412	0	0
T12	556670	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219112	0	0
T1	7879	71	0	0
T2	10981	205	0	0
T3	442005	14	0	0
T4	125275	547	0	0
T7	57082	94	0	0
T8	429867	10	0	0
T9	8609	138	0	0
T10	3899	59	0	0
T11	105576	1412	0	0
T12	556670	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219112	0	0
T1	7879	71	0	0
T2	10981	205	0	0
T3	442005	14	0	0
T4	125275	547	0	0
T7	57082	94	0	0
T8	429867	10	0	0
T9	8609	138	0	0
T10	3899	59	0	0
T11	105576	1412	0	0
T12	556670	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2894872	0	0
T1	7879	69	0	0
T2	10981	190	0	0
T3	442005	48	0	0
T4	125275	673	0	0
T7	57082	779	0	0
T8	429867	3656	0	0
T9	8609	131	0	0
T10	3899	58	0	0
T11	105576	796	0	0
T12	556670	15828	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219112	0	0
T1	7879	71	0	0
T2	10981	205	0	0
T3	442005	14	0	0
T4	125275	547	0	0
T7	57082	94	0	0
T8	429867	10	0	0
T9	8609	138	0	0
T10	3899	59	0	0
T11	105576	1412	0	0
T12	556670	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219112	0	0
T1	7879	71	0	0
T2	10981	205	0	0
T3	442005	14	0	0
T4	125275	547	0	0
T7	57082	94	0	0
T8	429867	10	0	0
T9	8609	138	0	0
T10	3899	59	0	0
T11	105576	1412	0	0
T12	556670	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	572843	0	0
T1	7879	74	0	0
T2	10981	221	0	0
T3	442005	17	0	0
T4	125275	5558	0	0
T7	57082	110	0	0
T8	429867	19	0	0
T9	8609	146	0	0
T10	3899	61	0	0
T11	105576	2029	0	0
T12	556670	915	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	219112	0	0
T1	7879	71	0	0
T2	10981	205	0	0
T3	442005	14	0	0
T4	125275	547	0	0
T7	57082	94	0	0
T8	429867	10	0	0
T9	8609	138	0	0
T10	3899	59	0	0
T11	105576	1412	0	0
T12	556670	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	232579	0	0
GntImpliesValid_A	415429174	232579	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	232579	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2947929	0	0
ReadyAndValidImplyGrant_A	415429174	232579	0	0
ReqAndReadyImplyGrant_A	415429174	232579	0	0
ReqImpliesValid_A	415429174	559332	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	232579	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	232579	0	0
T1	7879	103	0	0
T2	10981	214	0	0
T3	442005	19	0	0
T4	125275	481	0	0
T7	57082	174	0	0
T8	429867	22	0	0
T9	8609	157	0	0
T10	3899	64	0	0
T11	105576	1120	0	0
T12	556670	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	232579	0	0
T1	7879	103	0	0
T2	10981	214	0	0
T3	442005	19	0	0
T4	125275	481	0	0
T7	57082	174	0	0
T8	429867	22	0	0
T9	8609	157	0	0
T10	3899	64	0	0
T11	105576	1120	0	0
T12	556670	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	232579	0	0
T1	7879	103	0	0
T2	10981	214	0	0
T3	442005	19	0	0
T4	125275	481	0	0
T7	57082	174	0	0
T8	429867	22	0	0
T9	8609	157	0	0
T10	3899	64	0	0
T11	105576	1120	0	0
T12	556670	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2947929	0	0
T1	7879	99	0	0
T2	10981	201	0	0
T3	442005	95	0	0
T4	125275	1035	0	0
T7	57082	1327	0	0
T8	429867	9232	0	0
T9	8609	151	0	0
T10	3899	61	0	0
T11	105576	977	0	0
T12	556670	13999	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	232579	0	0
T1	7879	103	0	0
T2	10981	214	0	0
T3	442005	19	0	0
T4	125275	481	0	0
T7	57082	174	0	0
T8	429867	22	0	0
T9	8609	157	0	0
T10	3899	64	0	0
T11	105576	1120	0	0
T12	556670	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	232579	0	0
T1	7879	103	0	0
T2	10981	214	0	0
T3	442005	19	0	0
T4	125275	481	0	0
T7	57082	174	0	0
T8	429867	22	0	0
T9	8609	157	0	0
T10	3899	64	0	0
T11	105576	1120	0	0
T12	556670	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	559332	0	0
T1	7879	108	0	0
T2	10981	228	0	0
T3	442005	25	0	0
T4	125275	1953	0	0
T7	57082	245	0	0
T8	429867	1380	0	0
T9	8609	164	0	0
T10	3899	68	0	0
T11	105576	1264	0	0
T12	556670	489	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	232579	0	0
T1	7879	103	0	0
T2	10981	214	0	0
T3	442005	19	0	0
T4	125275	481	0	0
T7	57082	174	0	0
T8	429867	22	0	0
T9	8609	157	0	0
T10	3899	64	0	0
T11	105576	1120	0	0
T12	556670	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	216171	0	0
GntImpliesValid_A	415429174	216171	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	216171	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2980530	0	0
ReadyAndValidImplyGrant_A	415429174	216171	0	0
ReqAndReadyImplyGrant_A	415429174	216171	0	0
ReqImpliesValid_A	415429174	535037	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	216171	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	216171	0	0
T1	7879	72	0	0
T2	10981	223	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	87	0	0
T8	429867	9	0	0
T9	8609	135	0	0
T10	3899	61	0	0
T11	105576	568	0	0
T12	556670	22	0	0
T13	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	216171	0	0
T1	7879	72	0	0
T2	10981	223	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	87	0	0
T8	429867	9	0	0
T9	8609	135	0	0
T10	3899	61	0	0
T11	105576	568	0	0
T12	556670	22	0	0
T13	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	216171	0	0
T1	7879	72	0	0
T2	10981	223	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	87	0	0
T8	429867	9	0	0
T9	8609	135	0	0
T10	3899	61	0	0
T11	105576	568	0	0
T12	556670	22	0	0
T13	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2980530	0	0
T1	7879	71	0	0
T2	10981	214	0	0
T3	442005	60	0	0
T4	125275	1	0	0
T7	57082	609	0	0
T8	429867	2622	0	0
T9	8609	130	0	0
T10	3899	60	0	0
T11	105576	554	0	0
T12	556670	6788	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	216171	0	0
T1	7879	72	0	0
T2	10981	223	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	87	0	0
T8	429867	9	0	0
T9	8609	135	0	0
T10	3899	61	0	0
T11	105576	568	0	0
T12	556670	22	0	0
T13	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	216171	0	0
T1	7879	72	0	0
T2	10981	223	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	87	0	0
T8	429867	9	0	0
T9	8609	135	0	0
T10	3899	61	0	0
T11	105576	568	0	0
T12	556670	22	0	0
T13	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	535037	0	0
T1	7879	74	0	0
T2	10981	233	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	117	0	0
T8	429867	9	0	0
T9	8609	141	0	0
T10	3899	63	0	0
T11	105576	583	0	0
T12	556670	64	0	0
T13	0	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	216171	0	0
T1	7879	72	0	0
T2	10981	223	0	0
T3	442005	13	0	0
T4	125275	0	0	0
T7	57082	87	0	0
T8	429867	9	0	0
T9	8609	135	0	0
T10	3899	61	0	0
T11	105576	568	0	0
T12	556670	22	0	0
T13	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	211106	0	0
GntImpliesValid_A	415429174	211106	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	211106	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2945044	0	0
ReadyAndValidImplyGrant_A	415429174	211106	0	0
ReqAndReadyImplyGrant_A	415429174	211106	0	0
ReqImpliesValid_A	415429174	501721	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	211106	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	211106	0	0
T1	7879	75	0	0
T2	10981	247	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	106	0	0
T8	429867	11	0	0
T9	8609	158	0	0
T10	3899	52	0	0
T11	105576	2088	0	0
T12	556670	38	0	0
T13	0	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	211106	0	0
T1	7879	75	0	0
T2	10981	247	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	106	0	0
T8	429867	11	0	0
T9	8609	158	0	0
T10	3899	52	0	0
T11	105576	2088	0	0
T12	556670	38	0	0
T13	0	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	211106	0	0
T1	7879	75	0	0
T2	10981	247	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	106	0	0
T8	429867	11	0	0
T9	8609	158	0	0
T10	3899	52	0	0
T11	105576	2088	0	0
T12	556670	38	0	0
T13	0	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2945044	0	0
T1	7879	73	0	0
T2	10981	230	0	0
T3	442005	46	0	0
T4	125275	1	0	0
T7	57082	820	0	0
T8	429867	2781	0	0
T9	8609	153	0	0
T10	3899	52	0	0
T11	105576	1440	0	0
T12	556670	10963	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	211106	0	0
T1	7879	75	0	0
T2	10981	247	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	106	0	0
T8	429867	11	0	0
T9	8609	158	0	0
T10	3899	52	0	0
T11	105576	2088	0	0
T12	556670	38	0	0
T13	0	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	211106	0	0
T1	7879	75	0	0
T2	10981	247	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	106	0	0
T8	429867	11	0	0
T9	8609	158	0	0
T10	3899	52	0	0
T11	105576	2088	0	0
T12	556670	38	0	0
T13	0	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	501721	0	0
T1	7879	78	0	0
T2	10981	265	0	0
T3	442005	23	0	0
T4	125275	0	0	0
T7	57082	110	0	0
T8	429867	11	0	0
T9	8609	164	0	0
T10	3899	53	0	0
T11	105576	2737	0	0
T12	556670	1127	0	0
T13	0	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	211106	0	0
T1	7879	75	0	0
T2	10981	247	0	0
T3	442005	15	0	0
T4	125275	0	0	0
T7	57082	106	0	0
T8	429867	11	0	0
T9	8609	158	0	0
T10	3899	52	0	0
T11	105576	2088	0	0
T12	556670	38	0	0
T13	0	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	213203	0	0
GntImpliesValid_A	415429174	213203	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	213203	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2908479	0	0
ReadyAndValidImplyGrant_A	415429174	213203	0	0
ReqAndReadyImplyGrant_A	415429174	213203	0	0
ReqImpliesValid_A	415429174	532544	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	213203	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213203	0	0
T1	7879	59	0	0
T2	10981	232	0	0
T3	442005	14	0	0
T4	125275	968	0	0
T7	57082	96	0	0
T8	429867	9	0	0
T9	8609	156	0	0
T10	3899	62	0	0
T11	105576	2081	0	0
T12	556670	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213203	0	0
T1	7879	59	0	0
T2	10981	232	0	0
T3	442005	14	0	0
T4	125275	968	0	0
T7	57082	96	0	0
T8	429867	9	0	0
T9	8609	156	0	0
T10	3899	62	0	0
T11	105576	2081	0	0
T12	556670	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213203	0	0
T1	7879	59	0	0
T2	10981	232	0	0
T3	442005	14	0	0
T4	125275	968	0	0
T7	57082	96	0	0
T8	429867	9	0	0
T9	8609	156	0	0
T10	3899	62	0	0
T11	105576	2081	0	0
T12	556670	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2908479	0	0
T1	7879	56	0	0
T2	10981	217	0	0
T3	442005	58	0	0
T4	125275	1428	0	0
T7	57082	644	0	0
T8	429867	3230	0	0
T9	8609	142	0	0
T10	3899	60	0	0
T11	105576	644	0	0
T12	556670	13678	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213203	0	0
T1	7879	59	0	0
T2	10981	232	0	0
T3	442005	14	0	0
T4	125275	968	0	0
T7	57082	96	0	0
T8	429867	9	0	0
T9	8609	156	0	0
T10	3899	62	0	0
T11	105576	2081	0	0
T12	556670	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213203	0	0
T1	7879	59	0	0
T2	10981	232	0	0
T3	442005	14	0	0
T4	125275	968	0	0
T7	57082	96	0	0
T8	429867	9	0	0
T9	8609	156	0	0
T10	3899	62	0	0
T11	105576	2081	0	0
T12	556670	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	532544	0	0
T1	7879	63	0	0
T2	10981	248	0	0
T3	442005	14	0	0
T4	125275	9575	0	0
T7	57082	161	0	0
T8	429867	9	0	0
T9	8609	171	0	0
T10	3899	65	0	0
T11	105576	3519	0	0
T12	556670	783	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	213203	0	0
T1	7879	59	0	0
T2	10981	232	0	0
T3	442005	14	0	0
T4	125275	968	0	0
T7	57082	96	0	0
T8	429867	9	0	0
T9	8609	156	0	0
T10	3899	62	0	0
T11	105576	2081	0	0
T12	556670	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	214174	0	0
GntImpliesValid_A	415429174	214174	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	214174	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2908849	0	0
ReadyAndValidImplyGrant_A	415429174	214174	0	0
ReqAndReadyImplyGrant_A	415429174	214174	0	0
ReqImpliesValid_A	415429174	517532	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	214174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214174	0	0
T1	7879	58	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	110	0	0
T8	429867	11	0	0
T9	8609	134	0	0
T10	3899	89	0	0
T11	105576	3535	0	0
T12	556670	29	0	0
T13	0	37	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214174	0	0
T1	7879	58	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	110	0	0
T8	429867	11	0	0
T9	8609	134	0	0
T10	3899	89	0	0
T11	105576	3535	0	0
T12	556670	29	0	0
T13	0	37	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214174	0	0
T1	7879	58	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	110	0	0
T8	429867	11	0	0
T9	8609	134	0	0
T10	3899	89	0	0
T11	105576	3535	0	0
T12	556670	29	0	0
T13	0	37	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2908849	0	0
T1	7879	57	0	0
T2	10981	200	0	0
T3	442005	55	0	0
T4	125275	1	0	0
T7	57082	870	0	0
T8	429867	4732	0	0
T9	8609	129	0	0
T10	3899	82	0	0
T11	105576	1662	0	0
T12	556670	9481	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214174	0	0
T1	7879	58	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	110	0	0
T8	429867	11	0	0
T9	8609	134	0	0
T10	3899	89	0	0
T11	105576	3535	0	0
T12	556670	29	0	0
T13	0	37	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214174	0	0
T1	7879	58	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	110	0	0
T8	429867	11	0	0
T9	8609	134	0	0
T10	3899	89	0	0
T11	105576	3535	0	0
T12	556670	29	0	0
T13	0	37	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	517532	0	0
T1	7879	60	0	0
T2	10981	217	0	0
T3	442005	16	0	0
T4	125275	0	0	0
T7	57082	115	0	0
T8	429867	620	0	0
T9	8609	140	0	0
T10	3899	97	0	0
T11	105576	5409	0	0
T12	556670	465	0	0
T13	0	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214174	0	0
T1	7879	58	0	0
T2	10981	208	0	0
T3	442005	14	0	0
T4	125275	0	0	0
T7	57082	110	0	0
T8	429867	11	0	0
T9	8609	134	0	0
T10	3899	89	0	0
T11	105576	3535	0	0
T12	556670	29	0	0
T13	0	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	214726	0	0
GntImpliesValid_A	415429174	214726	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	214726	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	2882549	0	0
ReadyAndValidImplyGrant_A	415429174	214726	0	0
ReqAndReadyImplyGrant_A	415429174	214726	0	0
ReqImpliesValid_A	415429174	509883	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	0	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	214726	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214726	0	0
T1	7879	73	0	0
T2	10981	210	0	0
T3	442005	17	0	0
T4	125275	0	0	0
T7	57082	119	0	0
T8	429867	11	0	0
T9	8609	166	0	0
T10	3899	62	0	0
T11	105576	2136	0	0
T12	556670	36	0	0
T13	0	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214726	0	0
T1	7879	73	0	0
T2	10981	210	0	0
T3	442005	17	0	0
T4	125275	0	0	0
T7	57082	119	0	0
T8	429867	11	0	0
T9	8609	166	0	0
T10	3899	62	0	0
T11	105576	2136	0	0
T12	556670	36	0	0
T13	0	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214726	0	0
T1	7879	73	0	0
T2	10981	210	0	0
T3	442005	17	0	0
T4	125275	0	0	0
T7	57082	119	0	0
T8	429867	11	0	0
T9	8609	166	0	0
T10	3899	62	0	0
T11	105576	2136	0	0
T12	556670	36	0	0
T13	0	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2882549	0	0
T1	7879	71	0	0
T2	10981	202	0	0
T3	442005	72	0	0
T4	125275	1	0	0
T7	57082	876	0	0
T8	429867	2987	0	0
T9	8609	154	0	0
T10	3899	61	0	0
T11	105576	1140	0	0
T12	556670	8459	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214726	0	0
T1	7879	73	0	0
T2	10981	210	0	0
T3	442005	17	0	0
T4	125275	0	0	0
T7	57082	119	0	0
T8	429867	11	0	0
T9	8609	166	0	0
T10	3899	62	0	0
T11	105576	2136	0	0
T12	556670	36	0	0
T13	0	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214726	0	0
T1	7879	73	0	0
T2	10981	210	0	0
T3	442005	17	0	0
T4	125275	0	0	0
T7	57082	119	0	0
T8	429867	11	0	0
T9	8609	166	0	0
T10	3899	62	0	0
T11	105576	2136	0	0
T12	556670	36	0	0
T13	0	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	509883	0	0
T1	7879	76	0	0
T2	10981	219	0	0
T3	442005	17	0	0
T4	125275	0	0	0
T7	57082	157	0	0
T8	429867	11	0	0
T9	8609	179	0	0
T10	3899	64	0	0
T11	105576	3133	0	0
T12	556670	782	0	0
T13	0	54	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	214726	0	0
T1	7879	73	0	0
T2	10981	210	0	0
T3	442005	17	0	0
T4	125275	0	0	0
T7	57082	119	0	0
T8	429867	11	0	0
T9	8609	166	0	0
T10	3899	62	0	0
T11	105576	2136	0	0
T12	556670	36	0	0
T13	0	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	874364	0	0
GntImpliesValid_A	415429174	874364	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	874364	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	10965358	0	0
ReadyAndValidImplyGrant_A	415429174	874364	0	0
ReqAndReadyImplyGrant_A	415429174	874364	0	0
ReqImpliesValid_A	415429174	2161028	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	21772	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	874364	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874364	0	0
T1	7879	239	0	0
T2	10981	878	0	0
T3	442005	54	0	0
T4	125275	742	0	0
T7	57082	377	0	0
T8	429867	46	0	0
T9	8609	576	0	0
T10	3899	192	0	0
T11	105576	6518	0	0
T12	556670	173	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874364	0	0
T1	7879	239	0	0
T2	10981	878	0	0
T3	442005	54	0	0
T4	125275	742	0	0
T7	57082	377	0	0
T8	429867	46	0	0
T9	8609	576	0	0
T10	3899	192	0	0
T11	105576	6518	0	0
T12	556670	173	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874364	0	0
T1	7879	239	0	0
T2	10981	878	0	0
T3	442005	54	0	0
T4	125275	742	0	0
T7	57082	377	0	0
T8	429867	46	0	0
T9	8609	576	0	0
T10	3899	192	0	0
T11	105576	6518	0	0
T12	556670	173	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	10965358	0	0
T1	7879	1	0	0
T2	10981	1	0	0
T3	442005	185	0	0
T4	125275	4895	0	0
T7	57082	2377	0	0
T8	429867	16270	0	0
T9	8609	1	0	0
T10	3899	1	0	0
T11	105576	1	0	0
T12	556670	51392	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874364	0	0
T1	7879	239	0	0
T2	10981	878	0	0
T3	442005	54	0	0
T4	125275	742	0	0
T7	57082	377	0	0
T8	429867	46	0	0
T9	8609	576	0	0
T10	3899	192	0	0
T11	105576	6518	0	0
T12	556670	173	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874364	0	0
T1	7879	239	0	0
T2	10981	878	0	0
T3	442005	54	0	0
T4	125275	742	0	0
T7	57082	377	0	0
T8	429867	46	0	0
T9	8609	576	0	0
T10	3899	192	0	0
T11	105576	6518	0	0
T12	556670	173	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	2161028	0	0
T1	7879	239	0	0
T2	10981	878	0	0
T3	442005	66	0	0
T4	125275	1104	0	0
T7	57082	543	0	0
T8	429867	1625	0	0
T9	8609	576	0	0
T10	3899	192	0	0
T11	105576	6518	0	0
T12	556670	9138	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	21772	0	900
T1	7879	1	0	1
T2	10981	16	0	1
T3	442005	0	0	1
T4	125275	0	0	1
T7	57082	0	0	1
T8	429867	0	0	1
T9	8609	11	0	1
T10	3899	3	0	1
T11	105576	680	0	1
T12	556670	0	0	1
T13	0	2	0	0
T14	0	7	0	0
T15	0	1	0	0
T16	0	22	0	0
T17	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	874364	0	0
T1	7879	239	0	0
T2	10981	878	0	0
T3	442005	54	0	0
T4	125275	742	0	0
T7	57082	377	0	0
T8	429867	46	0	0
T9	8609	576	0	0
T10	3899	192	0	0
T11	105576	6518	0	0
T12	556670	173	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415429174	415310673	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415429174	869874	0	0
GntImpliesValid_A	415429174	869874	0	0
GrantKnown_A	415429174	415310673	0	0
IdxKnown_A	415429174	415310673	0	0
IndexIsCorrect_A	415429174	869874	0	0
LockArbDecision_A	415429174	0	0	0
NoReadyValidNoGrant_A	415429174	348289263	0	0
ReadyAndValidImplyGrant_A	415429174	869874	0	0
ReqAndReadyImplyGrant_A	415429174	869874	0	0
ReqImpliesValid_A	415429174	12730741	0	0
ReqStaysHighUntilGranted0_M	415429174	0	0	0
RoundRobin_A	415429174	33074	0	900
ValidKnown_A	415429174	415310673	0	0
gen_data_port_assertion.DataFlow_A	415429174	869874	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	869874	0	0
T1	7879	277	0	0
T2	10981	804	0	0
T3	442005	61	0	0
T4	125275	1999	0	0
T7	57082	387	0	0
T8	429867	42	0	0
T9	8609	590	0	0
T10	3899	227	0	0
T11	105576	5903	0	0
T12	556670	131	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	869874	0	0
T1	7879	277	0	0
T2	10981	804	0	0
T3	442005	61	0	0
T4	125275	1999	0	0
T7	57082	387	0	0
T8	429867	42	0	0
T9	8609	590	0	0
T10	3899	227	0	0
T11	105576	5903	0	0
T12	556670	131	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	869874	0	0
T1	7879	277	0	0
T2	10981	804	0	0
T3	442005	61	0	0
T4	125275	1999	0	0
T7	57082	387	0	0
T8	429867	42	0	0
T9	8609	590	0	0
T10	3899	227	0	0
T11	105576	5903	0	0
T12	556670	131	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	348289263	0	0
T1	7879	1	0	0
T2	10981	1	0	0
T3	442005	368029	0	0
T4	125275	96120	0	0
T7	57082	47997	0	0
T8	429867	410023	0	0
T9	8609	1	0	0
T10	3899	1	0	0
T11	105576	1	0	0
T12	556670	493687	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	869874	0	0
T1	7879	277	0	0
T2	10981	804	0	0
T3	442005	61	0	0
T4	125275	1999	0	0
T7	57082	387	0	0
T8	429867	42	0	0
T9	8609	590	0	0
T10	3899	227	0	0
T11	105576	5903	0	0
T12	556670	131	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	869874	0	0
T1	7879	277	0	0
T2	10981	804	0	0
T3	442005	61	0	0
T4	125275	1999	0	0
T7	57082	387	0	0
T8	429867	42	0	0
T9	8609	590	0	0
T10	3899	227	0	0
T11	105576	5903	0	0
T12	556670	131	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	12730741	0	0
T1	7879	277	0	0
T2	10981	804	0	0
T3	442005	266	0	0
T4	125275	19730	0	0
T7	57082	2947	0	0
T8	429867	11561	0	0
T9	8609	590	0	0
T10	3899	227	0	0
T11	105576	5903	0	0
T12	556670	38939	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	33074	0	900
T1	7879	1	0	1
T2	10981	10	0	1
T3	442005	0	0	1
T4	125275	41	0	1
T7	57082	0	0	1
T8	429867	0	0	1
T9	8609	7	0	1
T10	3899	2	0	1
T11	105576	791	0	1
T12	556670	0	0	1
T13	0	2	0	0
T14	0	5	0	0
T16	0	17	0	0
T17	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	415310673	0	0
T1	7879	7824	0	0
T2	10981	10976	0	0
T3	442005	441955	0	0
T4	125275	125229	0	0
T7	57082	57041	0	0
T8	429867	429854	0	0
T9	8609	8578	0	0
T10	3899	3871	0	0
T11	105576	105522	0	0
T12	556670	556618	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415429174	869874	0	0
T1	7879	277	0	0
T2	10981	804	0	0
T3	442005	61	0	0
T4	125275	1999	0	0
T7	57082	387	0	0
T8	429867	42	0	0
T9	8609	590	0	0
T10	3899	227	0	0
T11	105576	5903	0	0
T12	556670	131	0	0