Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1446790 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 230470 1 T1 17 T2 534 T3 27


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 569236 1 T1 46 T2 1254 T3 64
values[0x0] 537768 1 T1 46 T2 1229 T3 64
values[0x1] 570256 1 T1 53 T2 1248 T3 57


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1116565 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 560695 1 T1 46 T2 1276 T3 76


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26687 1 T2 62 T3 2 T7 30
valid_sources[0x01] 25792 1 T2 49 T3 2 T7 25
valid_sources[0x02] 26017 1 T1 3 T2 58 T3 9
valid_sources[0x03] 26003 1 T2 64 T3 1 T7 29
valid_sources[0x04] 25967 1 T1 31 T2 52 T3 1
valid_sources[0x05] 25757 1 T1 11 T2 55 T3 1
valid_sources[0x06] 26278 1 T2 56 T3 4 T7 8
valid_sources[0x07] 26853 1 T2 55 T3 2 T7 44
valid_sources[0x08] 26520 1 T2 63 T3 3 T7 61
valid_sources[0x09] 25671 1 T2 61 T3 1 T7 27
valid_sources[0x0a] 26193 1 T2 60 T3 3 T7 58
valid_sources[0x0b] 26029 1 T2 46 T3 2 T7 32
valid_sources[0x0c] 26250 1 T2 69 T3 5 T7 12
valid_sources[0x0d] 25978 1 T2 53 T3 1 T7 7
valid_sources[0x0e] 25983 1 T2 58 T3 2 T7 50
valid_sources[0x0f] 27490 1 T1 21 T2 63 T3 3
valid_sources[0x10] 26026 1 T2 48 T3 1 T7 38
valid_sources[0x11] 25917 1 T2 62 T3 4 T7 29
valid_sources[0x12] 27070 1 T2 54 T3 7 T7 80
valid_sources[0x13] 25779 1 T2 55 T3 5 T7 10
valid_sources[0x14] 27593 1 T2 58 T3 2 T7 76
valid_sources[0x15] 25813 1 T2 60 T3 3 T7 16
valid_sources[0x16] 26345 1 T2 50 T3 5 T7 70
valid_sources[0x17] 25347 1 T2 56 T3 5 T7 52
valid_sources[0x18] 25003 1 T2 69 T3 3 T7 5
valid_sources[0x19] 26271 1 T2 63 T3 1 T7 34
valid_sources[0x1a] 26340 1 T2 58 T3 3 T7 42
valid_sources[0x1b] 26332 1 T2 58 T3 4 T7 35
valid_sources[0x1c] 27057 1 T2 65 T3 2 T7 24
valid_sources[0x1d] 25948 1 T1 5 T2 71 T3 5
valid_sources[0x1e] 26450 1 T1 2 T2 71 T3 3
valid_sources[0x1f] 26381 1 T2 71 T3 1 T7 60
valid_sources[0x20] 25248 1 T1 1 T2 63 T3 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24073 1 T2 48 T3 2 T7 32
values[0x0] all_enables biggest_size 182294 1 T1 14 T2 431 T3 25
values[0x1] all_enables biggest_size 24103 1 T1 3 T2 55 T7 32


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1465539 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 238437 1 T1 19 T2 522 T3 27


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 582861 1 T1 26 T2 1267 T3 64
values[0x0] 537551 1 T1 39 T2 1209 T3 63
values[0x1] 583564 1 T1 22 T2 1286 T3 61


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1124523 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 579453 1 T1 36 T2 1253 T3 66


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26361 1 T1 1 T2 58 T7 24
valid_sources[0x01] 26738 1 T1 1 T2 52 T7 38
valid_sources[0x02] 26410 1 T1 1 T2 59 T3 14
valid_sources[0x03] 26374 1 T1 2 T2 57 T3 1
valid_sources[0x04] 26665 1 T2 50 T3 6 T7 27
valid_sources[0x05] 26306 1 T2 51 T3 1 T7 34
valid_sources[0x06] 26288 1 T1 1 T2 79 T3 1
valid_sources[0x07] 26631 1 T1 3 T2 70 T7 37
valid_sources[0x08] 26258 1 T2 44 T7 25 T8 1
valid_sources[0x09] 26840 1 T2 63 T3 19 T7 29
valid_sources[0x0a] 26156 1 T1 2 T2 59 T3 3
valid_sources[0x0b] 26070 1 T2 62 T7 32 T8 1
valid_sources[0x0c] 26581 1 T1 1 T2 80 T7 17
valid_sources[0x0d] 26337 1 T1 1 T2 63 T7 10
valid_sources[0x0e] 27186 1 T1 2 T2 53 T7 27
valid_sources[0x0f] 27220 1 T1 1 T2 65 T7 47
valid_sources[0x10] 26449 1 T2 50 T3 3 T7 25
valid_sources[0x11] 27365 1 T1 2 T2 57 T3 7
valid_sources[0x12] 27481 1 T1 3 T2 70 T3 8
valid_sources[0x13] 26256 1 T2 62 T7 34 T9 73
valid_sources[0x14] 27242 1 T2 70 T3 10 T7 29
valid_sources[0x15] 26200 1 T2 60 T3 1 T7 27
valid_sources[0x16] 27298 1 T1 1 T2 44 T7 33
valid_sources[0x17] 26621 1 T1 1 T2 49 T7 17
valid_sources[0x18] 27129 1 T1 2 T2 47 T7 13
valid_sources[0x19] 26698 1 T1 3 T2 65 T7 28
valid_sources[0x1a] 26725 1 T1 1 T2 67 T7 14
valid_sources[0x1b] 26420 1 T1 2 T2 67 T7 30
valid_sources[0x1c] 26898 1 T1 1 T2 72 T7 38
valid_sources[0x1d] 26862 1 T2 60 T3 1 T7 20
valid_sources[0x1e] 26431 1 T1 1 T2 49 T3 7
valid_sources[0x1f] 26720 1 T2 70 T3 2 T7 36
valid_sources[0x20] 26566 1 T2 54 T3 3 T7 38


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24844 1 T1 1 T2 42 T3 3
values[0x0] all_enables biggest_size 188596 1 T1 16 T2 435 T3 21
values[0x1] all_enables biggest_size 24997 1 T1 2 T2 45 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1460093 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 232475 1 T1 18 T2 509 T3 23


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 573966 1 T1 48 T2 1234 T3 77
values[0x0] 543452 1 T1 44 T2 1213 T3 61
values[0x1] 575150 1 T1 52 T2 1280 T3 61


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1128606 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 563962 1 T1 46 T2 1230 T3 57


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26062 1 T1 2 T2 62 T3 7
valid_sources[0x01] 26122 1 T1 1 T2 46 T3 4
valid_sources[0x02] 26131 1 T1 5 T2 69 T3 3
valid_sources[0x03] 25797 1 T1 1 T2 62 T3 3
valid_sources[0x04] 25920 1 T2 64 T3 3 T7 19
valid_sources[0x05] 25759 1 T2 54 T3 1 T7 80
valid_sources[0x06] 25975 1 T1 5 T2 52 T3 1
valid_sources[0x07] 26470 1 T1 1 T2 61 T3 3
valid_sources[0x08] 25697 1 T2 54 T3 1 T9 66
valid_sources[0x09] 26987 1 T1 2 T2 74 T3 1
valid_sources[0x0a] 26266 1 T2 54 T3 1 T9 67
valid_sources[0x0b] 26153 1 T2 51 T3 4 T9 52
valid_sources[0x0c] 26567 1 T1 3 T2 61 T3 2
valid_sources[0x0d] 26471 1 T1 2 T2 57 T3 4
valid_sources[0x0e] 26920 1 T1 6 T2 68 T3 3
valid_sources[0x0f] 26618 1 T1 7 T2 73 T3 1
valid_sources[0x10] 26544 1 T1 1 T2 67 T3 2
valid_sources[0x11] 26483 1 T1 1 T2 66 T3 1
valid_sources[0x12] 27124 1 T1 3 T2 70 T3 3
valid_sources[0x13] 26900 1 T2 66 T3 2 T7 60
valid_sources[0x14] 26289 1 T1 4 T2 67 T3 3
valid_sources[0x15] 26507 1 T1 4 T2 56 T3 3
valid_sources[0x16] 25942 1 T2 52 T9 67 T10 10
valid_sources[0x17] 27117 1 T1 1 T2 62 T3 6
valid_sources[0x18] 26855 1 T2 61 T3 3 T7 106
valid_sources[0x19] 26995 1 T1 3 T2 61 T3 4
valid_sources[0x1a] 26532 1 T2 54 T3 5 T9 61
valid_sources[0x1b] 26339 1 T2 53 T3 1 T7 91
valid_sources[0x1c] 26635 1 T1 2 T2 56 T3 2
valid_sources[0x1d] 26037 1 T2 76 T3 6 T7 4
valid_sources[0x1e] 27081 1 T1 1 T2 61 T3 3
valid_sources[0x1f] 26122 1 T1 5 T2 55 T3 1
valid_sources[0x20] 26078 1 T1 4 T2 45 T3 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24523 1 T1 2 T2 48 T3 1
values[0x0] all_enables biggest_size 183792 1 T1 13 T2 398 T3 20
values[0x1] all_enables biggest_size 24160 1 T1 3 T2 63 T3 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%