Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21576	21576	0	0
GntImpliesReady_A	2147483647	7427492	0	0
GntImpliesValid_A	2147483647	7427492	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7427492	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	442373402	0	0
ReadyAndValidImplyGrant_A	2147483647	7427492	0	0
ReqAndReadyImplyGrant_A	2147483647	7427492	0	0
ReqImpliesValid_A	2147483647	32089764	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	41874	0	21576
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7427492	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6929832	6928200	0	0
T2	10502712	10502592	0	0
T3	359400	357984	0	0
T7	223080	221424	0	0
T8	8115552	8114544	0	0
T9	10902672	10902624	0	0
T10	1865160	1859640	0	0
T11	10287120	10286736	0	0
T12	3974256	3922872	0	0
T13	5282304	5282112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21576	21576	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7427492	0	0
T1	6929832	376	0	0
T2	10502712	11216	0	0
T3	359400	572	0	0
T7	223080	2992	0	0
T8	8115552	355	0	0
T9	10902672	12417	0	0
T10	1865160	34976	0	0
T11	10287120	460	0	0
T12	3974256	62406	0	0
T13	5282304	392	0	0
T14	0	735	0	0
T15	0	4568	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7427492	0	0
T1	6929832	376	0	0
T2	10502712	11216	0	0
T3	359400	572	0	0
T7	223080	2992	0	0
T8	8115552	355	0	0
T9	10902672	12417	0	0
T10	1865160	34976	0	0
T11	10287120	460	0	0
T12	3974256	62406	0	0
T13	5282304	392	0	0
T14	0	735	0	0
T15	0	4568	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6929832	6928200	0	0
T2	10502712	10502592	0	0
T3	359400	357984	0	0
T7	223080	221424	0	0
T8	8115552	8114544	0	0
T9	10902672	10902624	0	0
T10	1865160	1859640	0	0
T11	10287120	10286736	0	0
T12	3974256	3922872	0	0
T13	5282304	5282112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6929832	6928200	0	0
T2	10502712	10502592	0	0
T3	359400	357984	0	0
T7	223080	221424	0	0
T8	8115552	8114544	0	0
T9	10902672	10902624	0	0
T10	1865160	1859640	0	0
T11	10287120	10286736	0	0
T12	3974256	3922872	0	0
T13	5282304	5282112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7427492	0	0
T1	6929832	376	0	0
T2	10502712	11216	0	0
T3	359400	572	0	0
T7	223080	2992	0	0
T8	8115552	355	0	0
T9	10902672	12417	0	0
T10	1865160	34976	0	0
T11	10287120	460	0	0
T12	3974256	62406	0	0
T13	5282304	392	0	0
T14	0	735	0	0
T15	0	4568	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	442373402	0	0
T1	6929832	242642	0	0
T2	10502712	400540	0	0
T3	359400	17272	0	0
T7	223080	5492	0	0
T8	8115552	419398	0	0
T9	10902672	416880	0	0
T10	1865160	57370	0	0
T11	10287120	542992	0	0
T12	3974256	100651	0	0
T13	5282304	184825	0	0
T14	0	998	0	0
T15	0	12122	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7427492	0	0
T1	6929832	376	0	0
T2	10502712	11216	0	0
T3	359400	572	0	0
T7	223080	2992	0	0
T8	8115552	355	0	0
T9	10902672	12417	0	0
T10	1865160	34976	0	0
T11	10287120	460	0	0
T12	3974256	62406	0	0
T13	5282304	392	0	0
T14	0	735	0	0
T15	0	4568	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7427492	0	0
T1	6929832	376	0	0
T2	10502712	11216	0	0
T3	359400	572	0	0
T7	223080	2992	0	0
T8	8115552	355	0	0
T9	10902672	12417	0	0
T10	1865160	34976	0	0
T11	10287120	460	0	0
T12	3974256	62406	0	0
T13	5282304	392	0	0
T14	0	735	0	0
T15	0	4568	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32089764	0	0
T1	6929832	573	0	0
T2	10502712	25482	0	0
T3	359400	1263	0	0
T7	223080	3597	0	0
T8	8115552	18715	0	0
T9	10902672	28778	0	0
T10	1865160	39911	0	0
T11	10287120	21341	0	0
T12	3974256	90555	0	0
T13	5282304	570	0	0
T14	0	885	0	0
T15	0	19367	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41874	0	21576
T2	437613	16	0	1
T3	14975	0	0	1
T7	18590	7	0	2
T8	676296	0	0	2
T9	908556	0	0	2
T10	155430	90	0	2
T11	857260	0	0	2
T12	331188	759	0	2
T13	440192	0	0	2
T14	6568	7	0	2
T15	511196	153	0	1
T16	9301	14	0	1
T17	0	20	0	0
T18	0	1255	0	0
T19	0	3	0	0
T20	0	22	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6929832	6928200	0	0
T2	10502712	10502592	0	0
T3	359400	357984	0	0
T7	223080	221424	0	0
T8	8115552	8114544	0	0
T9	10902672	10902624	0	0
T10	1865160	1859640	0	0
T11	10287120	10286736	0	0
T12	3974256	3922872	0	0
T13	5282304	5282112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7427492	0	0
T1	6929832	376	0	0
T2	10502712	11216	0	0
T3	359400	572	0	0
T7	223080	2992	0	0
T8	8115552	355	0	0
T9	10902672	12417	0	0
T10	1865160	34976	0	0
T11	10287120	460	0	0
T12	3974256	62406	0	0
T13	5282304	392	0	0
T14	0	735	0	0
T15	0	4568	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	836349	0	0
GntImpliesValid_A	410573884	836349	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	836349	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	11324106	0	0
ReadyAndValidImplyGrant_A	410573884	836349	0	0
ReqAndReadyImplyGrant_A	410573884	836349	0	0
ReqImpliesValid_A	410573884	2364481	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	836349	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	836349	0	0
T1	288743	44	0	0
T2	437613	1576	0	0
T3	14975	59	0	0
T7	9295	322	0	0
T8	338148	32	0	0
T9	454278	1613	0	0
T10	77715	3949	0	0
T11	428630	57	0	0
T12	165594	7058	0	0
T13	220096	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	836349	0	0
T1	288743	44	0	0
T2	437613	1576	0	0
T3	14975	59	0	0
T7	9295	322	0	0
T8	338148	32	0	0
T9	454278	1613	0	0
T10	77715	3949	0	0
T11	428630	57	0	0
T12	165594	7058	0	0
T13	220096	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	836349	0	0
T1	288743	44	0	0
T2	437613	1576	0	0
T3	14975	59	0	0
T7	9295	322	0	0
T8	338148	32	0	0
T9	454278	1613	0	0
T10	77715	3949	0	0
T11	428630	57	0	0
T12	165594	7058	0	0
T13	220096	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	11324106	0	0
T1	288743	184	0	0
T2	437613	6001	0	0
T3	14975	456	0	0
T7	9295	271	0	0
T8	338148	10190	0	0
T9	454278	5791	0	0
T10	77715	3269	0	0
T11	428630	18815	0	0
T12	165594	5405	0	0
T13	220096	179	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	836349	0	0
T1	288743	44	0	0
T2	437613	1576	0	0
T3	14975	59	0	0
T7	9295	322	0	0
T8	338148	32	0	0
T9	454278	1613	0	0
T10	77715	3949	0	0
T11	428630	57	0	0
T12	165594	7058	0	0
T13	220096	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	836349	0	0
T1	288743	44	0	0
T2	437613	1576	0	0
T3	14975	59	0	0
T7	9295	322	0	0
T8	338148	32	0	0
T9	454278	1613	0	0
T10	77715	3949	0	0
T11	428630	57	0	0
T12	165594	7058	0	0
T13	220096	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2364481	0	0
T1	288743	75	0	0
T2	437613	2939	0	0
T3	14975	80	0	0
T7	9295	374	0	0
T8	338148	965	0	0
T9	454278	3052	0	0
T10	77715	4633	0	0
T11	428630	1097	0	0
T12	165594	8731	0	0
T13	220096	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	836349	0	0
T1	288743	44	0	0
T2	437613	1576	0	0
T3	14975	59	0	0
T7	9295	322	0	0
T8	338148	32	0	0
T9	454278	1613	0	0
T10	77715	3949	0	0
T11	428630	57	0	0
T12	165594	7058	0	0
T13	220096	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	819241	0	0
GntImpliesValid_A	410573884	819241	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	819241	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	11297379	0	0
ReadyAndValidImplyGrant_A	410573884	819241	0	0
ReqAndReadyImplyGrant_A	410573884	819241	0	0
ReqImpliesValid_A	410573884	2365084	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	819241	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	819241	0	0
T1	288743	39	0	0
T2	437613	789	0	0
T3	14975	65	0	0
T7	9295	299	0	0
T8	338148	35	0	0
T9	454278	970	0	0
T10	77715	3881	0	0
T11	428630	53	0	0
T12	165594	7697	0	0
T13	220096	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	819241	0	0
T1	288743	39	0	0
T2	437613	789	0	0
T3	14975	65	0	0
T7	9295	299	0	0
T8	338148	35	0	0
T9	454278	970	0	0
T10	77715	3881	0	0
T11	428630	53	0	0
T12	165594	7697	0	0
T13	220096	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	819241	0	0
T1	288743	39	0	0
T2	437613	789	0	0
T3	14975	65	0	0
T7	9295	299	0	0
T8	338148	35	0	0
T9	454278	970	0	0
T10	77715	3881	0	0
T11	428630	53	0	0
T12	165594	7697	0	0
T13	220096	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	11297379	0	0
T1	288743	165	0	0
T2	437613	3212	0	0
T3	14975	485	0	0
T7	9295	257	0	0
T8	338148	12181	0	0
T9	454278	3850	0	0
T10	77715	3198	0	0
T11	428630	17909	0	0
T12	165594	5464	0	0
T13	220096	156	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	819241	0	0
T1	288743	39	0	0
T2	437613	789	0	0
T3	14975	65	0	0
T7	9295	299	0	0
T8	338148	35	0	0
T9	454278	970	0	0
T10	77715	3881	0	0
T11	428630	53	0	0
T12	165594	7697	0	0
T13	220096	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	819241	0	0
T1	288743	39	0	0
T2	437613	789	0	0
T3	14975	65	0	0
T7	9295	299	0	0
T8	338148	35	0	0
T9	454278	970	0	0
T10	77715	3881	0	0
T11	428630	53	0	0
T12	165594	7697	0	0
T13	220096	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2365084	0	0
T1	288743	58	0	0
T2	437613	1108	0	0
T3	14975	88	0	0
T7	9295	342	0	0
T8	338148	243	0	0
T9	454278	1328	0	0
T10	77715	4568	0	0
T11	428630	649	0	0
T12	165594	9950	0	0
T13	220096	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	819241	0	0
T1	288743	39	0	0
T2	437613	789	0	0
T3	14975	65	0	0
T7	9295	299	0	0
T8	338148	35	0	0
T9	454278	970	0	0
T10	77715	3881	0	0
T11	428630	53	0	0
T12	165594	7697	0	0
T13	220096	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	214925	0	0
GntImpliesValid_A	410573884	214925	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	214925	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2766610	0	0
ReadyAndValidImplyGrant_A	410573884	214925	0	0
ReqAndReadyImplyGrant_A	410573884	214925	0	0
ReqImpliesValid_A	410573884	578495	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	214925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214925	0	0
T1	288743	10	0	0
T2	437613	1050	0	0
T3	14975	18	0	0
T7	9295	72	0	0
T8	338148	12	0	0
T9	454278	1469	0	0
T10	77715	929	0	0
T11	428630	12	0	0
T12	165594	2102	0	0
T13	220096	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214925	0	0
T1	288743	10	0	0
T2	437613	1050	0	0
T3	14975	18	0	0
T7	9295	72	0	0
T8	338148	12	0	0
T9	454278	1469	0	0
T10	77715	929	0	0
T11	428630	12	0	0
T12	165594	2102	0	0
T13	220096	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214925	0	0
T1	288743	10	0	0
T2	437613	1050	0	0
T3	14975	18	0	0
T7	9295	72	0	0
T8	338148	12	0	0
T9	454278	1469	0	0
T10	77715	929	0	0
T11	428630	12	0	0
T12	165594	2102	0	0
T13	220096	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2766610	0	0
T1	288743	39	0	0
T2	437613	3518	0	0
T3	14975	153	0	0
T7	9295	72	0	0
T8	338148	4699	0	0
T9	454278	4658	0	0
T10	77715	915	0	0
T11	428630	4680	0	0
T12	165594	1236	0	0
T13	220096	56	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214925	0	0
T1	288743	10	0	0
T2	437613	1050	0	0
T3	14975	18	0	0
T7	9295	72	0	0
T8	338148	12	0	0
T9	454278	1469	0	0
T10	77715	929	0	0
T11	428630	12	0	0
T12	165594	2102	0	0
T13	220096	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214925	0	0
T1	288743	10	0	0
T2	437613	1050	0	0
T3	14975	18	0	0
T7	9295	72	0	0
T8	338148	12	0	0
T9	454278	1469	0	0
T10	77715	929	0	0
T11	428630	12	0	0
T12	165594	2102	0	0
T13	220096	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	578495	0	0
T1	288743	14	0	0
T2	437613	2348	0	0
T3	14975	25	0	0
T7	9295	73	0	0
T8	338148	12	0	0
T9	454278	3658	0	0
T10	77715	947	0	0
T11	428630	92	0	0
T12	165594	2988	0	0
T13	220096	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214925	0	0
T1	288743	10	0	0
T2	437613	1050	0	0
T3	14975	18	0	0
T7	9295	72	0	0
T8	338148	12	0	0
T9	454278	1469	0	0
T10	77715	929	0	0
T11	428630	12	0	0
T12	165594	2102	0	0
T13	220096	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	202842	0	0
GntImpliesValid_A	410573884	202842	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	202842	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2710923	0	0
ReadyAndValidImplyGrant_A	410573884	202842	0	0
ReqAndReadyImplyGrant_A	410573884	202842	0	0
ReqImpliesValid_A	410573884	529971	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	202842	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202842	0	0
T1	288743	18	0	0
T2	437613	423	0	0
T3	14975	19	0	0
T7	9295	68	0	0
T8	338148	13	0	0
T9	454278	496	0	0
T10	77715	894	0	0
T11	428630	7	0	0
T12	165594	1614	0	0
T13	220096	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202842	0	0
T1	288743	18	0	0
T2	437613	423	0	0
T3	14975	19	0	0
T7	9295	68	0	0
T8	338148	13	0	0
T9	454278	496	0	0
T10	77715	894	0	0
T11	428630	7	0	0
T12	165594	1614	0	0
T13	220096	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202842	0	0
T1	288743	18	0	0
T2	437613	423	0	0
T3	14975	19	0	0
T7	9295	68	0	0
T8	338148	13	0	0
T9	454278	496	0	0
T10	77715	894	0	0
T11	428630	7	0	0
T12	165594	1614	0	0
T13	220096	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2710923	0	0
T1	288743	96	0	0
T2	437613	1336	0	0
T3	14975	116	0	0
T7	9295	67	0	0
T8	338148	5230	0	0
T9	454278	1602	0	0
T10	77715	877	0	0
T11	428630	2222	0	0
T12	165594	1132	0	0
T13	220096	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202842	0	0
T1	288743	18	0	0
T2	437613	423	0	0
T3	14975	19	0	0
T7	9295	68	0	0
T8	338148	13	0	0
T9	454278	496	0	0
T10	77715	894	0	0
T11	428630	7	0	0
T12	165594	1614	0	0
T13	220096	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202842	0	0
T1	288743	18	0	0
T2	437613	423	0	0
T3	14975	19	0	0
T7	9295	68	0	0
T8	338148	13	0	0
T9	454278	496	0	0
T10	77715	894	0	0
T11	428630	7	0	0
T12	165594	1614	0	0
T13	220096	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	529971	0	0
T1	288743	31	0	0
T2	437613	1059	0	0
T3	14975	31	0	0
T7	9295	70	0	0
T8	338148	13	0	0
T9	454278	1130	0	0
T10	77715	915	0	0
T11	428630	7	0	0
T12	165594	2116	0	0
T13	220096	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202842	0	0
T1	288743	18	0	0
T2	437613	423	0	0
T3	14975	19	0	0
T7	9295	68	0	0
T8	338148	13	0	0
T9	454278	496	0	0
T10	77715	894	0	0
T11	428630	7	0	0
T12	165594	1614	0	0
T13	220096	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	202958	0	0
GntImpliesValid_A	410573884	202958	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	202958	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	5203416	0	0
ReadyAndValidImplyGrant_A	410573884	202958	0	0
ReqAndReadyImplyGrant_A	410573884	202958	0	0
ReqImpliesValid_A	410573884	1085134	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	202958	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202958	0	0
T1	288743	17	0	0
T2	437613	0	0	0
T3	14975	10	0	0
T7	9295	106	0	0
T8	338148	8	0	0
T9	454278	483	0	0
T10	77715	976	0	0
T11	428630	19	0	0
T12	165594	1162	0	0
T13	220096	15	0	0
T14	0	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202958	0	0
T1	288743	17	0	0
T2	437613	0	0	0
T3	14975	10	0	0
T7	9295	106	0	0
T8	338148	8	0	0
T9	454278	483	0	0
T10	77715	976	0	0
T11	428630	19	0	0
T12	165594	1162	0	0
T13	220096	15	0	0
T14	0	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202958	0	0
T1	288743	17	0	0
T2	437613	0	0	0
T3	14975	10	0	0
T7	9295	106	0	0
T8	338148	8	0	0
T9	454278	483	0	0
T10	77715	976	0	0
T11	428630	19	0	0
T12	165594	1162	0	0
T13	220096	15	0	0
T14	0	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	5203416	0	0
T1	288743	228	0	0
T2	437613	0	0	0
T3	14975	114	0	0
T7	9295	808	0	0
T8	338148	2077	0	0
T9	454278	1419	0	0
T10	77715	7905	0	0
T11	428630	1376	0	0
T12	165594	15923	0	0
T13	220096	62	0	0
T14	0	269	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202958	0	0
T1	288743	17	0	0
T2	437613	0	0	0
T3	14975	10	0	0
T7	9295	106	0	0
T8	338148	8	0	0
T9	454278	483	0	0
T10	77715	976	0	0
T11	428630	19	0	0
T12	165594	1162	0	0
T13	220096	15	0	0
T14	0	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202958	0	0
T1	288743	17	0	0
T2	437613	0	0	0
T3	14975	10	0	0
T7	9295	106	0	0
T8	338148	8	0	0
T9	454278	483	0	0
T10	77715	976	0	0
T11	428630	19	0	0
T12	165594	1162	0	0
T13	220096	15	0	0
T14	0	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	1085134	0	0
T1	288743	28	0	0
T2	437613	0	0	0
T3	14975	10	0	0
T7	9295	228	0	0
T8	338148	8	0	0
T9	454278	1016	0	0
T10	77715	1516	0	0
T11	428630	56	0	0
T12	165594	2594	0	0
T13	220096	19	0	0
T14	0	76	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202958	0	0
T1	288743	17	0	0
T2	437613	0	0	0
T3	14975	10	0	0
T7	9295	106	0	0
T8	338148	8	0	0
T9	454278	483	0	0
T10	77715	976	0	0
T11	428630	19	0	0
T12	165594	1162	0	0
T13	220096	15	0	0
T14	0	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	199892	0	0
GntImpliesValid_A	410573884	199892	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	199892	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	5373100	0	0
ReadyAndValidImplyGrant_A	410573884	199892	0	0
ReqAndReadyImplyGrant_A	410573884	199892	0	0
ReqImpliesValid_A	410573884	1161669	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	199892	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199892	0	0
T1	288743	9	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	102	0	0
T8	338148	14	0	0
T9	454278	0	0	0
T10	77715	907	0	0
T11	428630	16	0	0
T12	165594	1801	0	0
T13	220096	12	0	0
T14	0	35	0	0
T15	0	680	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199892	0	0
T1	288743	9	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	102	0	0
T8	338148	14	0	0
T9	454278	0	0	0
T10	77715	907	0	0
T11	428630	16	0	0
T12	165594	1801	0	0
T13	220096	12	0	0
T14	0	35	0	0
T15	0	680	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199892	0	0
T1	288743	9	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	102	0	0
T8	338148	14	0	0
T9	454278	0	0	0
T10	77715	907	0	0
T11	428630	16	0	0
T12	165594	1801	0	0
T13	220096	12	0	0
T14	0	35	0	0
T15	0	680	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	5373100	0	0
T1	288743	275	0	0
T2	437613	0	0	0
T3	14975	156	0	0
T7	9295	641	0	0
T8	338148	4284	0	0
T9	454278	0	0	0
T10	77715	14148	0	0
T11	428630	1882	0	0
T12	165594	22022	0	0
T13	220096	55	0	0
T14	0	231	0	0
T15	0	12122	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199892	0	0
T1	288743	9	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	102	0	0
T8	338148	14	0	0
T9	454278	0	0	0
T10	77715	907	0	0
T11	428630	16	0	0
T12	165594	1801	0	0
T13	220096	12	0	0
T14	0	35	0	0
T15	0	680	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199892	0	0
T1	288743	9	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	102	0	0
T8	338148	14	0	0
T9	454278	0	0	0
T10	77715	907	0	0
T11	428630	16	0	0
T12	165594	1801	0	0
T13	220096	12	0	0
T14	0	35	0	0
T15	0	680	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	1161669	0	0
T1	288743	9	0	0
T2	437613	0	0	0
T3	14975	20	0	0
T7	9295	156	0	0
T8	338148	14	0	0
T9	454278	0	0	0
T10	77715	2231	0	0
T11	428630	16	0	0
T12	165594	13910	0	0
T13	220096	12	0	0
T14	0	51	0	0
T15	0	964	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199892	0	0
T1	288743	9	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	102	0	0
T8	338148	14	0	0
T9	454278	0	0	0
T10	77715	907	0	0
T11	428630	16	0	0
T12	165594	1801	0	0
T13	220096	12	0	0
T14	0	35	0	0
T15	0	680	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	194324	0	0
GntImpliesValid_A	410573884	194324	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	194324	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	5174810	0	0
ReadyAndValidImplyGrant_A	410573884	194324	0	0
ReqAndReadyImplyGrant_A	410573884	194324	0	0
ReqImpliesValid_A	410573884	1037927	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	194324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194324	0	0
T1	288743	14	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	470	0	0
T10	77715	927	0	0
T11	428630	15	0	0
T12	165594	1193	0	0
T13	220096	7	0	0
T14	0	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194324	0	0
T1	288743	14	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	470	0	0
T10	77715	927	0	0
T11	428630	15	0	0
T12	165594	1193	0	0
T13	220096	7	0	0
T14	0	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194324	0	0
T1	288743	14	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	470	0	0
T10	77715	927	0	0
T11	428630	15	0	0
T12	165594	1193	0	0
T13	220096	7	0	0
T14	0	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	5174810	0	0
T1	288743	172	0	0
T2	437613	0	0	0
T3	14975	173	0	0
T7	9295	874	0	0
T8	338148	946	0	0
T9	454278	1836	0	0
T10	77715	6376	0	0
T11	428630	6661	0	0
T12	165594	7414	0	0
T13	220096	24	0	0
T14	0	292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194324	0	0
T1	288743	14	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	470	0	0
T10	77715	927	0	0
T11	428630	15	0	0
T12	165594	1193	0	0
T13	220096	7	0	0
T14	0	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194324	0	0
T1	288743	14	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	470	0	0
T10	77715	927	0	0
T11	428630	15	0	0
T12	165594	1193	0	0
T13	220096	7	0	0
T14	0	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	1037927	0	0
T1	288743	20	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	218	0	0
T8	338148	154	0	0
T9	454278	1204	0	0
T10	77715	1343	0	0
T11	428630	1103	0	0
T12	165594	1539	0	0
T13	220096	15	0	0
T14	0	86	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194324	0	0
T1	288743	14	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	470	0	0
T10	77715	927	0	0
T11	428630	15	0	0
T12	165594	1193	0	0
T13	220096	7	0	0
T14	0	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	206617	0	0
GntImpliesValid_A	410573884	206617	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	206617	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	5060593	0	0
ReadyAndValidImplyGrant_A	410573884	206617	0	0
ReqAndReadyImplyGrant_A	410573884	206617	0	0
ReqImpliesValid_A	410573884	1061895	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	206617	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206617	0	0
T1	288743	13	0	0
T2	437613	947	0	0
T3	14975	20	0	0
T7	9295	99	0	0
T8	338148	12	0	0
T9	454278	0	0	0
T10	77715	923	0	0
T11	428630	14	0	0
T12	165594	1293	0	0
T13	220096	11	0	0
T14	0	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206617	0	0
T1	288743	13	0	0
T2	437613	947	0	0
T3	14975	20	0	0
T7	9295	99	0	0
T8	338148	12	0	0
T9	454278	0	0	0
T10	77715	923	0	0
T11	428630	14	0	0
T12	165594	1293	0	0
T13	220096	11	0	0
T14	0	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206617	0	0
T1	288743	13	0	0
T2	437613	947	0	0
T3	14975	20	0	0
T7	9295	99	0	0
T8	338148	12	0	0
T9	454278	0	0	0
T10	77715	923	0	0
T11	428630	14	0	0
T12	165594	1293	0	0
T13	220096	11	0	0
T14	0	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	5060593	0	0
T1	288743	105	0	0
T2	437613	4217	0	0
T3	14975	354	0	0
T7	9295	1318	0	0
T8	338148	3019	0	0
T9	454278	0	0	0
T10	77715	7272	0	0
T11	428630	1898	0	0
T12	165594	23091	0	0
T13	220096	64	0	0
T14	0	206	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206617	0	0
T1	288743	13	0	0
T2	437613	947	0	0
T3	14975	20	0	0
T7	9295	99	0	0
T8	338148	12	0	0
T9	454278	0	0	0
T10	77715	923	0	0
T11	428630	14	0	0
T12	165594	1293	0	0
T13	220096	11	0	0
T14	0	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206617	0	0
T1	288743	13	0	0
T2	437613	947	0	0
T3	14975	20	0	0
T7	9295	99	0	0
T8	338148	12	0	0
T9	454278	0	0	0
T10	77715	923	0	0
T11	428630	14	0	0
T12	165594	1293	0	0
T13	220096	11	0	0
T14	0	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	1061895	0	0
T1	288743	13	0	0
T2	437613	2433	0	0
T3	14975	54	0	0
T7	9295	229	0	0
T8	338148	168	0	0
T9	454278	0	0	0
T10	77715	1512	0	0
T11	428630	143	0	0
T12	165594	4966	0	0
T13	220096	15	0	0
T14	0	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206617	0	0
T1	288743	13	0	0
T2	437613	947	0	0
T3	14975	20	0	0
T7	9295	99	0	0
T8	338148	12	0	0
T9	454278	0	0	0
T10	77715	923	0	0
T11	428630	14	0	0
T12	165594	1293	0	0
T13	220096	11	0	0
T14	0	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	204615	0	0
GntImpliesValid_A	410573884	204615	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	204615	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2773823	0	0
ReadyAndValidImplyGrant_A	410573884	204615	0	0
ReqAndReadyImplyGrant_A	410573884	204615	0	0
ReqImpliesValid_A	410573884	561764	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	204615	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204615	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	13	0	0
T9	454278	0	0	0
T10	77715	902	0	0
T11	428630	13	0	0
T12	165594	2181	0	0
T13	220096	11	0	0
T14	0	58	0	0
T15	0	1162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204615	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	13	0	0
T9	454278	0	0	0
T10	77715	902	0	0
T11	428630	13	0	0
T12	165594	2181	0	0
T13	220096	11	0	0
T14	0	58	0	0
T15	0	1162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204615	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	13	0	0
T9	454278	0	0	0
T10	77715	902	0	0
T11	428630	13	0	0
T12	165594	2181	0	0
T13	220096	11	0	0
T14	0	58	0	0
T15	0	1162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2773823	0	0
T1	288743	48	0	0
T2	437613	1	0	0
T3	14975	104	0	0
T7	9295	82	0	0
T8	338148	4160	0	0
T9	454278	1	0	0
T10	77715	888	0	0
T11	428630	4833	0	0
T12	165594	1400	0	0
T13	220096	57	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204615	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	13	0	0
T9	454278	0	0	0
T10	77715	902	0	0
T11	428630	13	0	0
T12	165594	2181	0	0
T13	220096	11	0	0
T14	0	58	0	0
T15	0	1162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204615	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	13	0	0
T9	454278	0	0	0
T10	77715	902	0	0
T11	428630	13	0	0
T12	165594	2181	0	0
T13	220096	11	0	0
T14	0	58	0	0
T15	0	1162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	561764	0	0
T1	288743	13	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	87	0	0
T8	338148	13	0	0
T9	454278	0	0	0
T10	77715	920	0	0
T11	428630	206	0	0
T12	165594	2982	0	0
T13	220096	14	0	0
T14	0	64	0	0
T15	0	2807	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204615	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	13	0	0
T9	454278	0	0	0
T10	77715	902	0	0
T11	428630	13	0	0
T12	165594	2181	0	0
T13	220096	11	0	0
T14	0	58	0	0
T15	0	1162	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	214806	0	0
GntImpliesValid_A	410573884	214806	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	214806	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2768312	0	0
ReadyAndValidImplyGrant_A	410573884	214806	0	0
ReqAndReadyImplyGrant_A	410573884	214806	0	0
ReqImpliesValid_A	410573884	592084	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	214806	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214806	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	21	0	0
T7	9295	74	0	0
T8	338148	12	0	0
T9	454278	1049	0	0
T10	77715	973	0	0
T11	428630	9	0	0
T12	165594	2261	0	0
T13	220096	11	0	0
T14	0	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214806	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	21	0	0
T7	9295	74	0	0
T8	338148	12	0	0
T9	454278	1049	0	0
T10	77715	973	0	0
T11	428630	9	0	0
T12	165594	2261	0	0
T13	220096	11	0	0
T14	0	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214806	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	21	0	0
T7	9295	74	0	0
T8	338148	12	0	0
T9	454278	1049	0	0
T10	77715	973	0	0
T11	428630	9	0	0
T12	165594	2261	0	0
T13	220096	11	0	0
T14	0	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2768312	0	0
T1	288743	58	0	0
T2	437613	1	0	0
T3	14975	163	0	0
T7	9295	71	0	0
T8	338148	3764	0	0
T9	454278	3544	0	0
T10	77715	949	0	0
T11	428630	4227	0	0
T12	165594	1213	0	0
T13	220096	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214806	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	21	0	0
T7	9295	74	0	0
T8	338148	12	0	0
T9	454278	1049	0	0
T10	77715	973	0	0
T11	428630	9	0	0
T12	165594	2261	0	0
T13	220096	11	0	0
T14	0	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214806	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	21	0	0
T7	9295	74	0	0
T8	338148	12	0	0
T9	454278	1049	0	0
T10	77715	973	0	0
T11	428630	9	0	0
T12	165594	2261	0	0
T13	220096	11	0	0
T14	0	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	592084	0	0
T1	288743	16	0	0
T2	437613	0	0	0
T3	14975	25	0	0
T7	9295	78	0	0
T8	338148	334	0	0
T9	454278	2382	0	0
T10	77715	1001	0	0
T11	428630	9	0	0
T12	165594	3329	0	0
T13	220096	19	0	0
T14	0	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	214806	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	21	0	0
T7	9295	74	0	0
T8	338148	12	0	0
T9	454278	1049	0	0
T10	77715	973	0	0
T11	428630	9	0	0
T12	165594	2261	0	0
T13	220096	11	0	0
T14	0	52	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	206233	0	0
GntImpliesValid_A	410573884	206233	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	206233	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2750598	0	0
ReadyAndValidImplyGrant_A	410573884	206233	0	0
ReqAndReadyImplyGrant_A	410573884	206233	0	0
ReqImpliesValid_A	410573884	531641	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	206233	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206233	0	0
T1	288743	13	0	0
T2	437613	993	0	0
T3	14975	15	0	0
T7	9295	78	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	965	0	0
T11	428630	11	0	0
T12	165594	1596	0	0
T13	220096	9	0	0
T14	0	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206233	0	0
T1	288743	13	0	0
T2	437613	993	0	0
T3	14975	15	0	0
T7	9295	78	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	965	0	0
T11	428630	11	0	0
T12	165594	1596	0	0
T13	220096	9	0	0
T14	0	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206233	0	0
T1	288743	13	0	0
T2	437613	993	0	0
T3	14975	15	0	0
T7	9295	78	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	965	0	0
T11	428630	11	0	0
T12	165594	1596	0	0
T13	220096	9	0	0
T14	0	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2750598	0	0
T1	288743	57	0	0
T2	437613	3289	0	0
T3	14975	98	0	0
T7	9295	74	0	0
T8	338148	2817	0	0
T9	454278	1	0	0
T10	77715	940	0	0
T11	428630	2822	0	0
T12	165594	1352	0	0
T13	220096	39	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206233	0	0
T1	288743	13	0	0
T2	437613	993	0	0
T3	14975	15	0	0
T7	9295	78	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	965	0	0
T11	428630	11	0	0
T12	165594	1596	0	0
T13	220096	9	0	0
T14	0	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206233	0	0
T1	288743	13	0	0
T2	437613	993	0	0
T3	14975	15	0	0
T7	9295	78	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	965	0	0
T11	428630	11	0	0
T12	165594	1596	0	0
T13	220096	9	0	0
T14	0	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	531641	0	0
T1	288743	17	0	0
T2	437613	2408	0	0
T3	14975	24	0	0
T7	9295	83	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	994	0	0
T11	428630	350	0	0
T12	165594	1860	0	0
T13	220096	9	0	0
T14	0	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	206233	0	0
T1	288743	13	0	0
T2	437613	993	0	0
T3	14975	15	0	0
T7	9295	78	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	965	0	0
T11	428630	11	0	0
T12	165594	1596	0	0
T13	220096	9	0	0
T14	0	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	199493	0	0
GntImpliesValid_A	410573884	199493	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	199493	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2756054	0	0
ReadyAndValidImplyGrant_A	410573884	199493	0	0
ReqAndReadyImplyGrant_A	410573884	199493	0	0
ReqImpliesValid_A	410573884	513478	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	199493	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199493	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	15	0	0
T7	9295	72	0	0
T8	338148	7	0	0
T9	454278	465	0	0
T10	77715	913	0	0
T11	428630	10	0	0
T12	165594	1175	0	0
T13	220096	10	0	0
T14	0	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199493	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	15	0	0
T7	9295	72	0	0
T8	338148	7	0	0
T9	454278	465	0	0
T10	77715	913	0	0
T11	428630	10	0	0
T12	165594	1175	0	0
T13	220096	10	0	0
T14	0	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199493	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	15	0	0
T7	9295	72	0	0
T8	338148	7	0	0
T9	454278	465	0	0
T10	77715	913	0	0
T11	428630	10	0	0
T12	165594	1175	0	0
T13	220096	10	0	0
T14	0	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2756054	0	0
T1	288743	55	0	0
T2	437613	1	0	0
T3	14975	110	0	0
T7	9295	71	0	0
T8	338148	3569	0	0
T9	454278	1400	0	0
T10	77715	887	0	0
T11	428630	2238	0	0
T12	165594	1155	0	0
T13	220096	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199493	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	15	0	0
T7	9295	72	0	0
T8	338148	7	0	0
T9	454278	465	0	0
T10	77715	913	0	0
T11	428630	10	0	0
T12	165594	1175	0	0
T13	220096	10	0	0
T14	0	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199493	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	15	0	0
T7	9295	72	0	0
T8	338148	7	0	0
T9	454278	465	0	0
T10	77715	913	0	0
T11	428630	10	0	0
T12	165594	1175	0	0
T13	220096	10	0	0
T14	0	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	513478	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	46	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	1239	0	0
T10	77715	943	0	0
T11	428630	94	0	0
T12	165594	1215	0	0
T13	220096	17	0	0
T14	0	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199493	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	15	0	0
T7	9295	72	0	0
T8	338148	7	0	0
T9	454278	465	0	0
T10	77715	913	0	0
T11	428630	10	0	0
T12	165594	1175	0	0
T13	220096	10	0	0
T14	0	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	200684	0	0
GntImpliesValid_A	410573884	200684	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	200684	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2719251	0	0
ReadyAndValidImplyGrant_A	410573884	200684	0	0
ReqAndReadyImplyGrant_A	410573884	200684	0	0
ReqImpliesValid_A	410573884	527347	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	200684	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	200684	0	0
T1	288743	19	0	0
T2	437613	461	0	0
T3	14975	14	0	0
T7	9295	96	0	0
T8	338148	8	0	0
T9	454278	0	0	0
T10	77715	960	0	0
T11	428630	15	0	0
T12	165594	1103	0	0
T13	220096	10	0	0
T14	0	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	200684	0	0
T1	288743	19	0	0
T2	437613	461	0	0
T3	14975	14	0	0
T7	9295	96	0	0
T8	338148	8	0	0
T9	454278	0	0	0
T10	77715	960	0	0
T11	428630	15	0	0
T12	165594	1103	0	0
T13	220096	10	0	0
T14	0	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	200684	0	0
T1	288743	19	0	0
T2	437613	461	0	0
T3	14975	14	0	0
T7	9295	96	0	0
T8	338148	8	0	0
T9	454278	0	0	0
T10	77715	960	0	0
T11	428630	15	0	0
T12	165594	1103	0	0
T13	220096	10	0	0
T14	0	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2719251	0	0
T1	288743	80	0	0
T2	437613	1540	0	0
T3	14975	104	0	0
T7	9295	95	0	0
T8	338148	2048	0	0
T9	454278	1	0	0
T10	77715	933	0	0
T11	428630	5693	0	0
T12	165594	1102	0	0
T13	220096	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	200684	0	0
T1	288743	19	0	0
T2	437613	461	0	0
T3	14975	14	0	0
T7	9295	96	0	0
T8	338148	8	0	0
T9	454278	0	0	0
T10	77715	960	0	0
T11	428630	15	0	0
T12	165594	1103	0	0
T13	220096	10	0	0
T14	0	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	200684	0	0
T1	288743	19	0	0
T2	437613	461	0	0
T3	14975	14	0	0
T7	9295	96	0	0
T8	338148	8	0	0
T9	454278	0	0	0
T10	77715	960	0	0
T11	428630	15	0	0
T12	165594	1103	0	0
T13	220096	10	0	0
T14	0	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	527347	0	0
T1	288743	19	0	0
T2	437613	1002	0	0
T3	14975	14	0	0
T7	9295	98	0	0
T8	338148	736	0	0
T9	454278	0	0	0
T10	77715	991	0	0
T11	428630	1857	0	0
T12	165594	1124	0	0
T13	220096	10	0	0
T14	0	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	200684	0	0
T1	288743	19	0	0
T2	437613	461	0	0
T3	14975	14	0	0
T7	9295	96	0	0
T8	338148	8	0	0
T9	454278	0	0	0
T10	77715	960	0	0
T11	428630	15	0	0
T12	165594	1103	0	0
T13	220096	10	0	0
T14	0	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	204369	0	0
GntImpliesValid_A	410573884	204369	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	204369	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2708125	0	0
ReadyAndValidImplyGrant_A	410573884	204369	0	0
ReqAndReadyImplyGrant_A	410573884	204369	0	0
ReqImpliesValid_A	410573884	504951	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	204369	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204369	0	0
T1	288743	8	0	0
T2	437613	471	0	0
T3	14975	19	0	0
T7	9295	74	0	0
T8	338148	9	0	0
T9	454278	0	0	0
T10	77715	928	0	0
T11	428630	12	0	0
T12	165594	2273	0	0
T13	220096	14	0	0
T14	0	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204369	0	0
T1	288743	8	0	0
T2	437613	471	0	0
T3	14975	19	0	0
T7	9295	74	0	0
T8	338148	9	0	0
T9	454278	0	0	0
T10	77715	928	0	0
T11	428630	12	0	0
T12	165594	2273	0	0
T13	220096	14	0	0
T14	0	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204369	0	0
T1	288743	8	0	0
T2	437613	471	0	0
T3	14975	19	0	0
T7	9295	74	0	0
T8	338148	9	0	0
T9	454278	0	0	0
T10	77715	928	0	0
T11	428630	12	0	0
T12	165594	2273	0	0
T13	220096	14	0	0
T14	0	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2708125	0	0
T1	288743	52	0	0
T2	437613	1527	0	0
T3	14975	175	0	0
T7	9295	71	0	0
T8	338148	1458	0	0
T9	454278	1	0	0
T10	77715	905	0	0
T11	428630	5890	0	0
T12	165594	1605	0	0
T13	220096	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204369	0	0
T1	288743	8	0	0
T2	437613	471	0	0
T3	14975	19	0	0
T7	9295	74	0	0
T8	338148	9	0	0
T9	454278	0	0	0
T10	77715	928	0	0
T11	428630	12	0	0
T12	165594	2273	0	0
T13	220096	14	0	0
T14	0	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204369	0	0
T1	288743	8	0	0
T2	437613	471	0	0
T3	14975	19	0	0
T7	9295	74	0	0
T8	338148	9	0	0
T9	454278	0	0	0
T10	77715	928	0	0
T11	428630	12	0	0
T12	165594	2273	0	0
T13	220096	14	0	0
T14	0	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	504951	0	0
T1	288743	8	0	0
T2	437613	1084	0	0
T3	14975	30	0	0
T7	9295	78	0	0
T8	338148	9	0	0
T9	454278	0	0	0
T10	77715	955	0	0
T11	428630	226	0	0
T12	165594	2961	0	0
T13	220096	14	0	0
T14	0	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	204369	0	0
T1	288743	8	0	0
T2	437613	471	0	0
T3	14975	19	0	0
T7	9295	74	0	0
T8	338148	9	0	0
T9	454278	0	0	0
T10	77715	928	0	0
T11	428630	12	0	0
T12	165594	2273	0	0
T13	220096	14	0	0
T14	0	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	210957	0	0
GntImpliesValid_A	410573884	210957	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	210957	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2836097	0	0
ReadyAndValidImplyGrant_A	410573884	210957	0	0
ReqAndReadyImplyGrant_A	410573884	210957	0	0
ReqImpliesValid_A	410573884	556340	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	210957	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	210957	0	0
T1	288743	10	0	0
T2	437613	464	0	0
T3	14975	18	0	0
T7	9295	101	0	0
T8	338148	11	0	0
T9	454278	996	0	0
T10	77715	872	0	0
T11	428630	11	0	0
T12	165594	1183	0	0
T13	220096	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	210957	0	0
T1	288743	10	0	0
T2	437613	464	0	0
T3	14975	18	0	0
T7	9295	101	0	0
T8	338148	11	0	0
T9	454278	996	0	0
T10	77715	872	0	0
T11	428630	11	0	0
T12	165594	1183	0	0
T13	220096	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	210957	0	0
T1	288743	10	0	0
T2	437613	464	0	0
T3	14975	18	0	0
T7	9295	101	0	0
T8	338148	11	0	0
T9	454278	996	0	0
T10	77715	872	0	0
T11	428630	11	0	0
T12	165594	1183	0	0
T13	220096	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2836097	0	0
T1	288743	32	0	0
T2	437613	1549	0	0
T3	14975	97	0	0
T7	9295	95	0	0
T8	338148	3943	0	0
T9	454278	3200	0	0
T10	77715	857	0	0
T11	428630	3008	0	0
T12	165594	1177	0	0
T13	220096	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	210957	0	0
T1	288743	10	0	0
T2	437613	464	0	0
T3	14975	18	0	0
T7	9295	101	0	0
T8	338148	11	0	0
T9	454278	996	0	0
T10	77715	872	0	0
T11	428630	11	0	0
T12	165594	1183	0	0
T13	220096	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	210957	0	0
T1	288743	10	0	0
T2	437613	464	0	0
T3	14975	18	0	0
T7	9295	101	0	0
T8	338148	11	0	0
T9	454278	996	0	0
T10	77715	872	0	0
T11	428630	11	0	0
T12	165594	1183	0	0
T13	220096	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	556340	0	0
T1	288743	10	0	0
T2	437613	1138	0	0
T3	14975	26	0	0
T7	9295	108	0	0
T8	338148	135	0	0
T9	454278	2332	0	0
T10	77715	891	0	0
T11	428630	11	0	0
T12	165594	1209	0	0
T13	220096	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	210957	0	0
T1	288743	10	0	0
T2	437613	464	0	0
T3	14975	18	0	0
T7	9295	101	0	0
T8	338148	11	0	0
T9	454278	996	0	0
T10	77715	872	0	0
T11	428630	11	0	0
T12	165594	1183	0	0
T13	220096	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	209113	0	0
GntImpliesValid_A	410573884	209113	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	209113	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2821884	0	0
ReadyAndValidImplyGrant_A	410573884	209113	0	0
ReqAndReadyImplyGrant_A	410573884	209113	0	0
ReqImpliesValid_A	410573884	570835	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	209113	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	209113	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	18	0	0
T7	9295	91	0	0
T8	338148	13	0	0
T9	454278	517	0	0
T10	77715	851	0	0
T11	428630	8	0	0
T12	165594	2572	0	0
T13	220096	18	0	0
T14	0	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	209113	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	18	0	0
T7	9295	91	0	0
T8	338148	13	0	0
T9	454278	517	0	0
T10	77715	851	0	0
T11	428630	8	0	0
T12	165594	2572	0	0
T13	220096	18	0	0
T14	0	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	209113	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	18	0	0
T7	9295	91	0	0
T8	338148	13	0	0
T9	454278	517	0	0
T10	77715	851	0	0
T11	428630	8	0	0
T12	165594	2572	0	0
T13	220096	18	0	0
T14	0	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2821884	0	0
T1	288743	71	0	0
T2	437613	1	0	0
T3	14975	146	0	0
T7	9295	87	0	0
T8	338148	5306	0	0
T9	454278	1747	0	0
T10	77715	832	0	0
T11	428630	1287	0	0
T12	165594	1450	0	0
T13	220096	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	209113	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	18	0	0
T7	9295	91	0	0
T8	338148	13	0	0
T9	454278	517	0	0
T10	77715	851	0	0
T11	428630	8	0	0
T12	165594	2572	0	0
T13	220096	18	0	0
T14	0	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	209113	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	18	0	0
T7	9295	91	0	0
T8	338148	13	0	0
T9	454278	517	0	0
T10	77715	851	0	0
T11	428630	8	0	0
T12	165594	2572	0	0
T13	220096	18	0	0
T14	0	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	570835	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	18	0	0
T7	9295	96	0	0
T8	338148	13	0	0
T9	454278	1195	0	0
T10	77715	874	0	0
T11	428630	538	0	0
T12	165594	3713	0	0
T13	220096	26	0	0
T14	0	58	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	209113	0	0
T1	288743	12	0	0
T2	437613	0	0	0
T3	14975	18	0	0
T7	9295	91	0	0
T8	338148	13	0	0
T9	454278	517	0	0
T10	77715	851	0	0
T11	428630	8	0	0
T12	165594	2572	0	0
T13	220096	18	0	0
T14	0	52	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	227392	0	0
GntImpliesValid_A	410573884	227392	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	227392	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2853583	0	0
ReadyAndValidImplyGrant_A	410573884	227392	0	0
ReqAndReadyImplyGrant_A	410573884	227392	0	0
ReqImpliesValid_A	410573884	560653	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	227392	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	227392	0	0
T1	288743	15	0	0
T2	437613	1081	0	0
T3	14975	13	0	0
T7	9295	149	0	0
T8	338148	14	0	0
T9	454278	428	0	0
T10	77715	981	0	0
T11	428630	19	0	0
T12	165594	1421	0	0
T13	220096	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	227392	0	0
T1	288743	15	0	0
T2	437613	1081	0	0
T3	14975	13	0	0
T7	9295	149	0	0
T8	338148	14	0	0
T9	454278	428	0	0
T10	77715	981	0	0
T11	428630	19	0	0
T12	165594	1421	0	0
T13	220096	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	227392	0	0
T1	288743	15	0	0
T2	437613	1081	0	0
T3	14975	13	0	0
T7	9295	149	0	0
T8	338148	14	0	0
T9	454278	428	0	0
T10	77715	981	0	0
T11	428630	19	0	0
T12	165594	1421	0	0
T13	220096	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2853583	0	0
T1	288743	70	0	0
T2	437613	3705	0	0
T3	14975	107	0	0
T7	9295	142	0	0
T8	338148	4590	0	0
T9	454278	1420	0	0
T10	77715	958	0	0
T11	428630	5641	0	0
T12	165594	1397	0	0
T13	220096	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	227392	0	0
T1	288743	15	0	0
T2	437613	1081	0	0
T3	14975	13	0	0
T7	9295	149	0	0
T8	338148	14	0	0
T9	454278	428	0	0
T10	77715	981	0	0
T11	428630	19	0	0
T12	165594	1421	0	0
T13	220096	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	227392	0	0
T1	288743	15	0	0
T2	437613	1081	0	0
T3	14975	13	0	0
T7	9295	149	0	0
T8	338148	14	0	0
T9	454278	428	0	0
T10	77715	981	0	0
T11	428630	19	0	0
T12	165594	1421	0	0
T13	220096	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	560653	0	0
T1	288743	19	0	0
T2	437613	2363	0	0
T3	14975	21	0	0
T7	9295	157	0	0
T8	338148	206	0	0
T9	454278	1102	0	0
T10	77715	1008	0	0
T11	428630	36	0	0
T12	165594	1465	0	0
T13	220096	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	227392	0	0
T1	288743	15	0	0
T2	437613	1081	0	0
T3	14975	13	0	0
T7	9295	149	0	0
T8	338148	14	0	0
T9	454278	428	0	0
T10	77715	981	0	0
T11	428630	19	0	0
T12	165594	1421	0	0
T13	220096	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	218828	0	0
GntImpliesValid_A	410573884	218828	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	218828	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2794401	0	0
ReadyAndValidImplyGrant_A	410573884	218828	0	0
ReqAndReadyImplyGrant_A	410573884	218828	0	0
ReqImpliesValid_A	410573884	613624	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	218828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	218828	0	0
T1	288743	8	0	0
T2	437613	516	0	0
T3	14975	17	0	0
T7	9295	90	0	0
T8	338148	16	0	0
T9	454278	441	0	0
T10	77715	1413	0	0
T11	428630	14	0	0
T12	165594	2600	0	0
T13	220096	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	218828	0	0
T1	288743	8	0	0
T2	437613	516	0	0
T3	14975	17	0	0
T7	9295	90	0	0
T8	338148	16	0	0
T9	454278	441	0	0
T10	77715	1413	0	0
T11	428630	14	0	0
T12	165594	2600	0	0
T13	220096	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	218828	0	0
T1	288743	8	0	0
T2	437613	516	0	0
T3	14975	17	0	0
T7	9295	90	0	0
T8	338148	16	0	0
T9	454278	441	0	0
T10	77715	1413	0	0
T11	428630	14	0	0
T12	165594	2600	0	0
T13	220096	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2794401	0	0
T1	288743	37	0	0
T2	437613	1695	0	0
T3	14975	110	0	0
T7	9295	87	0	0
T8	338148	4015	0	0
T9	454278	1470	0	0
T10	77715	1315	0	0
T11	428630	4081	0	0
T12	165594	2058	0	0
T13	220096	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	218828	0	0
T1	288743	8	0	0
T2	437613	516	0	0
T3	14975	17	0	0
T7	9295	90	0	0
T8	338148	16	0	0
T9	454278	441	0	0
T10	77715	1413	0	0
T11	428630	14	0	0
T12	165594	2600	0	0
T13	220096	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	218828	0	0
T1	288743	8	0	0
T2	437613	516	0	0
T3	14975	17	0	0
T7	9295	90	0	0
T8	338148	16	0	0
T9	454278	441	0	0
T10	77715	1413	0	0
T11	428630	14	0	0
T12	165594	2600	0	0
T13	220096	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	613624	0	0
T1	288743	10	0	0
T2	437613	1110	0	0
T3	14975	17	0	0
T7	9295	94	0	0
T8	338148	16	0	0
T9	454278	1166	0	0
T10	77715	1515	0	0
T11	428630	36	0	0
T12	165594	3162	0	0
T13	220096	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	218828	0	0
T1	288743	8	0	0
T2	437613	516	0	0
T3	14975	17	0	0
T7	9295	90	0	0
T8	338148	16	0	0
T9	454278	441	0	0
T10	77715	1413	0	0
T11	428630	14	0	0
T12	165594	2600	0	0
T13	220096	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	199045	0	0
GntImpliesValid_A	410573884	199045	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	199045	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2763780	0	0
ReadyAndValidImplyGrant_A	410573884	199045	0	0
ReqAndReadyImplyGrant_A	410573884	199045	0	0
ReqImpliesValid_A	410573884	512210	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	199045	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199045	0	0
T1	288743	5	0	0
T2	437613	0	0	0
T3	14975	20	0	0
T7	9295	79	0	0
T8	338148	4	0	0
T9	454278	0	0	0
T10	77715	957	0	0
T11	428630	14	0	0
T12	165594	1165	0	0
T13	220096	10	0	0
T14	0	54	0	0
T15	0	1095	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199045	0	0
T1	288743	5	0	0
T2	437613	0	0	0
T3	14975	20	0	0
T7	9295	79	0	0
T8	338148	4	0	0
T9	454278	0	0	0
T10	77715	957	0	0
T11	428630	14	0	0
T12	165594	1165	0	0
T13	220096	10	0	0
T14	0	54	0	0
T15	0	1095	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199045	0	0
T1	288743	5	0	0
T2	437613	0	0	0
T3	14975	20	0	0
T7	9295	79	0	0
T8	338148	4	0	0
T9	454278	0	0	0
T10	77715	957	0	0
T11	428630	14	0	0
T12	165594	1165	0	0
T13	220096	10	0	0
T14	0	54	0	0
T15	0	1095	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2763780	0	0
T1	288743	26	0	0
T2	437613	1	0	0
T3	14975	172	0	0
T7	9295	77	0	0
T8	338148	1014	0	0
T9	454278	1	0	0
T10	77715	942	0	0
T11	428630	3783	0	0
T12	165594	1158	0	0
T13	220096	35	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199045	0	0
T1	288743	5	0	0
T2	437613	0	0	0
T3	14975	20	0	0
T7	9295	79	0	0
T8	338148	4	0	0
T9	454278	0	0	0
T10	77715	957	0	0
T11	428630	14	0	0
T12	165594	1165	0	0
T13	220096	10	0	0
T14	0	54	0	0
T15	0	1095	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199045	0	0
T1	288743	5	0	0
T2	437613	0	0	0
T3	14975	20	0	0
T7	9295	79	0	0
T8	338148	4	0	0
T9	454278	0	0	0
T10	77715	957	0	0
T11	428630	14	0	0
T12	165594	1165	0	0
T13	220096	10	0	0
T14	0	54	0	0
T15	0	1095	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	512210	0	0
T1	288743	5	0	0
T2	437613	0	0	0
T3	14975	28	0	0
T7	9295	82	0	0
T8	338148	4	0	0
T9	454278	0	0	0
T10	77715	976	0	0
T11	428630	1275	0	0
T12	165594	1192	0	0
T13	220096	10	0	0
T14	0	57	0	0
T15	0	5489	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	199045	0	0
T1	288743	5	0	0
T2	437613	0	0	0
T3	14975	20	0	0
T7	9295	79	0	0
T8	338148	4	0	0
T9	454278	0	0	0
T10	77715	957	0	0
T11	428630	14	0	0
T12	165594	1165	0	0
T13	220096	10	0	0
T14	0	54	0	0
T15	0	1095	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T11
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T7,T10,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	202031	0	0
GntImpliesValid_A	410573884	202031	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	202031	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2705788	0	0
ReadyAndValidImplyGrant_A	410573884	202031	0	0
ReqAndReadyImplyGrant_A	410573884	202031	0	0
ReqImpliesValid_A	410573884	522627	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	202031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202031	0	0
T1	288743	7	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	856	0	0
T11	428630	16	0	0
T12	165594	1288	0	0
T13	220096	8	0	0
T14	0	38	0	0
T15	0	1631	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202031	0	0
T1	288743	7	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	856	0	0
T11	428630	16	0	0
T12	165594	1288	0	0
T13	220096	8	0	0
T14	0	38	0	0
T15	0	1631	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202031	0	0
T1	288743	7	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	856	0	0
T11	428630	16	0	0
T12	165594	1288	0	0
T13	220096	8	0	0
T14	0	38	0	0
T15	0	1631	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2705788	0	0
T1	288743	32	0	0
T2	437613	1	0	0
T3	14975	90	0	0
T7	9295	79	0	0
T8	338148	4241	0	0
T9	454278	1	0	0
T10	77715	839	0	0
T11	428630	3637	0	0
T12	165594	1252	0	0
T13	220096	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202031	0	0
T1	288743	7	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	856	0	0
T11	428630	16	0	0
T12	165594	1288	0	0
T13	220096	8	0	0
T14	0	38	0	0
T15	0	1631	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202031	0	0
T1	288743	7	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	856	0	0
T11	428630	16	0	0
T12	165594	1288	0	0
T13	220096	8	0	0
T14	0	38	0	0
T15	0	1631	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	522627	0	0
T1	288743	7	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	90	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	877	0	0
T11	428630	1776	0	0
T12	165594	1344	0	0
T13	220096	8	0	0
T14	0	40	0	0
T15	0	10107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202031	0	0
T1	288743	7	0	0
T2	437613	0	0	0
T3	14975	14	0	0
T7	9295	84	0	0
T8	338148	11	0	0
T9	454278	0	0	0
T10	77715	856	0	0
T11	428630	16	0	0
T12	165594	1288	0	0
T13	220096	8	0	0
T14	0	38	0	0
T15	0	1631	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	194159	0	0
GntImpliesValid_A	410573884	194159	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	194159	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2712410	0	0
ReadyAndValidImplyGrant_A	410573884	194159	0	0
ReqAndReadyImplyGrant_A	410573884	194159	0	0
ReqImpliesValid_A	410573884	493523	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	194159	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194159	0	0
T1	288743	15	0	0
T2	437613	0	0	0
T3	14975	13	0	0
T7	9295	79	0	0
T8	338148	8	0	0
T9	454278	542	0	0
T10	77715	1459	0	0
T11	428630	10	0	0
T12	165594	1164	0	0
T13	220096	8	0	0
T14	0	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194159	0	0
T1	288743	15	0	0
T2	437613	0	0	0
T3	14975	13	0	0
T7	9295	79	0	0
T8	338148	8	0	0
T9	454278	542	0	0
T10	77715	1459	0	0
T11	428630	10	0	0
T12	165594	1164	0	0
T13	220096	8	0	0
T14	0	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194159	0	0
T1	288743	15	0	0
T2	437613	0	0	0
T3	14975	13	0	0
T7	9295	79	0	0
T8	338148	8	0	0
T9	454278	542	0	0
T10	77715	1459	0	0
T11	428630	10	0	0
T12	165594	1164	0	0
T13	220096	8	0	0
T14	0	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2712410	0	0
T1	288743	40	0	0
T2	437613	1	0	0
T3	14975	129	0	0
T7	9295	77	0	0
T8	338148	2769	0	0
T9	454278	1793	0	0
T10	77715	1205	0	0
T11	428630	3273	0	0
T12	165594	1155	0	0
T13	220096	25	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194159	0	0
T1	288743	15	0	0
T2	437613	0	0	0
T3	14975	13	0	0
T7	9295	79	0	0
T8	338148	8	0	0
T9	454278	542	0	0
T10	77715	1459	0	0
T11	428630	10	0	0
T12	165594	1164	0	0
T13	220096	8	0	0
T14	0	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194159	0	0
T1	288743	15	0	0
T2	437613	0	0	0
T3	14975	13	0	0
T7	9295	79	0	0
T8	338148	8	0	0
T9	454278	542	0	0
T10	77715	1459	0	0
T11	428630	10	0	0
T12	165594	1164	0	0
T13	220096	8	0	0
T14	0	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	493523	0	0
T1	288743	15	0	0
T2	437613	0	0	0
T3	14975	13	0	0
T7	9295	82	0	0
T8	338148	8	0	0
T9	454278	1240	0	0
T10	77715	1717	0	0
T11	428630	10	0	0
T12	165594	1193	0	0
T13	220096	8	0	0
T14	0	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	194159	0	0
T1	288743	15	0	0
T2	437613	0	0	0
T3	14975	13	0	0
T7	9295	79	0	0
T8	338148	8	0	0
T9	454278	542	0	0
T10	77715	1459	0	0
T11	428630	10	0	0
T12	165594	1164	0	0
T13	220096	8	0	0
T14	0	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	202951	0	0
GntImpliesValid_A	410573884	202951	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	202951	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	2757014	0	0
ReadyAndValidImplyGrant_A	410573884	202951	0	0
ReqAndReadyImplyGrant_A	410573884	202951	0	0
ReqImpliesValid_A	410573884	515282	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	0	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	202951	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202951	0	0
T1	288743	10	0	0
T2	437613	0	0	0
T3	14975	16	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	477	0	0
T10	77715	975	0	0
T11	428630	17	0	0
T12	165594	1958	0	0
T13	220096	14	0	0
T14	0	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202951	0	0
T1	288743	10	0	0
T2	437613	0	0	0
T3	14975	16	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	477	0	0
T10	77715	975	0	0
T11	428630	17	0	0
T12	165594	1958	0	0
T13	220096	14	0	0
T14	0	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202951	0	0
T1	288743	10	0	0
T2	437613	0	0	0
T3	14975	16	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	477	0	0
T10	77715	975	0	0
T11	428630	17	0	0
T12	165594	1958	0	0
T13	220096	14	0	0
T14	0	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2757014	0	0
T1	288743	44	0	0
T2	437613	1	0	0
T3	14975	99	0	0
T7	9295	74	0	0
T8	338148	2279	0	0
T9	454278	1581	0	0
T10	77715	955	0	0
T11	428630	4632	0	0
T12	165594	1469	0	0
T13	220096	57	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202951	0	0
T1	288743	10	0	0
T2	437613	0	0	0
T3	14975	16	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	477	0	0
T10	77715	975	0	0
T11	428630	17	0	0
T12	165594	1958	0	0
T13	220096	14	0	0
T14	0	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202951	0	0
T1	288743	10	0	0
T2	437613	0	0	0
T3	14975	16	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	477	0	0
T10	77715	975	0	0
T11	428630	17	0	0
T12	165594	1958	0	0
T13	220096	14	0	0
T14	0	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	515282	0	0
T1	288743	10	0	0
T2	437613	0	0	0
T3	14975	21	0	0
T7	9295	75	0	0
T8	338148	7	0	0
T9	454278	1106	0	0
T10	77715	999	0	0
T11	428630	270	0	0
T12	165594	2466	0	0
T13	220096	17	0	0
T14	0	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	202951	0	0
T1	288743	10	0	0
T2	437613	0	0	0
T3	14975	16	0	0
T7	9295	74	0	0
T8	338148	7	0	0
T9	454278	477	0	0
T10	77715	975	0	0
T11	428630	17	0	0
T12	165594	1958	0	0
T13	220096	14	0	0
T14	0	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	832518	0	0
GntImpliesValid_A	410573884	832518	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	832518	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	10558441	0	0
ReadyAndValidImplyGrant_A	410573884	832518	0	0
ReqAndReadyImplyGrant_A	410573884	832518	0	0
ReqImpliesValid_A	410573884	2168024	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	17945	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	832518	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	832518	0	0
T1	288743	32	0	0
T2	437613	1586	0	0
T3	14975	64	0	0
T7	9295	289	0	0
T8	338148	45	0	0
T9	454278	1022	0	0
T10	77715	3708	0	0
T11	428630	56	0	0
T12	165594	6891	0	0
T13	220096	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	832518	0	0
T1	288743	32	0	0
T2	437613	1586	0	0
T3	14975	64	0	0
T7	9295	289	0	0
T8	338148	45	0	0
T9	454278	1022	0	0
T10	77715	3708	0	0
T11	428630	56	0	0
T12	165594	6891	0	0
T13	220096	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	832518	0	0
T1	288743	32	0	0
T2	437613	1586	0	0
T3	14975	64	0	0
T7	9295	289	0	0
T8	338148	45	0	0
T9	454278	1022	0	0
T10	77715	3708	0	0
T11	428630	56	0	0
T12	165594	6891	0	0
T13	220096	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	10558441	0	0
T1	288743	108	0	0
T2	437613	4577	0	0
T3	14975	437	0	0
T7	9295	1	0	0
T8	338148	16023	0	0
T9	454278	3329	0	0
T10	77715	4	0	0
T11	428630	15525	0	0
T12	165594	20	0	0
T13	220096	218	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	832518	0	0
T1	288743	32	0	0
T2	437613	1586	0	0
T3	14975	64	0	0
T7	9295	289	0	0
T8	338148	45	0	0
T9	454278	1022	0	0
T10	77715	3708	0	0
T11	428630	56	0	0
T12	165594	6891	0	0
T13	220096	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	832518	0	0
T1	288743	32	0	0
T2	437613	1586	0	0
T3	14975	64	0	0
T7	9295	289	0	0
T8	338148	45	0	0
T9	454278	1022	0	0
T10	77715	3708	0	0
T11	428630	56	0	0
T12	165594	6891	0	0
T13	220096	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	2168024	0	0
T1	288743	41	0	0
T2	437613	2765	0	0
T3	14975	105	0	0
T7	9295	289	0	0
T8	338148	2193	0	0
T9	454278	1319	0	0
T10	77715	3708	0	0
T11	428630	699	0	0
T12	165594	6891	0	0
T13	220096	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	17945	0	899
T2	437613	16	0	1
T3	14975	0	0	1
T7	9295	0	0	1
T8	338148	0	0	1
T9	454278	0	0	1
T10	77715	48	0	1
T11	428630	0	0	1
T12	165594	153	0	1
T13	220096	0	0	1
T14	3284	2	0	1
T15	0	73	0	0
T16	0	4	0	0
T17	0	12	0	0
T18	0	1156	0	0
T19	0	1	0	0
T20	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	832518	0	0
T1	288743	32	0	0
T2	437613	1586	0	0
T3	14975	64	0	0
T7	9295	289	0	0
T8	338148	45	0	0
T9	454278	1022	0	0
T10	77715	3708	0	0
T11	428630	56	0	0
T12	165594	6891	0	0
T13	220096	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410573884	410445244	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410573884	823150	0	0
GntImpliesValid_A	410573884	823150	0	0
GrantKnown_A	410573884	410445244	0	0
IdxKnown_A	410573884	410445244	0	0
IndexIsCorrect_A	410573884	823150	0	0
LockArbDecision_A	410573884	0	0	0
NoReadyValidNoGrant_A	410573884	344182904	0	0
ReadyAndValidImplyGrant_A	410573884	823150	0	0
ReqAndReadyImplyGrant_A	410573884	823150	0	0
ReqImpliesValid_A	410573884	12160725	0	0
ReqStaysHighUntilGranted0_M	410573884	0	0	0
RoundRobin_A	410573884	23929	0	899
ValidKnown_A	410573884	410445244	0	0
gen_data_port_assertion.DataFlow_A	410573884	823150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	823150	0	0
T1	288743	22	0	0
T2	437613	859	0	0
T3	14975	62	0	0
T7	9295	336	0	0
T8	338148	33	0	0
T9	454278	979	0	0
T10	77715	3877	0	0
T11	428630	32	0	0
T12	165594	7655	0	0
T13	220096	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	823150	0	0
T1	288743	22	0	0
T2	437613	859	0	0
T3	14975	62	0	0
T7	9295	336	0	0
T8	338148	33	0	0
T9	454278	979	0	0
T10	77715	3877	0	0
T11	428630	32	0	0
T12	165594	7655	0	0
T13	220096	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	823150	0	0
T1	288743	22	0	0
T2	437613	859	0	0
T3	14975	62	0	0
T7	9295	336	0	0
T8	338148	33	0	0
T9	454278	979	0	0
T10	77715	3877	0	0
T11	428630	32	0	0
T12	165594	7655	0	0
T13	220096	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	344182904	0	0
T1	288743	240568	0	0
T2	437613	364366	0	0
T3	14975	13124	0	0
T7	9295	1	0	0
T8	338148	314776	0	0
T9	454278	378234	0	0
T10	77715	1	0	0
T11	428630	416979	0	0
T12	165594	1	0	0
T13	220096	183311	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	823150	0	0
T1	288743	22	0	0
T2	437613	859	0	0
T3	14975	62	0	0
T7	9295	336	0	0
T8	338148	33	0	0
T9	454278	979	0	0
T10	77715	3877	0	0
T11	428630	32	0	0
T12	165594	7655	0	0
T13	220096	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	823150	0	0
T1	288743	22	0	0
T2	437613	859	0	0
T3	14975	62	0	0
T7	9295	336	0	0
T8	338148	33	0	0
T9	454278	979	0	0
T10	77715	3877	0	0
T11	428630	32	0	0
T12	165594	7655	0	0
T13	220096	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	12160725	0	0
T1	288743	111	0	0
T2	437613	3725	0	0
T3	14975	525	0	0
T7	9295	336	0	0
T8	338148	13435	0	0
T9	454278	4309	0	0
T10	77715	3877	0	0
T11	428630	10785	0	0
T12	165594	7655	0	0
T13	220096	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	23929	0	899
T7	9295	7	0	1
T8	338148	0	0	1
T9	454278	0	0	1
T10	77715	42	0	1
T11	428630	0	0	1
T12	165594	606	0	1
T13	220096	0	0	1
T14	3284	5	0	1
T15	511196	80	0	1
T16	9301	10	0	1
T17	0	8	0	0
T18	0	99	0	0
T19	0	2	0	0
T20	0	15	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	410445244	0	0
T1	288743	288675	0	0
T2	437613	437608	0	0
T3	14975	14916	0	0
T7	9295	9226	0	0
T8	338148	338106	0	0
T9	454278	454276	0	0
T10	77715	77485	0	0
T11	428630	428614	0	0
T12	165594	163453	0	0
T13	220096	220088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410573884	823150	0	0
T1	288743	22	0	0
T2	437613	859	0	0
T3	14975	62	0	0
T7	9295	336	0	0
T8	338148	33	0	0
T9	454278	979	0	0
T10	77715	3877	0	0
T11	428630	32	0	0
T12	165594	7655	0	0
T13	220096	34	0	0