Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1746	1			T3	1		T7	1		T17	19
all_values[1]	1686	1			T3	3		T17	29		T26	1
all_values[2]	1586	1			T3	1		T7	2		T17	21
all_values[3]	1657	1			T7	1		T17	27		T23	8
all_values[4]	1696	1			T3	1		T7	2		T17	14
all_values[5]	1648	1			T3	1		T7	1		T17	20
all_values[6]	1641	1			T7	2		T17	9		T26	1
all_values[7]	1685	1			T3	2		T7	1		T17	23
all_values[8]	1691	1			T7	3		T17	15		T23	14
all_values[9]	1642	1			T3	2		T17	14		T26	1
all_values[10]	1709	1			T3	1		T7	1		T17	18
all_values[11]	1673	1			T7	2		T17	21		T23	18
all_values[12]	1621	1			T7	5		T17	11		T23	29
all_values[13]	1572	1			T17	18		T23	13		T24	5
all_values[14]	1655	1			T7	3		T17	18		T23	23
all_values[15]	1681	1			T3	2		T7	1		T17	14
all_values[16]	1684	1			T3	1		T7	1		T17	13
all_values[17]	1655	1			T7	4		T17	19		T26	2
all_values[18]	1639	1			T3	2		T7	1		T17	17
all_values[19]	1662	1			T3	1		T7	3		T17	11
all_values[20]	1649	1			T3	2		T7	1		T17	25
all_values[21]	1635	1			T7	3		T17	22		T23	22
all_values[22]	1686	1			T7	1		T17	19		T23	26
all_values[23]	1652	1			T3	3		T7	2		T17	19
all_values[24]	1608	1			T3	1		T7	3		T17	13
all_values[25]	1601	1			T3	1		T7	1		T17	17
all_values[26]	1697	1			T7	2		T17	15		T26	1
all_values[27]	1717	1			T3	3		T7	4		T17	24
all_values[28]	1635	1			T3	1		T17	22		T26	1
all_values[29]	1632	1			T3	3		T7	1		T17	16
all_values[30]	1756	1			T3	5		T7	4		T17	13
all_values[31]	1622	1			T3	2		T7	1		T17	27
all_values[32]	1718	1			T7	1		T17	17		T26	1
all_values[33]	1718	1			T3	2		T7	2		T17	18
all_values[34]	1691	1			T7	2		T17	16		T23	15
all_values[35]	1698	1			T3	2		T7	2		T17	12
all_values[36]	1707	1			T3	1		T7	1		T17	23
all_values[37]	1682	1			T3	2		T7	3		T17	17
all_values[38]	1594	1			T7	1		T17	21		T26	1
all_values[39]	1676	1			T3	3		T7	2		T17	19
all_values[40]	1690	1			T3	2		T7	1		T17	15
all_values[41]	1644	1			T3	2		T7	5		T17	18
all_values[42]	1697	1			T7	1		T17	21		T23	16
all_values[43]	1688	1			T7	1		T17	22		T26	1
all_values[44]	1689	1			T3	1		T7	1		T17	23
all_values[45]	1686	1			T3	2		T7	2		T17	17
all_values[46]	1678	1			T7	1		T17	14		T23	18
all_values[47]	1753	1			T3	1		T7	2		T17	17
all_values[48]	1644	1			T3	1		T7	2		T17	12
all_values[49]	1686	1			T3	4		T7	2		T17	14
all_values[50]	1732	1			T7	4		T17	18		T26	1
all_values[51]	1632	1			T3	3		T17	16		T23	15
all_values[52]	1676	1			T7	1		T17	26		T23	16
all_values[53]	1656	1			T3	2		T7	3		T17	17
all_values[54]	1669	1			T3	1		T7	2		T17	23
all_values[55]	1690	1			T3	1		T7	3		T17	25
all_values[56]	1628	1			T3	1		T7	3		T17	18
all_values[57]	1628	1			T3	2		T7	3		T17	17
all_values[58]	1698	1			T7	1		T17	25		T26	1
all_values[59]	1700	1			T7	4		T17	21		T23	17
all_values[60]	1698	1			T3	1		T7	2		T17	24
all_values[61]	1608	1			T3	1		T7	4		T17	19
all_values[62]	1672	1			T3	1		T7	3		T17	15
all_values[63]	1680	1			T7	1		T17	25		T23	22