Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1798549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

285476

1

T1

135

T2

9

T3

349

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	705985	1			T1	292		T2	28		T3	775
values[0x0]	671164	1			T1	311		T2	5		T3	886
values[0x1]	706876	1			T1	312		T2	37		T3	828

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1390194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

693831

1

T1

315

T2

21

T3

838

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32293	1			T2	1		T3	20		T8	3
valid_sources[0x01]	32517	1			T3	52		T9	267		T10	38
valid_sources[0x02]	31837	1			T3	37		T7	3		T8	1
valid_sources[0x03]	31497	1			T1	1		T3	43		T9	306
valid_sources[0x04]	32031	1			T1	7		T2	2		T3	34
valid_sources[0x05]	31793	1			T1	2		T3	26		T7	1
valid_sources[0x06]	32426	1			T2	1		T3	27		T7	4
valid_sources[0x07]	33391	1			T1	36		T2	1		T3	22
valid_sources[0x08]	32981	1			T2	1		T3	31		T9	247
valid_sources[0x09]	33361	1			T1	3		T3	42		T7	1
valid_sources[0x0a]	33675	1			T3	45		T7	4		T9	220
valid_sources[0x0b]	31794	1			T3	47		T7	4		T9	259
valid_sources[0x0c]	31877	1			T3	17		T8	2		T9	252
valid_sources[0x0d]	32745	1			T2	1		T3	109		T8	3
valid_sources[0x0e]	32749	1			T1	9		T3	31		T7	1
valid_sources[0x0f]	31454	1			T2	1		T3	26		T9	301
valid_sources[0x10]	31955	1			T1	28		T2	2		T3	16
valid_sources[0x11]	32681	1			T2	3		T3	15		T7	1
valid_sources[0x12]	32519	1			T1	78		T2	1		T3	36
valid_sources[0x13]	33093	1			T3	76		T7	4		T9	281
valid_sources[0x14]	33530	1			T3	47		T7	3		T8	2
valid_sources[0x15]	32935	1			T1	20		T2	4		T3	47
valid_sources[0x16]	32920	1			T1	23		T3	48		T8	1
valid_sources[0x17]	31333	1			T2	1		T3	15		T9	256
valid_sources[0x18]	32783	1			T2	1		T3	37		T9	195
valid_sources[0x19]	31995	1			T2	3		T3	58		T9	247
valid_sources[0x1a]	32712	1			T3	36		T8	1		T9	267
valid_sources[0x1b]	32712	1			T2	1		T3	12		T9	278
valid_sources[0x1c]	34370	1			T1	190		T2	5		T3	29
valid_sources[0x1d]	33720	1			T2	1		T3	50		T8	2
valid_sources[0x1e]	33258	1			T3	55		T8	1		T9	230
valid_sources[0x1f]	32549	1			T2	1		T3	73		T8	3
valid_sources[0x20]	33847	1			T1	57		T2	1		T3	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29906

1

T1

15

T2

2

T3

20

values[0x0]

all_enables

biggest_size

225572

1

T1

110

T2

3

T3

288

values[0x1]

all_enables

biggest_size

29998

1

T1

10

T2

4

T3

41

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1806829	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

294764

1

T1

133

T2

4

T3

352

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	719168	1			T1	340		T2	37		T3	910
values[0x0]	664170	1			T1	350		T2	4		T3	850
values[0x1]	718255	1			T1	352		T2	41		T3	880

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1387928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

713665

1

T1

326

T2

24

T3

851

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33169	1			T1	27		T2	1		T3	41
valid_sources[0x01]	32085	1			T1	42		T2	5		T3	54
valid_sources[0x02]	32414	1			T1	9		T2	1		T3	57
valid_sources[0x03]	32949	1			T1	23		T2	2		T3	29
valid_sources[0x04]	32547	1			T1	6		T2	2		T3	29
valid_sources[0x05]	32645	1			T1	33		T2	1		T3	49
valid_sources[0x06]	32870	1			T1	10		T2	1		T3	37
valid_sources[0x07]	33302	1			T1	14		T3	39		T7	2
valid_sources[0x08]	32225	1			T1	16		T2	1		T3	59
valid_sources[0x09]	33080	1			T1	15		T2	2		T3	41
valid_sources[0x0a]	33493	1			T1	15		T3	51		T8	1
valid_sources[0x0b]	32705	1			T1	24		T2	2		T3	27
valid_sources[0x0c]	32812	1			T1	8		T2	1		T3	25
valid_sources[0x0d]	33268	1			T1	34		T2	3		T3	33
valid_sources[0x0e]	33091	1			T1	20		T2	1		T3	26
valid_sources[0x0f]	32482	1			T1	9		T2	2		T3	31
valid_sources[0x10]	33106	1			T1	4		T3	33		T8	1
valid_sources[0x11]	32438	1			T1	10		T2	1		T3	47
valid_sources[0x12]	32915	1			T1	11		T2	1		T3	36
valid_sources[0x13]	33088	1			T1	14		T2	1		T3	58
valid_sources[0x14]	33939	1			T1	14		T3	29		T8	1
valid_sources[0x15]	33097	1			T1	13		T2	2		T3	34
valid_sources[0x16]	33981	1			T1	19		T3	60		T9	369
valid_sources[0x17]	32017	1			T1	8		T3	38		T7	2
valid_sources[0x18]	33439	1			T1	10		T2	3		T3	47
valid_sources[0x19]	31899	1			T1	12		T2	1		T3	51
valid_sources[0x1a]	32759	1			T1	14		T2	4		T3	54
valid_sources[0x1b]	32928	1			T1	29		T2	1		T3	54
valid_sources[0x1c]	33306	1			T1	15		T2	4		T3	64
valid_sources[0x1d]	33064	1			T1	12		T2	1		T3	38
valid_sources[0x1e]	32724	1			T1	11		T3	41		T7	1
valid_sources[0x1f]	32982	1			T1	9		T3	17		T7	1
valid_sources[0x20]	33375	1			T1	11		T2	3		T3	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31020

1

T1

15

T2

1

T3

38

values[0x0]

all_enables

biggest_size

232947

1

T1

103

T2

2

T3

284

values[0x1]

all_enables

biggest_size

30797

1

T1

15

T2

1

T3

30

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1810284	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

287347

1

T1

120

T2

8

T3

391

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	711583	1			T1	269		T2	38		T3	850
values[0x0]	673369	1			T1	273		T2	4		T3	878
values[0x1]	712679	1			T1	300		T2	32		T3	938

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1398874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

698757

1

T1

273

T2

30

T3

906

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33356	1			T1	10		T3	51		T9	276
valid_sources[0x01]	31874	1			T1	10		T2	2		T3	42
valid_sources[0x02]	33711	1			T1	16		T2	1		T3	52
valid_sources[0x03]	32124	1			T1	16		T2	2		T3	19
valid_sources[0x04]	31981	1			T1	16		T3	41		T7	1
valid_sources[0x05]	34166	1			T1	14		T2	1		T3	46
valid_sources[0x06]	32415	1			T1	16		T2	1		T3	33
valid_sources[0x07]	31777	1			T1	12		T3	2		T8	3
valid_sources[0x08]	32843	1			T1	13		T2	1		T3	66
valid_sources[0x09]	33237	1			T1	17		T2	2		T3	13
valid_sources[0x0a]	32936	1			T1	15		T2	3		T3	44
valid_sources[0x0b]	32628	1			T1	15		T2	1		T3	44
valid_sources[0x0c]	33621	1			T1	11		T3	44		T8	5
valid_sources[0x0d]	32237	1			T1	13		T2	1		T3	54
valid_sources[0x0e]	32763	1			T1	13		T3	53		T8	1
valid_sources[0x0f]	32245	1			T1	16		T3	55		T8	2
valid_sources[0x10]	32729	1			T1	11		T3	50		T8	1
valid_sources[0x11]	31962	1			T1	11		T2	1		T3	1
valid_sources[0x12]	33304	1			T1	15		T2	2		T3	72
valid_sources[0x13]	33177	1			T1	19		T3	32		T8	2
valid_sources[0x14]	33273	1			T1	8		T2	1		T3	89
valid_sources[0x15]	32774	1			T1	14		T2	1		T3	64
valid_sources[0x16]	32436	1			T1	10		T2	2		T3	44
valid_sources[0x17]	31606	1			T1	14		T2	1		T3	56
valid_sources[0x18]	32134	1			T1	10		T2	1		T3	53
valid_sources[0x19]	31871	1			T1	10		T2	1		T3	14
valid_sources[0x1a]	33483	1			T1	17		T3	17		T8	2
valid_sources[0x1b]	32690	1			T1	10		T2	3		T3	53
valid_sources[0x1c]	32911	1			T1	15		T3	88		T7	1
valid_sources[0x1d]	32639	1			T1	7		T2	1		T3	47
valid_sources[0x1e]	33041	1			T1	11		T3	8		T7	2
valid_sources[0x1f]	32843	1			T1	7		T2	1		T9	320
valid_sources[0x20]	32622	1			T1	20		T3	49		T9	216

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30280

1

T1

11

T2

4

T3

33

values[0x0]

all_enables

biggest_size

226882

1

T1

94

T2

1

T3

316

values[0x1]

all_enables

biggest_size

30185

1

T1

15

T2

3

T3

42