Unified Coverage Report :: Module

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8840351	0	0
GntImpliesValid_A	2147483647	8840351	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8840351	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	474905687	0	0
ReadyAndValidImplyGrant_A	2147483647	8840351	0	0
ReqAndReadyImplyGrant_A	2147483647	8840351	0	0
ReqImpliesValid_A	2147483647	36547596	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	59101	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8840351	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	106680	104520
T2	835584	834120
T3	5332752	5332608
T7	700752	699048
T8	160080	159024
T9	11529168	11526768
T10	9464784	9464592
T11	9741120	9740904
T12	2181360	2180208
T13	343488	342360

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	21600	21600
T1	24	24
T2	24	24
T3	24	24
T7	24	24
T8	24	24
T9	24	24
T10	24	24
T11	24	24
T12	24	24
T13	24	24

GntImpliesReady_A

Name	Attempts	Real Successes
Total	2147483647	8840351
T1	106680	2214
T2	835584	2254
T3	5332752	7795
T7	700752	1742
T8	160080	3456
T9	11529168	43261
T10	9464784	7521
T11	9741120	407
T12	2181360	8222
T13	343488	7169

GntImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	8840351
T1	106680	2214
T2	835584	2254
T3	5332752	7795
T7	700752	1742
T8	160080	3456
T9	11529168	43261
T10	9464784	7521
T11	9741120	407
T12	2181360	8222
T13	343488	7169

GrantKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	106680	104520
T2	835584	834120
T3	5332752	5332608
T7	700752	699048
T8	160080	159024
T9	11529168	11526768
T10	9464784	9464592
T11	9741120	9740904
T12	2181360	2180208
T13	343488	342360

IdxKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	106680	104520
T2	835584	834120
T3	5332752	5332608
T7	700752	699048
T8	160080	159024
T9	11529168	11526768
T10	9464784	9464592
T11	9741120	9740904
T12	2181360	2180208
T13	343488	342360

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	2147483647	8840351
T1	106680	2214
T2	835584	2254
T3	5332752	7795
T7	700752	1742
T8	160080	3456
T9	11529168	43261
T10	9464784	7521
T11	9741120	407
T12	2181360	8222
T13	343488	7169

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	2147483647	474905687
T1	106680	1568
T2	835584	45026
T3	5332752	231697
T7	700752	39135
T8	160080	4654
T9	11529168	633161
T10	9464784	3085047
T11	9741120	493789
T12	2181360	139126
T13	343488	10638

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	8840351
T1	106680	2214
T2	835584	2254
T3	5332752	7795
T7	700752	1742
T8	160080	3456
T9	11529168	43261
T10	9464784	7521
T11	9741120	407
T12	2181360	8222
T13	343488	7169

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	8840351
T1	106680	2214
T2	835584	2254
T3	5332752	7795
T7	700752	1742
T8	160080	3456
T9	11529168	43261
T10	9464784	7521
T11	9741120	407
T12	2181360	8222
T13	343488	7169

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	36547596
T1	106680	2368
T2	835584	4823
T3	5332752	13929
T7	700752	4258
T8	160080	4195
T9	11529168	196543
T10	9464784	533983
T11	9741120	26775
T12	2181360	19459
T13	343488	8774

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	2147483647	59101	21600
T1	8890	70	2
T2	69632	0	2
T3	444396	0	2
T7	58396	0	2
T8	13340	5	2
T9	960764	175	2
T10	788732	0	2
T11	811760	0	2
T12	181780	1	2
T13	28624	29	2
T14	0	18	0
T15	0	66	0
T16	0	4	0
T17	0	28	0
T18	0	3	0
T19	0	13	0

ValidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	106680	104520
T2	835584	834120
T3	5332752	5332608
T7	700752	699048
T8	160080	159024
T9	11529168	11526768
T10	9464784	9464592
T11	9741120	9740904
T12	2181360	2180208
T13	343488	342360

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	2147483647	8840351
T1	106680	2214
T2	835584	2254
T3	5332752	7795
T7	700752	1742
T8	160080	3456
T9	11529168	43261
T10	9464784	7521
T11	9741120	407
T12	2181360	8222
T13	343488	7169

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	978605	0	0
GntImpliesValid_A	432248515	978605	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	978605	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	12647816	0	0
ReadyAndValidImplyGrant_A	432248515	978605	0	0
ReqAndReadyImplyGrant_A	432248515	978605	0	0
ReqImpliesValid_A	432248515	2607067	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	978605	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	978605
T1	4445	156
T2	34816	231
T3	222198	879
T7	29198	203
T8	6670	402
T9	480382	4877
T10	394366	762
T11	405880	46
T12	90890	952
T13	14312	774

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	978605
T1	4445	156
T2	34816	231
T3	222198	879
T7	29198	203
T8	6670	402
T9	480382	4877
T10	394366	762
T11	405880	46
T12	90890	952
T13	14312	774

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	978605
T1	4445	156
T2	34816	231
T3	222198	879
T7	29198	203
T8	6670	402
T9	480382	4877
T10	394366	762
T11	405880	46
T12	90890	952
T13	14312	774

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	12647816
T1	4445	131
T2	34816	1659
T3	222198	3844
T7	29198	1414
T8	6670	295
T9	480382	28289
T10	394366	251816
T11	405880	13768
T12	90890	6305
T13	14312	574

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	978605
T1	4445	156
T2	34816	231
T3	222198	879
T7	29198	203
T8	6670	402
T9	480382	4877
T10	394366	762
T11	405880	46
T12	90890	952
T13	14312	774

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	978605
T1	4445	156
T2	34816	231
T3	222198	879
T7	29198	203
T8	6670	402
T9	480382	4877
T10	394366	762
T11	405880	46
T12	90890	952
T13	14312	774

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	2607067
T1	4445	183
T2	34816	318
T3	222198	1164
T7	29198	277
T8	6670	510
T9	480382	19044
T10	394366	32526
T11	405880	284
T12	90890	1692
T13	14312	975

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	978605
T1	4445	156
T2	34816	231
T3	222198	879
T7	29198	203
T8	6670	402
T9	480382	4877
T10	394366	762
T11	405880	46
T12	90890	952
T13	14312	774

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	989734	0	0
GntImpliesValid_A	432248515	989734	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	989734	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	12722274	0	0
ReadyAndValidImplyGrant_A	432248515	989734	0	0
ReqAndReadyImplyGrant_A	432248515	989734	0	0
ReqImpliesValid_A	432248515	2681243	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	989734	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	989734
T1	4445	164
T2	34816	254
T3	222198	877
T7	29198	171
T8	6670	367
T9	480382	5879
T10	394366	801
T11	405880	63
T12	90890	894
T13	14312	843

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	989734
T1	4445	164
T2	34816	254
T3	222198	877
T7	29198	171
T8	6670	367
T9	480382	5879
T10	394366	801
T11	405880	63
T12	90890	894
T13	14312	843

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	989734
T1	4445	164
T2	34816	254
T3	222198	877
T7	29198	171
T8	6670	367
T9	480382	5879
T10	394366	801
T11	405880	63
T12	90890	894
T13	14312	843

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	12722274
T1	4445	137
T2	34816	1829
T3	222198	3632
T7	29198	1315
T8	6670	290
T9	480382	30272
T10	394366	253196
T11	405880	21402
T12	90890	6808
T13	14312	622

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	989734
T1	4445	164
T2	34816	254
T3	222198	877
T7	29198	171
T8	6670	367
T9	480382	5879
T10	394366	801
T11	405880	63
T12	90890	894
T13	14312	843

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	989734
T1	4445	164
T2	34816	254
T3	222198	877
T7	29198	171
T8	6670	367
T9	480382	5879
T10	394366	801
T11	405880	63
T12	90890	894
T13	14312	843

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	2681243
T1	4445	193
T2	34816	393
T3	222198	1163
T7	29198	268
T8	6670	445
T9	480382	27317
T10	394366	30387
T11	405880	1484
T12	90890	1606
T13	14312	1065

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	989734
T1	4445	164
T2	34816	254
T3	222198	877
T7	29198	171
T8	6670	367
T9	480382	5879
T10	394366	801
T11	405880	63
T12	90890	894
T13	14312	843

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	235103	0	0
GntImpliesValid_A	432248515	235103	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	235103	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3137711	0	0
ReadyAndValidImplyGrant_A	432248515	235103	0	0
ReqAndReadyImplyGrant_A	432248515	235103	0	0
ReqImpliesValid_A	432248515	594098	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	235103	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	235103
T1	4445	31
T2	34816	44
T3	222198	198
T7	29198	40
T8	6670	90
T9	480382	2438
T10	394366	222
T11	405880	7
T12	90890	200
T13	14312	207

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	235103
T1	4445	31
T2	34816	44
T3	222198	198
T7	29198	40
T8	6670	90
T9	480382	2438
T10	394366	222
T11	405880	7
T12	90890	200
T13	14312	207

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	235103
T1	4445	31
T2	34816	44
T3	222198	198
T7	29198	40
T8	6670	90
T9	480382	2438
T10	394366	222
T11	405880	7
T12	90890	200
T13	14312	207

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3137711
T1	4445	33
T2	34816	354
T3	222198	922
T7	29198	304
T8	6670	89
T9	480382	9831
T10	394366	76016
T11	405880	2633
T12	90890	1501
T13	14312	195

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	235103
T1	4445	31
T2	34816	44
T3	222198	198
T7	29198	40
T8	6670	90
T9	480382	2438
T10	394366	222
T11	405880	7
T12	90890	200
T13	14312	207

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	235103
T1	4445	31
T2	34816	44
T3	222198	198
T7	29198	40
T8	6670	90
T9	480382	2438
T10	394366	222
T11	405880	7
T12	90890	200
T13	14312	207

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	594098
T1	4445	31
T2	34816	53
T3	222198	239
T7	29198	55
T8	6670	92
T9	480382	15665
T10	394366	4832
T11	405880	141
T12	90890	285
T13	14312	220

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	235103
T1	4445	31
T2	34816	44
T3	222198	198
T7	29198	40
T8	6670	90
T9	480382	2438
T10	394366	222
T11	405880	7
T12	90890	200
T13	14312	207

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	264972	0	0
GntImpliesValid_A	432248515	264972	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	264972	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3179899	0	0
ReadyAndValidImplyGrant_A	432248515	264972	0	0
ReqAndReadyImplyGrant_A	432248515	264972	0	0
ReqImpliesValid_A	432248515	684214	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	264972	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	264972
T1	4445	37
T2	34816	54
T3	222198	213
T7	29198	59
T8	6670	93
T9	480382	945
T10	394366	226
T11	405880	11
T12	90890	231
T13	14312	204

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	264972
T1	4445	37
T2	34816	54
T3	222198	213
T7	29198	59
T8	6670	93
T9	480382	945
T10	394366	226
T11	405880	11
T12	90890	231
T13	14312	204

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	264972
T1	4445	37
T2	34816	54
T3	222198	213
T7	29198	59
T8	6670	93
T9	480382	945
T10	394366	226
T11	405880	11
T12	90890	231
T13	14312	204

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3179899
T1	4445	39
T2	34816	477
T3	222198	899
T7	29198	452
T8	6670	90
T9	480382	5377
T10	394366	72052
T11	405880	2911
T12	90890	1668
T13	14312	197

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	264972
T1	4445	37
T2	34816	54
T3	222198	213
T7	29198	59
T8	6670	93
T9	480382	945
T10	394366	226
T11	405880	11
T12	90890	231
T13	14312	204

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	264972
T1	4445	37
T2	34816	54
T3	222198	213
T7	29198	59
T8	6670	93
T9	480382	945
T10	394366	226
T11	405880	11
T12	90890	231
T13	14312	204

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	684214
T1	4445	37
T2	34816	60
T3	222198	310
T7	29198	91
T8	6670	97
T9	480382	3672
T10	394366	4668
T11	405880	11
T12	90890	335
T13	14312	212

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	264972
T1	4445	37
T2	34816	54
T3	222198	213
T7	29198	59
T8	6670	93
T9	480382	945
T10	394366	226
T11	405880	11
T12	90890	231
T13	14312	204

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	234791	0	0
GntImpliesValid_A	432248515	234791	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	234791	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	5929446	0	0
ReadyAndValidImplyGrant_A	432248515	234791	0	0
ReqAndReadyImplyGrant_A	432248515	234791	0	0
ReqImpliesValid_A	432248515	1201331	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	234791	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	234791
T1	4445	24
T2	34816	67
T3	222198	220
T7	29198	59
T8	6670	123
T9	480382	1371
T10	394366	203
T11	405880	12
T12	90890	218
T13	14312	201

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	234791
T1	4445	24
T2	34816	67
T3	222198	220
T7	29198	59
T8	6670	123
T9	480382	1371
T10	394366	203
T11	405880	12
T12	90890	218
T13	14312	201

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	234791
T1	4445	24
T2	34816	67
T3	222198	220
T7	29198	59
T8	6670	123
T9	480382	1371
T10	394366	203
T11	405880	12
T12	90890	218
T13	14312	201

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	5929446
T1	4445	123
T2	34816	866
T3	222198	6747
T7	29198	3045
T8	6670	554
T9	480382	8547
T10	394366	92494
T11	405880	2223
T12	90890	2708
T13	14312	1159

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	234791
T1	4445	24
T2	34816	67
T3	222198	220
T7	29198	59
T8	6670	123
T9	480382	1371
T10	394366	203
T11	405880	12
T12	90890	218
T13	14312	201

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	234791
T1	4445	24
T2	34816	67
T3	222198	220
T7	29198	59
T8	6670	123
T9	480382	1371
T10	394366	203
T11	405880	12
T12	90890	218
T13	14312	201

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	1201331
T1	4445	30
T2	34816	104
T3	222198	631
T7	29198	542
T8	6670	247
T9	480382	6644
T10	394366	6617
T11	405880	12
T12	90890	423
T13	14312	326

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	234791
T1	4445	24
T2	34816	67
T3	222198	220
T7	29198	59
T8	6670	123
T9	480382	1371
T10	394366	203
T11	405880	12
T12	90890	218
T13	14312	201

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	245596	0	0
GntImpliesValid_A	432248515	245596	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	245596	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	5546055	0	0
ReadyAndValidImplyGrant_A	432248515	245596	0	0
ReqAndReadyImplyGrant_A	432248515	245596	0	0
ReqImpliesValid_A	432248515	1364605	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	245596	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	245596
T1	4445	35
T2	34816	59
T3	222198	200
T7	29198	50
T8	6670	91
T9	480382	1005
T10	394366	205
T11	405880	8
T12	90890	238
T13	14312	213

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	245596
T1	4445	35
T2	34816	59
T3	222198	200
T7	29198	50
T8	6670	91
T9	480382	1005
T10	394366	205
T11	405880	8
T12	90890	238
T13	14312	213

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	245596
T1	4445	35
T2	34816	59
T3	222198	200
T7	29198	50
T8	6670	91
T9	480382	1005
T10	394366	205
T11	405880	8
T12	90890	238
T13	14312	213

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	5546055
T1	4445	159
T2	34816	508
T3	222198	5474
T7	29198	524
T8	6670	613
T9	480382	17500
T10	394366	156012
T11	405880	535
T12	90890	6406
T13	14312	1368

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	245596
T1	4445	35
T2	34816	59
T3	222198	200
T7	29198	50
T8	6670	91
T9	480382	1005
T10	394366	205
T11	405880	8
T12	90890	238
T13	14312	213

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	245596
T1	4445	35
T2	34816	59
T3	222198	200
T7	29198	50
T8	6670	91
T9	480382	1005
T10	394366	205
T11	405880	8
T12	90890	238
T13	14312	213

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	1364605
T1	4445	35
T2	34816	79
T3	222198	605
T7	29198	91
T8	6670	215
T9	480382	20790
T10	394366	11279
T11	405880	59
T12	90890	834
T13	14312	392

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	245596
T1	4445	35
T2	34816	59
T3	222198	200
T7	29198	50
T8	6670	91
T9	480382	1005
T10	394366	205
T11	405880	8
T12	90890	238
T13	14312	213

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	235894	0	0
GntImpliesValid_A	432248515	235894	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	235894	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	6382404	0	0
ReadyAndValidImplyGrant_A	432248515	235894	0	0
ReqAndReadyImplyGrant_A	432248515	235894	0	0
ReqImpliesValid_A	432248515	1276231	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	235894	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	235894
T1	4445	30
T2	34816	51
T3	222198	222
T7	29198	43
T8	6670	104
T9	480382	500
T10	394366	241
T11	405880	11
T12	90890	229
T13	14312	187

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	235894
T1	4445	30
T2	34816	51
T3	222198	222
T7	29198	43
T8	6670	104
T9	480382	500
T10	394366	241
T11	405880	11
T12	90890	229
T13	14312	187

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	235894
T1	4445	30
T2	34816	51
T3	222198	222
T7	29198	43
T8	6670	104
T9	480382	500
T10	394366	241
T11	405880	11
T12	90890	229
T13	14312	187

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	6382404
T1	4445	211
T2	34816	469
T3	222198	4578
T7	29198	609
T8	6670	518
T9	480382	16674
T10	394366	473721
T11	405880	664
T12	90890	2782
T13	14312	1731

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	235894
T1	4445	30
T2	34816	51
T3	222198	222
T7	29198	43
T8	6670	104
T9	480382	500
T10	394366	241
T11	405880	11
T12	90890	229
T13	14312	187

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	235894
T1	4445	30
T2	34816	51
T3	222198	222
T7	29198	43
T8	6670	104
T9	480382	500
T10	394366	241
T11	405880	11
T12	90890	229
T13	14312	187

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	1276231
T1	4445	30
T2	34816	57
T3	222198	522
T7	29198	50
T8	6670	196
T9	480382	1114
T10	394366	89597
T11	405880	11
T12	90890	380
T13	14312	488

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	235894
T1	4445	30
T2	34816	51
T3	222198	222
T7	29198	43
T8	6670	104
T9	480382	500
T10	394366	241
T11	405880	11
T12	90890	229
T13	14312	187

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	245696	0	0
GntImpliesValid_A	432248515	245696	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	245696	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	5998476	0	0
ReadyAndValidImplyGrant_A	432248515	245696	0	0
ReqAndReadyImplyGrant_A	432248515	245696	0	0
ReqImpliesValid_A	432248515	1405981	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	245696	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	245696
T1	4445	32
T2	34816	72
T3	222198	227
T7	29198	36
T8	6670	89
T9	480382	977
T10	394366	206
T11	405880	13
T12	90890	217
T13	14312	190

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	245696
T1	4445	32
T2	34816	72
T3	222198	227
T7	29198	36
T8	6670	89
T9	480382	977
T10	394366	206
T11	405880	13
T12	90890	217
T13	14312	190

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	245696
T1	4445	32
T2	34816	72
T3	222198	227
T7	29198	36
T8	6670	89
T9	480382	977
T10	394366	206
T11	405880	13
T12	90890	217
T13	14312	190

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	5998476
T1	4445	142
T2	34816	684
T3	222198	4968
T7	29198	420
T8	6670	910
T9	480382	11810
T10	394366	80946
T11	405880	2028
T12	90890	5415
T13	14312	2236

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	245696
T1	4445	32
T2	34816	72
T3	222198	227
T7	29198	36
T8	6670	89
T9	480382	977
T10	394366	206
T11	405880	13
T12	90890	217
T13	14312	190

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	245696
T1	4445	32
T2	34816	72
T3	222198	227
T7	29198	36
T8	6670	89
T9	480382	977
T10	394366	206
T11	405880	13
T12	90890	217
T13	14312	190

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	1405981
T1	4445	35
T2	34816	89
T3	222198	723
T7	29198	53
T8	6670	213
T9	480382	3272
T10	394366	4079
T11	405880	13
T12	90890	458
T13	14312	602

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	245696
T1	4445	32
T2	34816	72
T3	222198	227
T7	29198	36
T8	6670	89
T9	480382	977
T10	394366	206
T11	405880	13
T12	90890	217
T13	14312	190

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	248201	0	0
GntImpliesValid_A	432248515	248201	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	248201	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3196060	0	0
ReadyAndValidImplyGrant_A	432248515	248201	0	0
ReqAndReadyImplyGrant_A	432248515	248201	0	0
ReqImpliesValid_A	432248515	604100	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	248201	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	248201
T1	4445	27
T2	34816	67
T3	222198	207
T7	29198	41
T8	6670	105
T9	480382	1522
T10	394366	202
T11	405880	11
T12	90890	247
T13	14312	185

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	248201
T1	4445	27
T2	34816	67
T3	222198	207
T7	29198	41
T8	6670	105
T9	480382	1522
T10	394366	202
T11	405880	11
T12	90890	247
T13	14312	185

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	248201
T1	4445	27
T2	34816	67
T3	222198	207
T7	29198	41
T8	6670	105
T9	480382	1522
T10	394366	202
T11	405880	11
T12	90890	247
T13	14312	185

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3196060
T1	4445	29
T2	34816	487
T3	222198	842
T7	29198	259
T8	6670	96
T9	480382	8860
T10	394366	65502
T11	405880	3709
T12	90890	1796
T13	14312	173

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	248201
T1	4445	27
T2	34816	67
T3	222198	207
T7	29198	41
T8	6670	105
T9	480382	1522
T10	394366	202
T11	405880	11
T12	90890	247
T13	14312	185

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	248201
T1	4445	27
T2	34816	67
T3	222198	207
T7	29198	41
T8	6670	105
T9	480382	1522
T10	394366	202
T11	405880	11
T12	90890	247
T13	14312	185

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	604100
T1	4445	27
T2	34816	108
T3	222198	263
T7	29198	58
T8	6670	115
T9	480382	2894
T10	394366	2520
T11	405880	11
T12	90890	375
T13	14312	198

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	248201
T1	4445	27
T2	34816	67
T3	222198	207
T7	29198	41
T8	6670	105
T9	480382	1522
T10	394366	202
T11	405880	11
T12	90890	247
T13	14312	185

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	248358	0	0
GntImpliesValid_A	432248515	248358	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	248358	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3198807	0	0
ReadyAndValidImplyGrant_A	432248515	248358	0	0
ReqAndReadyImplyGrant_A	432248515	248358	0	0
ReqImpliesValid_A	432248515	625239	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	248358	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	248358
T1	4445	26
T2	34816	67
T3	222198	228
T7	29198	46
T8	6670	102
T9	480382	561
T10	394366	216
T11	405880	6
T12	90890	239
T13	14312	192

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	248358
T1	4445	26
T2	34816	67
T3	222198	228
T7	29198	46
T8	6670	102
T9	480382	561
T10	394366	216
T11	405880	6
T12	90890	239
T13	14312	192

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	248358
T1	4445	26
T2	34816	67
T3	222198	228
T7	29198	46
T8	6670	102
T9	480382	561
T10	394366	216
T11	405880	6
T12	90890	239
T13	14312	192

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3198807
T1	4445	28
T2	34816	449
T3	222198	955
T7	29198	320
T8	6670	95
T9	480382	4209
T10	394366	71195
T11	405880	2502
T12	90890	1702
T13	14312	186

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	248358
T1	4445	26
T2	34816	67
T3	222198	228
T7	29198	46
T8	6670	102
T9	480382	561
T10	394366	216
T11	405880	6
T12	90890	239
T13	14312	192

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	248358
T1	4445	26
T2	34816	67
T3	222198	228
T7	29198	46
T8	6670	102
T9	480382	561
T10	394366	216
T11	405880	6
T12	90890	239
T13	14312	192

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	625239
T1	4445	26
T2	34816	82
T3	222198	270
T7	29198	46
T8	6670	110
T9	480382	648
T10	394366	4417
T11	405880	6
T12	90890	295
T13	14312	199

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	248358
T1	4445	26
T2	34816	67
T3	222198	228
T7	29198	46
T8	6670	102
T9	480382	561
T10	394366	216
T11	405880	6
T12	90890	239
T13	14312	192

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	243352	0	0
GntImpliesValid_A	432248515	243352	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	243352	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3226876	0	0
ReadyAndValidImplyGrant_A	432248515	243352	0	0
ReqAndReadyImplyGrant_A	432248515	243352	0	0
ReqImpliesValid_A	432248515	639741	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	243352	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	243352
T1	4445	32
T2	34816	55
T3	222198	203
T7	29198	40
T8	6670	102
T9	480382	529
T10	394366	245
T11	405880	11
T12	90890	228
T13	14312	209

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	243352
T1	4445	32
T2	34816	55
T3	222198	203
T7	29198	40
T8	6670	102
T9	480382	529
T10	394366	245
T11	405880	11
T12	90890	228
T13	14312	209

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	243352
T1	4445	32
T2	34816	55
T3	222198	203
T7	29198	40
T8	6670	102
T9	480382	529
T10	394366	245
T11	405880	11
T12	90890	228
T13	14312	209

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3226876
T1	4445	33
T2	34816	318
T3	222198	913
T7	29198	249
T8	6670	99
T9	480382	3923
T10	394366	81283
T11	405880	3616
T12	90890	1678
T13	14312	194

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	243352
T1	4445	32
T2	34816	55
T3	222198	203
T7	29198	40
T8	6670	102
T9	480382	529
T10	394366	245
T11	405880	11
T12	90890	228
T13	14312	209

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	243352
T1	4445	32
T2	34816	55
T3	222198	203
T7	29198	40
T8	6670	102
T9	480382	529
T10	394366	245
T11	405880	11
T12	90890	228
T13	14312	209

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	639741
T1	4445	33
T2	34816	66
T3	222198	247
T7	29198	42
T8	6670	106
T9	480382	640
T10	394366	6127
T11	405880	11
T12	90890	324
T13	14312	225

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	243352
T1	4445	32
T2	34816	55
T3	222198	203
T7	29198	40
T8	6670	102
T9	480382	529
T10	394366	245
T11	405880	11
T12	90890	228
T13	14312	209

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	243174	0	0
GntImpliesValid_A	432248515	243174	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	243174	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3160090	0	0
ReadyAndValidImplyGrant_A	432248515	243174	0	0
ReqAndReadyImplyGrant_A	432248515	243174	0	0
ReqImpliesValid_A	432248515	614819	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	243174	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	243174
T1	4445	21
T2	34816	75
T3	222198	233
T7	29198	49
T8	6670	100
T9	480382	1046
T10	394366	204
T11	405880	10
T12	90890	256
T13	14312	217

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	243174
T1	4445	21
T2	34816	75
T3	222198	233
T7	29198	49
T8	6670	100
T9	480382	1046
T10	394366	204
T11	405880	10
T12	90890	256
T13	14312	217

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	243174
T1	4445	21
T2	34816	75
T3	222198	233
T7	29198	49
T8	6670	100
T9	480382	1046
T10	394366	204
T11	405880	10
T12	90890	256
T13	14312	217

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3160090
T1	4445	23
T2	34816	574
T3	222198	1035
T7	29198	399
T8	6670	94
T9	480382	4796
T10	394366	66081
T11	405880	3836
T12	90890	1767
T13	14312	207

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	243174
T1	4445	21
T2	34816	75
T3	222198	233
T7	29198	49
T8	6670	100
T9	480382	1046
T10	394366	204
T11	405880	10
T12	90890	256
T13	14312	217

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	243174
T1	4445	21
T2	34816	75
T3	222198	233
T7	29198	49
T8	6670	100
T9	480382	1046
T10	394366	204
T11	405880	10
T12	90890	256
T13	14312	217

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	614819
T1	4445	21
T2	34816	100
T3	222198	260
T7	29198	63
T8	6670	107
T9	480382	5569
T10	394366	4443
T11	405880	1040
T12	90890	310
T13	14312	228

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	243174
T1	4445	21
T2	34816	75
T3	222198	233
T7	29198	49
T8	6670	100
T9	480382	1046
T10	394366	204
T11	405880	10
T12	90890	256
T13	14312	217

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	258855	0	0
GntImpliesValid_A	432248515	258855	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	258855	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3217492	0	0
ReadyAndValidImplyGrant_A	432248515	258855	0	0
ReqAndReadyImplyGrant_A	432248515	258855	0	0
ReqImpliesValid_A	432248515	673592	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	258855	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	258855
T1	4445	26
T2	34816	61
T3	222198	221
T7	29198	59
T8	6670	91
T9	480382	556
T10	394366	212
T11	405880	15
T12	90890	237
T13	14312	200

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	258855
T1	4445	26
T2	34816	61
T3	222198	221
T7	29198	59
T8	6670	91
T9	480382	556
T10	394366	212
T11	405880	15
T12	90890	237
T13	14312	200

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	258855
T1	4445	26
T2	34816	61
T3	222198	221
T7	29198	59
T8	6670	91
T9	480382	556
T10	394366	212
T11	405880	15
T12	90890	237
T13	14312	200

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3217492
T1	4445	28
T2	34816	483
T3	222198	962
T7	29198	450
T8	6670	86
T9	480382	4109
T10	394366	69595
T11	405880	6175
T12	90890	1832
T13	14312	190

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	258855
T1	4445	26
T2	34816	61
T3	222198	221
T7	29198	59
T8	6670	91
T9	480382	556
T10	394366	212
T11	405880	15
T12	90890	237
T13	14312	200

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	258855
T1	4445	26
T2	34816	61
T3	222198	221
T7	29198	59
T8	6670	91
T9	480382	556
T10	394366	212
T11	405880	15
T12	90890	237
T13	14312	200

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	673592
T1	4445	26
T2	34816	77
T3	222198	257
T7	29198	64
T8	6670	97
T9	480382	661
T10	394366	3959
T11	405880	355
T12	90890	338
T13	14312	211

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	258855
T1	4445	26
T2	34816	61
T3	222198	221
T7	29198	59
T8	6670	91
T9	480382	556
T10	394366	212
T11	405880	15
T12	90890	237
T13	14312	200

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	246340	0	0
GntImpliesValid_A	432248515	246340	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	246340	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3254850	0	0
ReadyAndValidImplyGrant_A	432248515	246340	0	0
ReqAndReadyImplyGrant_A	432248515	246340	0	0
ReqImpliesValid_A	432248515	633095	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	246340	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	246340
T1	4445	26
T2	34816	57
T3	222198	214
T7	29198	46
T8	6670	82
T9	480382	517
T10	394366	212
T11	405880	15
T12	90890	243
T13	14312	204

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	246340
T1	4445	26
T2	34816	57
T3	222198	214
T7	29198	46
T8	6670	82
T9	480382	517
T10	394366	212
T11	405880	15
T12	90890	243
T13	14312	204

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	246340
T1	4445	26
T2	34816	57
T3	222198	214
T7	29198	46
T8	6670	82
T9	480382	517
T10	394366	212
T11	405880	15
T12	90890	243
T13	14312	204

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3254850
T1	4445	28
T2	34816	381
T3	222198	930
T7	29198	337
T8	6670	78
T9	480382	3983
T10	394366	69946
T11	405880	6452
T12	90890	1736
T13	14312	189

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	246340
T1	4445	26
T2	34816	57
T3	222198	214
T7	29198	46
T8	6670	82
T9	480382	517
T10	394366	212
T11	405880	15
T12	90890	243
T13	14312	204

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	246340
T1	4445	26
T2	34816	57
T3	222198	214
T7	29198	46
T8	6670	82
T9	480382	517
T10	394366	212
T11	405880	15
T12	90890	243
T13	14312	204

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	633095
T1	4445	26
T2	34816	79
T3	222198	267
T7	29198	68
T8	6670	87
T9	480382	616
T10	394366	5461
T11	405880	975
T12	90890	334
T13	14312	220

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	246340
T1	4445	26
T2	34816	57
T3	222198	214
T7	29198	46
T8	6670	82
T9	480382	517
T10	394366	212
T11	405880	15
T12	90890	243
T13	14312	204

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	242512	0	0
GntImpliesValid_A	432248515	242512	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	242512	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3182627	0	0
ReadyAndValidImplyGrant_A	432248515	242512	0	0
ReqAndReadyImplyGrant_A	432248515	242512	0	0
ReqImpliesValid_A	432248515	598968	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	242512	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	242512
T1	4445	43
T2	34816	66
T3	222198	223
T7	29198	38
T8	6670	90
T9	480382	531
T10	394366	240
T11	405880	7
T12	90890	219
T13	14312	190

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	242512
T1	4445	43
T2	34816	66
T3	222198	223
T7	29198	38
T8	6670	90
T9	480382	531
T10	394366	240
T11	405880	7
T12	90890	219
T13	14312	190

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	242512
T1	4445	43
T2	34816	66
T3	222198	223
T7	29198	38
T8	6670	90
T9	480382	531
T10	394366	240
T11	405880	7
T12	90890	219
T13	14312	190

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3182627
T1	4445	45
T2	34816	550
T3	222198	1003
T7	29198	290
T8	6670	87
T9	480382	3949
T10	394366	84645
T11	405880	1542
T12	90890	1567
T13	14312	180

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	242512
T1	4445	43
T2	34816	66
T3	222198	223
T7	29198	38
T8	6670	90
T9	480382	531
T10	394366	240
T11	405880	7
T12	90890	219
T13	14312	190

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	242512
T1	4445	43
T2	34816	66
T3	222198	223
T7	29198	38
T8	6670	90
T9	480382	531
T10	394366	240
T11	405880	7
T12	90890	219
T13	14312	190

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	598968
T1	4445	43
T2	34816	85
T3	222198	268
T7	29198	38
T8	6670	94
T9	480382	591
T10	394366	7753
T11	405880	7
T12	90890	270
T13	14312	201

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	242512
T1	4445	43
T2	34816	66
T3	222198	223
T7	29198	38
T8	6670	90
T9	480382	531
T10	394366	240
T11	405880	7
T12	90890	219
T13	14312	190

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	246630	0	0
GntImpliesValid_A	432248515	246630	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	246630	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3276283	0	0
ReadyAndValidImplyGrant_A	432248515	246630	0	0
ReqAndReadyImplyGrant_A	432248515	246630	0	0
ReqImpliesValid_A	432248515	646538	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	246630	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	246630
T1	4445	26
T2	34816	60
T3	222198	191
T7	29198	41
T8	6670	98
T9	480382	1004
T10	394366	225
T11	405880	4
T12	90890	250
T13	14312	173

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	246630
T1	4445	26
T2	34816	60
T3	222198	191
T7	29198	41
T8	6670	98
T9	480382	1004
T10	394366	225
T11	405880	4
T12	90890	250
T13	14312	173

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	246630
T1	4445	26
T2	34816	60
T3	222198	191
T7	29198	41
T8	6670	98
T9	480382	1004
T10	394366	225
T11	405880	4
T12	90890	250
T13	14312	173

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3276283
T1	4445	28
T2	34816	444
T3	222198	800
T7	29198	306
T8	6670	94
T9	480382	7107
T10	394366	70085
T11	405880	1055
T12	90890	1792
T13	14312	162

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	246630
T1	4445	26
T2	34816	60
T3	222198	191
T7	29198	41
T8	6670	98
T9	480382	1004
T10	394366	225
T11	405880	4
T12	90890	250
T13	14312	173

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	246630
T1	4445	26
T2	34816	60
T3	222198	191
T7	29198	41
T8	6670	98
T9	480382	1004
T10	394366	225
T11	405880	4
T12	90890	250
T13	14312	173

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	646538
T1	4445	26
T2	34816	91
T3	222198	228
T7	29198	45
T8	6670	103
T9	480382	2118
T10	394366	5518
T11	405880	4
T12	90890	347
T13	14312	185

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	246630
T1	4445	26
T2	34816	60
T3	222198	191
T7	29198	41
T8	6670	98
T9	480382	1004
T10	394366	225
T11	405880	4
T12	90890	250
T13	14312	173

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	263366	0	0
GntImpliesValid_A	432248515	263366	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	263366	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3271065	0	0
ReadyAndValidImplyGrant_A	432248515	263366	0	0
ReqAndReadyImplyGrant_A	432248515	263366	0	0
ReqImpliesValid_A	432248515	587177	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	263366	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	263366
T1	4445	37
T2	34816	103
T3	222198	203
T7	29198	95
T8	6670	85
T9	480382	1612
T10	394366	210
T11	405880	9
T12	90890	224
T13	14312	169

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	263366
T1	4445	37
T2	34816	103
T3	222198	203
T7	29198	95
T8	6670	85
T9	480382	1612
T10	394366	210
T11	405880	9
T12	90890	224
T13	14312	169

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	263366
T1	4445	37
T2	34816	103
T3	222198	203
T7	29198	95
T8	6670	85
T9	480382	1612
T10	394366	210
T11	405880	9
T12	90890	224
T13	14312	169

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3271065
T1	4445	39
T2	34816	789
T3	222198	876
T7	29198	702
T8	6670	83
T9	480382	6895
T10	394366	67582
T11	405880	3633
T12	90890	1678
T13	14312	161

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	263366
T1	4445	37
T2	34816	103
T3	222198	203
T7	29198	95
T8	6670	85
T9	480382	1612
T10	394366	210
T11	405880	9
T12	90890	224
T13	14312	169

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	263366
T1	4445	37
T2	34816	103
T3	222198	203
T7	29198	95
T8	6670	85
T9	480382	1612
T10	394366	210
T11	405880	9
T12	90890	224
T13	14312	169

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	587177
T1	4445	37
T2	34816	132
T3	222198	273
T7	29198	151
T8	6670	88
T9	480382	4793
T10	394366	3789
T11	405880	77
T12	90890	296
T13	14312	178

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	263366
T1	4445	37
T2	34816	103
T3	222198	203
T7	29198	95
T8	6670	85
T9	480382	1612
T10	394366	210
T11	405880	9
T12	90890	224
T13	14312	169

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	244651	0	0
GntImpliesValid_A	432248515	244651	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	244651	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3239873	0	0
ReadyAndValidImplyGrant_A	432248515	244651	0	0
ReqAndReadyImplyGrant_A	432248515	244651	0	0
ReqImpliesValid_A	432248515	623751	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	244651	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	244651
T1	4445	16
T2	34816	64
T3	222198	233
T7	29198	47
T8	6670	98
T9	480382	1414
T10	394366	266
T11	405880	12
T12	90890	229
T13	14312	209

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	244651
T1	4445	16
T2	34816	64
T3	222198	233
T7	29198	47
T8	6670	98
T9	480382	1414
T10	394366	266
T11	405880	12
T12	90890	229
T13	14312	209

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	244651
T1	4445	16
T2	34816	64
T3	222198	233
T7	29198	47
T8	6670	98
T9	480382	1414
T10	394366	266
T11	405880	12
T12	90890	229
T13	14312	209

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3239873
T1	4445	18
T2	34816	466
T3	222198	952
T7	29198	384
T8	6670	90
T9	480382	7262
T10	394366	82171
T11	405880	3355
T12	90890	1616
T13	14312	196

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	244651
T1	4445	16
T2	34816	64
T3	222198	233
T7	29198	47
T8	6670	98
T9	480382	1414
T10	394366	266
T11	405880	12
T12	90890	229
T13	14312	209

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	244651
T1	4445	16
T2	34816	64
T3	222198	233
T7	29198	47
T8	6670	98
T9	480382	1414
T10	394366	266
T11	405880	12
T12	90890	229
T13	14312	209

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	623751
T1	4445	16
T2	34816	77
T3	222198	290
T7	29198	47
T8	6670	107
T9	480382	3557
T10	394366	7410
T11	405880	175
T12	90890	275
T13	14312	223

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	244651
T1	4445	16
T2	34816	64
T3	222198	233
T7	29198	47
T8	6670	98
T9	480382	1414
T10	394366	266
T11	405880	12
T12	90890	229
T13	14312	209

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	248491	0	0
GntImpliesValid_A	432248515	248491	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	248491	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3198028	0	0
ReadyAndValidImplyGrant_A	432248515	248491	0	0
ReqAndReadyImplyGrant_A	432248515	248491	0	0
ReqImpliesValid_A	432248515	610477	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	248491	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	248491
T1	4445	272
T2	34816	61
T3	222198	223
T7	29198	49
T8	6670	100
T9	480382	1499
T10	394366	207
T11	405880	11
T12	90890	210
T13	14312	187

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	248491
T1	4445	272
T2	34816	61
T3	222198	223
T7	29198	49
T8	6670	100
T9	480382	1499
T10	394366	207
T11	405880	11
T12	90890	210
T13	14312	187

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	248491
T1	4445	272
T2	34816	61
T3	222198	223
T7	29198	49
T8	6670	100
T9	480382	1499
T10	394366	207
T11	405880	11
T12	90890	210
T13	14312	187

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3198028
T1	4445	187
T2	34816	517
T3	222198	944
T7	29198	342
T8	6670	96
T9	480382	7610
T10	394366	64811
T11	405880	3353
T12	90890	1537
T13	14312	181

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	248491
T1	4445	272
T2	34816	61
T3	222198	223
T7	29198	49
T8	6670	100
T9	480382	1499
T10	394366	207
T11	405880	11
T12	90890	210
T13	14312	187

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	248491
T1	4445	272
T2	34816	61
T3	222198	223
T7	29198	49
T8	6670	100
T9	480382	1499
T10	394366	207
T11	405880	11
T12	90890	210
T13	14312	187

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	610477
T1	4445	359
T2	34816	78
T3	222198	278
T7	29198	57
T8	6670	105
T9	480382	7416
T10	394366	4483
T11	405880	357
T12	90890	245
T13	14312	194

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	248491
T1	4445	272
T2	34816	61
T3	222198	223
T7	29198	49
T8	6670	100
T9	480382	1499
T10	394366	207
T11	405880	11
T12	90890	210
T13	14312	187

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	228361	0	0
GntImpliesValid_A	432248515	228361	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	228361	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3183845	0	0
ReadyAndValidImplyGrant_A	432248515	228361	0	0
ReqAndReadyImplyGrant_A	432248515	228361	0	0
ReqImpliesValid_A	432248515	521085	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	228361	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	228361
T1	4445	33
T2	34816	64
T3	222198	203
T7	29198	50
T8	6670	99
T9	480382	1488
T10	394366	196
T11	405880	11
T12	90890	256
T13	14312	186

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	228361
T1	4445	33
T2	34816	64
T3	222198	203
T7	29198	50
T8	6670	99
T9	480382	1488
T10	394366	196
T11	405880	11
T12	90890	256
T13	14312	186

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	228361
T1	4445	33
T2	34816	64
T3	222198	203
T7	29198	50
T8	6670	99
T9	480382	1488
T10	394366	196
T11	405880	11
T12	90890	256
T13	14312	186

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3183845
T1	4445	35
T2	34816	456
T3	222198	866
T7	29198	318
T8	6670	94
T9	480382	7176
T10	394366	68870
T11	405880	4594
T12	90890	1769
T13	14312	184

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	228361
T1	4445	33
T2	34816	64
T3	222198	203
T7	29198	50
T8	6670	99
T9	480382	1488
T10	394366	196
T11	405880	11
T12	90890	256
T13	14312	186

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	228361
T1	4445	33
T2	34816	64
T3	222198	203
T7	29198	50
T8	6670	99
T9	480382	1488
T10	394366	196
T11	405880	11
T12	90890	256
T13	14312	186

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	521085
T1	4445	33
T2	34816	82
T3	222198	239
T7	29198	77
T8	6670	105
T9	480382	3874
T10	394366	5586
T11	405880	11
T12	90890	382
T13	14312	189

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	228361
T1	4445	33
T2	34816	64
T3	222198	203
T7	29198	50
T8	6670	99
T9	480382	1488
T10	394366	196
T11	405880	11
T12	90890	256
T13	14312	186

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	242278	0	0
GntImpliesValid_A	432248515	242278	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	242278	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3189973	0	0
ReadyAndValidImplyGrant_A	432248515	242278	0	0
ReqAndReadyImplyGrant_A	432248515	242278	0	0
ReqImpliesValid_A	432248515	635211	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	242278	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	242278
T1	4445	35
T2	34816	71
T3	222198	177
T7	29198	50
T8	6670	106
T9	480382	1448
T10	394366	235
T11	405880	7
T12	90890	219
T13	14312	196

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	242278
T1	4445	35
T2	34816	71
T3	222198	177
T7	29198	50
T8	6670	106
T9	480382	1448
T10	394366	235
T11	405880	7
T12	90890	219
T13	14312	196

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	242278
T1	4445	35
T2	34816	71
T3	222198	177
T7	29198	50
T8	6670	106
T9	480382	1448
T10	394366	235
T11	405880	7
T12	90890	219
T13	14312	196

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3189973
T1	4445	36
T2	34816	533
T3	222198	781
T7	29198	391
T8	6670	101
T9	480382	6358
T10	394366	75074
T11	405880	1032
T12	90890	1579
T13	14312	191

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	242278
T1	4445	35
T2	34816	71
T3	222198	177
T7	29198	50
T8	6670	106
T9	480382	1448
T10	394366	235
T11	405880	7
T12	90890	219
T13	14312	196

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	242278
T1	4445	35
T2	34816	71
T3	222198	177
T7	29198	50
T8	6670	106
T9	480382	1448
T10	394366	235
T11	405880	7
T12	90890	219
T13	14312	196

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	635211
T1	4445	36
T2	34816	133
T3	222198	203
T7	29198	86
T8	6670	112
T9	480382	8227
T10	394366	4689
T11	405880	7
T12	90890	330
T13	14312	202

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	242278
T1	4445	35
T2	34816	71
T3	222198	177
T7	29198	50
T8	6670	106
T9	480382	1448
T10	394366	235
T11	405880	7
T12	90890	219
T13	14312	196

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	245463	0	0
GntImpliesValid_A	432248515	245463	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	245463	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	3136609	0	0
ReadyAndValidImplyGrant_A	432248515	245463	0	0
ReqAndReadyImplyGrant_A	432248515	245463	0	0
ReqImpliesValid_A	432248515	580298	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	0	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	245463	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	245463
T1	4445	31
T2	34816	54
T3	222198	210
T7	29198	44
T8	6670	104
T9	480382	536
T10	394366	214
T11	405880	8
T12	90890	214
T13	14312	167

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	245463
T1	4445	31
T2	34816	54
T3	222198	210
T7	29198	44
T8	6670	104
T9	480382	536
T10	394366	214
T11	405880	8
T12	90890	214
T13	14312	167

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	245463
T1	4445	31
T2	34816	54
T3	222198	210
T7	29198	44
T8	6670	104
T9	480382	536
T10	394366	214
T11	405880	8
T12	90890	214
T13	14312	167

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	3136609
T1	4445	33
T2	34816	367
T3	222198	940
T7	29198	279
T8	6670	100
T9	480382	4026
T10	394366	67163
T11	405880	2783
T12	90890	1739
T13	14312	160

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	245463
T1	4445	31
T2	34816	54
T3	222198	210
T7	29198	44
T8	6670	104
T9	480382	536
T10	394366	214
T11	405880	8
T12	90890	214
T13	14312	167

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	245463
T1	4445	31
T2	34816	54
T3	222198	210
T7	29198	44
T8	6670	104
T9	480382	536
T10	394366	214
T11	405880	8
T12	90890	214
T13	14312	167

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	580298
T1	4445	31
T2	34816	67
T3	222198	244
T7	29198	60
T8	6670	109
T9	480382	643
T10	394366	3185
T11	405880	146
T12	90890	326
T13	14312	175

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	245463
T1	4445	31
T2	34816	54
T3	222198	210
T7	29198	44
T8	6670	104
T9	480382	536
T10	394366	214
T11	405880	8
T12	90890	214
T13	14312	167

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	987852	0	0
GntImpliesValid_A	432248515	987852	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	987852	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	11858749	0	0
ReadyAndValidImplyGrant_A	432248515	987852	0	0
ReqAndReadyImplyGrant_A	432248515	987852	0	0
ReqImpliesValid_A	432248515	2427053	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	23389	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	987852	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	987852
T1	4445	880
T2	34816	253
T3	222198	916
T7	29198	167
T8	6670	363
T9	480382	5800
T10	394366	804
T11	405880	50
T12	90890	886
T13	14312	817

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	987852
T1	4445	880
T2	34816	253
T3	222198	916
T7	29198	167
T8	6670	363
T9	480382	5800
T10	394366	804
T11	405880	50
T12	90890	886
T13	14312	817

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	987852
T1	4445	880
T2	34816	253
T3	222198	916
T7	29198	167
T8	6670	363
T9	480382	5800
T10	394366	804
T11	405880	50
T12	90890	886
T13	14312	817

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	11858749
T1	4445	2
T2	34816	1595
T3	222198	2956
T7	29198	1053
T8	6670	1
T9	480382	27822
T10	394366	269727
T11	405880	14547
T12	90890	5811
T13	14312	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	987852
T1	4445	880
T2	34816	253
T3	222198	916
T7	29198	167
T8	6670	363
T9	480382	5800
T10	394366	804
T11	405880	50
T12	90890	886
T13	14312	817

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	987852
T1	4445	880
T2	34816	253
T3	222198	916
T7	29198	167
T8	6670	363
T9	480382	5800
T10	394366	804
T11	405880	50
T12	90890	886
T13	14312	817

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	2427053
T1	4445	880
T2	34816	340
T3	222198	1165
T7	29198	231
T8	6670	363
T9	480382	11552
T10	394366	31150
T11	405880	1922
T12	90890	1426
T13	14312	817

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	432248515	23389	900
T1	4445	68	1
T2	34816	0	1
T3	222198	0	1
T7	29198	0	1
T8	6670	2	1
T9	480382	140	1
T10	394366	0	1
T11	405880	0	1
T12	90890	0	1
T13	14312	15	1
T14	0	9	0
T15	0	37	0
T16	0	2	0
T17	0	14	0
T18	0	2	0
T19	0	13	0

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	987852
T1	4445	880
T2	34816	253
T3	222198	916
T7	29198	167
T8	6670	363
T9	480382	5800
T10	394366	804
T11	405880	50
T12	90890	886
T13	14312	817

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432248515	432122964	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432248515	972076	0	0
GntImpliesValid_A	432248515	972076	0	0
GrantKnown_A	432248515	432122964	0	0
IdxKnown_A	432248515	432122964	0	0
IndexIsCorrect_A	432248515	972076	0	0
LockArbDecision_A	432248515	0	0	0
NoReadyValidNoGrant_A	432248515	362570379	0	0
ReadyAndValidImplyGrant_A	432248515	972076	0	0
ReqAndReadyImplyGrant_A	432248515	972076	0	0
ReqImpliesValid_A	432248515	13711682	0	0
ReqStaysHighUntilGranted0_M	432248515	0	0	0
RoundRobin_A	432248515	35712	0	900
ValidKnown_A	432248515	432122964	0	0
gen_data_port_assertion.DataFlow_A	432248515	972076	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	432248515	972076
T1	4445	174
T2	34816	244
T3	222198	874
T7	29198	219
T8	6670	372
T9	480382	5206
T10	394366	767
T11	405880	49
T12	90890	886
T13	14312	849

GntImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	972076
T1	4445	174
T2	34816	244
T3	222198	874
T7	29198	219
T8	6670	372
T9	480382	5206
T10	394366	767
T11	405880	49
T12	90890	886
T13	14312	849

GrantKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IdxKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	432248515	972076
T1	4445	174
T2	34816	244
T3	222198	874
T7	29198	219
T8	6670	372
T9	480382	5206
T10	394366	767
T11	405880	49
T12	90890	886
T13	14312	849

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	432248515	362570379
T1	4445	1
T2	34816	29771
T3	222198	184878
T7	29198	24973
T8	6670	1
T9	480382	396776
T10	394366	355064
T11	405880	385441
T12	90890	75934
T13	14312	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	972076
T1	4445	174
T2	34816	244
T3	222198	874
T7	29198	219
T8	6670	372
T9	480382	5206
T10	394366	767
T11	405880	49
T12	90890	886
T13	14312	849

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	432248515	972076
T1	4445	174
T2	34816	244
T3	222198	874
T7	29198	219
T8	6670	372
T9	480382	5206
T10	394366	767
T11	405880	49
T12	90890	886
T13	14312	849

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	432248515	13711682
T1	4445	174
T2	34816	2073
T3	222198	3820
T7	29198	1698
T8	6670	372
T9	480382	45226
T10	394366	249508
T11	405880	19656
T12	90890	7573
T13	14312	849

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432248515	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	432248515	35712	900
T1	4445	2	1
T2	34816	0	1
T3	222198	0	1
T7	29198	0	1
T8	6670	3	1
T9	480382	35	1
T10	394366	0	1
T11	405880	0	1
T12	90890	1	1
T13	14312	14	1
T14	0	9	0
T15	0	29	0
T16	0	2	0
T17	0	14	0
T18	0	1	0

ValidKnown_A

Name	Attempts	Real Successes
Total	432248515	432122964
T1	4445	4355
T2	34816	34755
T3	222198	222192
T7	29198	29127
T8	6670	6626
T9	480382	480282
T10	394366	394358
T11	405880	405871
T12	90890	90842
T13	14312	14265

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	432248515	972076
T1	4445	174
T2	34816	244
T3	222198	874
T7	29198	219
T8	6670	372
T9	480382	5206
T10	394366	767
T11	405880	49
T12	90890	886
T13	14312	849

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33