Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1459067	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

232669

1

T1

83

T2

19

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	572583	1			T1	189		T2	59		T3	72
values[0x0]	544787	1			T1	171		T2	40		T3	67
values[0x1]	574366	1			T1	194		T2	43		T3	81

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1127916	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

563820

1

T1

198

T2

50

T3

72

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26669	1			T1	5		T2	3		T9	2
valid_sources[0x01]	26543	1			T1	13		T7	13		T9	1
valid_sources[0x02]	26156	1			T1	9		T2	2		T9	4
valid_sources[0x03]	27042	1			T1	6		T2	2		T9	3
valid_sources[0x04]	26748	1			T1	11		T2	3		T3	18
valid_sources[0x05]	26078	1			T1	12		T2	3		T7	39
valid_sources[0x06]	27038	1			T1	10		T9	1		T4	3
valid_sources[0x07]	26081	1			T1	10		T2	3		T3	19
valid_sources[0x08]	26797	1			T1	9		T3	6		T9	3
valid_sources[0x09]	26127	1			T1	9		T2	2		T3	15
valid_sources[0x0a]	26720	1			T1	4		T2	2		T8	16
valid_sources[0x0b]	25861	1			T1	7		T2	5		T7	23
valid_sources[0x0c]	26423	1			T1	13		T2	2		T3	19
valid_sources[0x0d]	26741	1			T1	8		T2	5		T7	13
valid_sources[0x0e]	26516	1			T1	11		T2	6		T9	1
valid_sources[0x0f]	25995	1			T1	8		T2	4		T7	20
valid_sources[0x10]	26547	1			T1	4		T2	6		T9	4
valid_sources[0x11]	26377	1			T1	5		T2	2		T9	2
valid_sources[0x12]	26210	1			T1	7		T2	1		T9	3
valid_sources[0x13]	26439	1			T1	15		T2	2		T7	19
valid_sources[0x14]	26129	1			T1	8		T2	3		T3	6
valid_sources[0x15]	26668	1			T1	6		T2	3		T9	5
valid_sources[0x16]	25794	1			T1	10		T2	4		T3	10
valid_sources[0x17]	27004	1			T1	7		T2	3		T8	54
valid_sources[0x18]	25898	1			T1	7		T2	2		T3	5
valid_sources[0x19]	27248	1			T1	8		T2	3		T9	6
valid_sources[0x1a]	27035	1			T1	11		T2	3		T3	5
valid_sources[0x1b]	27166	1			T1	12		T2	1		T3	9
valid_sources[0x1c]	25639	1			T1	7		T2	4		T9	4
valid_sources[0x1d]	25483	1			T1	9		T9	3		T4	1
valid_sources[0x1e]	26428	1			T1	6		T2	2		T3	10
valid_sources[0x1f]	26226	1			T1	9		T2	1		T4	1
valid_sources[0x20]	26070	1			T1	10		T2	2		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24334

1

T1

9

T2

1

T3

4

values[0x0]

all_enables

biggest_size

183889

1

T1

64

T2

15

T3

20

values[0x1]

all_enables

biggest_size

24446

1

T1

10

T2

3

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1464194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238655

1

T1

76

T2

19

T3

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	582470	1			T1	158		T2	56		T3	66
values[0x0]	536829	1			T1	150		T2	52		T3	79
values[0x1]	583550	1			T1	142		T2	46		T3	93

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1124138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

578711

1

T1

166

T2

45

T3

92

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27007	1			T1	12		T8	3		T9	2
valid_sources[0x01]	27300	1			T1	3		T2	6		T7	16
valid_sources[0x02]	26733	1			T1	8		T8	3		T4	6
valid_sources[0x03]	26823	1			T1	8		T2	1		T8	1
valid_sources[0x04]	27465	1			T1	11		T2	2		T3	8
valid_sources[0x05]	26681	1			T1	8		T2	2		T7	27
valid_sources[0x06]	27033	1			T1	1		T2	2		T9	4
valid_sources[0x07]	26423	1			T1	5		T3	9		T8	5
valid_sources[0x08]	26999	1			T1	6		T2	4		T3	14
valid_sources[0x09]	26250	1			T1	10		T3	10		T7	20
valid_sources[0x0a]	26095	1			T1	3		T8	2		T9	1
valid_sources[0x0b]	27119	1			T1	8		T2	3		T7	34
valid_sources[0x0c]	26347	1			T1	14		T2	6		T3	18
valid_sources[0x0d]	26337	1			T1	3		T2	3		T7	16
valid_sources[0x0e]	26104	1			T1	6		T2	2		T9	3
valid_sources[0x0f]	27068	1			T1	3		T2	3		T7	15
valid_sources[0x10]	27020	1			T1	2		T2	4		T9	2
valid_sources[0x11]	25696	1			T1	1		T8	3		T9	2
valid_sources[0x12]	26490	1			T1	6		T2	2		T8	1
valid_sources[0x13]	26480	1			T1	3		T2	5		T7	8
valid_sources[0x14]	26834	1			T1	4		T2	1		T3	13
valid_sources[0x15]	26888	1			T1	26		T2	2		T9	3
valid_sources[0x16]	25846	1			T1	2		T2	3		T3	19
valid_sources[0x17]	26684	1			T1	1		T2	1		T8	1
valid_sources[0x18]	26615	1			T1	12		T2	2		T3	18
valid_sources[0x19]	26679	1			T1	7		T9	4		T4	5
valid_sources[0x1a]	27024	1			T1	9		T3	18		T7	6
valid_sources[0x1b]	27051	1			T1	4		T3	11		T7	14
valid_sources[0x1c]	25373	1			T1	4		T2	4		T9	2
valid_sources[0x1d]	26138	1			T1	10		T8	3		T9	4
valid_sources[0x1e]	27339	1			T1	16		T2	3		T3	11
valid_sources[0x1f]	26093	1			T1	8		T2	4		T8	4
valid_sources[0x20]	26585	1			T1	10		T2	4		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24985

1

T1

9

T2

4

T3

4

values[0x0]

all_enables

biggest_size

188163

1

T1

62

T2

13

T3

32

values[0x1]

all_enables

biggest_size

25507

1

T1

5

T2

2

T3

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1470109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

233798

1

T1

48

T2

14

T3

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	578267	1			T1	168		T2	30		T3	76
values[0x0]	548588	1			T1	130		T2	31		T3	90
values[0x1]	577052	1			T1	165		T2	41		T3	86

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1136747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

567160

1

T1

133

T2

37

T3

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27297	1			T1	8		T4	4		T11	2
valid_sources[0x01]	26875	1			T1	6		T7	16		T8	1
valid_sources[0x02]	26557	1			T1	4		T9	2		T11	4
valid_sources[0x03]	26892	1			T1	6		T8	2		T9	6
valid_sources[0x04]	26344	1			T1	8		T3	18		T4	1
valid_sources[0x05]	26718	1			T1	7		T7	49		T4	4
valid_sources[0x06]	27323	1			T1	4		T2	6		T8	4
valid_sources[0x07]	26694	1			T1	8		T3	16		T8	2
valid_sources[0x08]	27336	1			T1	4		T2	4		T3	17
valid_sources[0x09]	27018	1			T1	5		T3	15		T7	6
valid_sources[0x0a]	26932	1			T1	4		T2	2		T4	2
valid_sources[0x0b]	27252	1			T1	8		T7	22		T8	3
valid_sources[0x0c]	27174	1			T1	5		T2	5		T3	17
valid_sources[0x0d]	26889	1			T1	4		T2	5		T7	15
valid_sources[0x0e]	27235	1			T1	7		T2	4		T8	1
valid_sources[0x0f]	26890	1			T1	9		T2	12		T7	7
valid_sources[0x10]	26761	1			T1	4		T4	3		T10	2
valid_sources[0x11]	26524	1			T1	6		T2	2		T8	3
valid_sources[0x12]	27161	1			T1	9		T8	7		T9	2
valid_sources[0x13]	25894	1			T1	9		T7	18		T8	1
valid_sources[0x14]	27056	1			T1	5		T3	19		T7	14
valid_sources[0x15]	26320	1			T1	5		T8	2		T4	11
valid_sources[0x16]	26518	1			T1	7		T3	7		T9	2
valid_sources[0x17]	26847	1			T1	7		T2	1		T8	3
valid_sources[0x18]	25223	1			T1	9		T3	11		T8	5
valid_sources[0x19]	26159	1			T1	7		T9	4		T4	6
valid_sources[0x1a]	25932	1			T1	9		T3	20		T7	6
valid_sources[0x1b]	27154	1			T1	8		T3	6		T7	12
valid_sources[0x1c]	26145	1			T1	6		T4	2		T11	5
valid_sources[0x1d]	26331	1			T1	9		T2	5		T8	6
valid_sources[0x1e]	27387	1			T1	9		T3	19		T8	4
valid_sources[0x1f]	25970	1			T1	5		T2	1		T10	4
valid_sources[0x20]	25447	1			T1	6		T8	2		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24757

1

T1

4

T7

3

T8

2

values[0x0]

all_enables

biggest_size

184854

1

T1

37

T2

11

T3

30

values[0x1]

all_enables

biggest_size

24187

1

T1

7

T2

3

T3

7