Line Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_async ( parameter Width=107,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Cond Coverage for Module :
prim_fifo_async ( parameter Width=64,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_async
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4105090 |
4104963 |
0 |
0 |
T2 |
3302395 |
3302027 |
0 |
0 |
T3 |
87065 |
86518 |
0 |
0 |
T4 |
16048 |
15609 |
0 |
0 |
T7 |
36362 |
36104 |
0 |
0 |
T8 |
3311357 |
3310914 |
0 |
0 |
T9 |
2883645 |
2883572 |
0 |
0 |
T10 |
1705240 |
1704879 |
0 |
0 |
T11 |
357900 |
357233 |
0 |
0 |
T12 |
2405897 |
2405847 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4105090 |
4104963 |
0 |
0 |
T2 |
3302395 |
3302027 |
0 |
0 |
T3 |
87065 |
86518 |
0 |
0 |
T4 |
16048 |
15609 |
0 |
0 |
T7 |
36362 |
36104 |
0 |
0 |
T8 |
3311357 |
3310914 |
0 |
0 |
T9 |
2883645 |
2883572 |
0 |
0 |
T10 |
1705240 |
1704879 |
0 |
0 |
T11 |
357900 |
357233 |
0 |
0 |
T12 |
2405897 |
2405847 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7200 |
7200 |
0 |
0 |
T1 |
8 |
8 |
0 |
0 |
T2 |
8 |
8 |
0 |
0 |
T3 |
8 |
8 |
0 |
0 |
T4 |
8 |
8 |
0 |
0 |
T7 |
8 |
8 |
0 |
0 |
T8 |
8 |
8 |
0 |
0 |
T9 |
8 |
8 |
0 |
0 |
T10 |
8 |
8 |
0 |
0 |
T11 |
8 |
8 |
0 |
0 |
T12 |
8 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T8,T9 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_35.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565878398 |
565758963 |
0 |
0 |
T1 |
434394 |
434380 |
0 |
0 |
T2 |
87830 |
87819 |
0 |
0 |
T3 |
8912 |
8856 |
0 |
0 |
T4 |
1274 |
1240 |
0 |
0 |
T7 |
4959 |
4924 |
0 |
0 |
T8 |
202610 |
202583 |
0 |
0 |
T9 |
279831 |
279824 |
0 |
0 |
T10 |
221052 |
221005 |
0 |
0 |
T11 |
65403 |
65282 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_37.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
507389543 |
507268910 |
0 |
0 |
T1 |
152039 |
152034 |
0 |
0 |
T2 |
588473 |
588408 |
0 |
0 |
T3 |
3976 |
3950 |
0 |
0 |
T4 |
1247 |
1212 |
0 |
0 |
T7 |
7247 |
7197 |
0 |
0 |
T8 |
392558 |
392505 |
0 |
0 |
T9 |
253311 |
253304 |
0 |
0 |
T10 |
213156 |
213111 |
0 |
0 |
T11 |
36335 |
36267 |
0 |
0 |
T12 |
128017 |
128015 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_39.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
568558050 |
568437150 |
0 |
0 |
T1 |
181650 |
181644 |
0 |
0 |
T2 |
764134 |
764049 |
0 |
0 |
T3 |
7952 |
7902 |
0 |
0 |
T4 |
2605 |
2534 |
0 |
0 |
T7 |
3306 |
3282 |
0 |
0 |
T8 |
607812 |
607730 |
0 |
0 |
T9 |
256264 |
256258 |
0 |
0 |
T10 |
186838 |
186799 |
0 |
0 |
T11 |
70851 |
70720 |
0 |
0 |
T12 |
335494 |
335487 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_41.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
583185378 |
583065940 |
0 |
0 |
T1 |
572611 |
572593 |
0 |
0 |
T2 |
386454 |
386411 |
0 |
0 |
T3 |
12477 |
12398 |
0 |
0 |
T4 |
1718 |
1671 |
0 |
0 |
T7 |
12206 |
12121 |
0 |
0 |
T8 |
360897 |
360848 |
0 |
0 |
T9 |
209123 |
209118 |
0 |
0 |
T10 |
157894 |
157860 |
0 |
0 |
T11 |
18167 |
18132 |
0 |
0 |
T12 |
286931 |
286925 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_35.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
565878398 |
565758963 |
0 |
0 |
T1 |
434394 |
434380 |
0 |
0 |
T2 |
87830 |
87819 |
0 |
0 |
T3 |
8912 |
8856 |
0 |
0 |
T4 |
1274 |
1240 |
0 |
0 |
T7 |
4959 |
4924 |
0 |
0 |
T8 |
202610 |
202583 |
0 |
0 |
T9 |
279831 |
279824 |
0 |
0 |
T10 |
221052 |
221005 |
0 |
0 |
T11 |
65403 |
65282 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_37.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
507389543 |
507268910 |
0 |
0 |
T1 |
152039 |
152034 |
0 |
0 |
T2 |
588473 |
588408 |
0 |
0 |
T3 |
3976 |
3950 |
0 |
0 |
T4 |
1247 |
1212 |
0 |
0 |
T7 |
7247 |
7197 |
0 |
0 |
T8 |
392558 |
392505 |
0 |
0 |
T9 |
253311 |
253304 |
0 |
0 |
T10 |
213156 |
213111 |
0 |
0 |
T11 |
36335 |
36267 |
0 |
0 |
T12 |
128017 |
128015 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_39.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
568558050 |
568437150 |
0 |
0 |
T1 |
181650 |
181644 |
0 |
0 |
T2 |
764134 |
764049 |
0 |
0 |
T3 |
7952 |
7902 |
0 |
0 |
T4 |
2605 |
2534 |
0 |
0 |
T7 |
3306 |
3282 |
0 |
0 |
T8 |
607812 |
607730 |
0 |
0 |
T9 |
256264 |
256258 |
0 |
0 |
T10 |
186838 |
186799 |
0 |
0 |
T11 |
70851 |
70720 |
0 |
0 |
T12 |
335494 |
335487 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T7 |
1 | 1 | Covered | T2,T3,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_41.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
583185378 |
583065940 |
0 |
0 |
T1 |
572611 |
572593 |
0 |
0 |
T2 |
386454 |
386411 |
0 |
0 |
T3 |
12477 |
12398 |
0 |
0 |
T4 |
1718 |
1671 |
0 |
0 |
T7 |
12206 |
12121 |
0 |
0 |
T8 |
360897 |
360848 |
0 |
0 |
T9 |
209123 |
209118 |
0 |
0 |
T10 |
157894 |
157860 |
0 |
0 |
T11 |
18167 |
18132 |
0 |
0 |
T12 |
286931 |
286925 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
400253245 |
400133658 |
0 |
0 |
T1 |
691099 |
691078 |
0 |
0 |
T2 |
368876 |
368835 |
0 |
0 |
T3 |
13437 |
13353 |
0 |
0 |
T4 |
2301 |
2238 |
0 |
0 |
T7 |
2161 |
2145 |
0 |
0 |
T8 |
436870 |
436812 |
0 |
0 |
T9 |
471279 |
471267 |
0 |
0 |
T10 |
231575 |
231526 |
0 |
0 |
T11 |
41786 |
41708 |
0 |
0 |
T12 |
331091 |
331084 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |