Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7350777	0	0
GntImpliesValid_A	2147483647	7350777	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7350777	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	440482025	0	0
ReadyAndValidImplyGrant_A	2147483647	7350777	0	0
ReqAndReadyImplyGrant_A	2147483647	7350777	0	0
ReqImpliesValid_A	2147483647	33281707	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	36412	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7350777	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16586376	16585896	0	0
T2	8853024	8852064	0	0
T3	322488	320496	0	0
T4	55224	53736	0	0
T7	51864	51504	0	0
T8	10484880	10483512	0	0
T9	11310696	11310432	0	0
T10	5557800	5556648	0	0
T11	1002864	1001040	0	0
T12	7946184	7946016	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7350777	0	0
T1	3455495	1467	0	0
T2	8853024	398	0	0
T3	322488	707	0	0
T4	55224	436	0	0
T7	51864	749	0	0
T8	10484880	436	0	0
T9	11310696	444	0	0
T10	5557800	357	0	0
T11	1002864	16119	0	0
T12	7946184	7258	0	0
T13	2342947	3406	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7350777	0	0
T1	3455495	1467	0	0
T2	8853024	398	0	0
T3	322488	707	0	0
T4	55224	436	0	0
T7	51864	749	0	0
T8	10484880	436	0	0
T9	11310696	444	0	0
T10	5557800	357	0	0
T11	1002864	16119	0	0
T12	7946184	7258	0	0
T13	2342947	3406	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16586376	16585896	0	0
T2	8853024	8852064	0	0
T3	322488	320496	0	0
T4	55224	53736	0	0
T7	51864	51504	0	0
T8	10484880	10483512	0	0
T9	11310696	11310432	0	0
T10	5557800	5556648	0	0
T11	1002864	1001040	0	0
T12	7946184	7946016	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16586376	16585896	0	0
T2	8853024	8852064	0	0
T3	322488	320496	0	0
T4	55224	53736	0	0
T7	51864	51504	0	0
T8	10484880	10483512	0	0
T9	11310696	11310432	0	0
T10	5557800	5556648	0	0
T11	1002864	1001040	0	0
T12	7946184	7946016	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7350777	0	0
T1	3455495	1467	0	0
T2	8853024	398	0	0
T3	322488	707	0	0
T4	55224	436	0	0
T7	51864	749	0	0
T8	10484880	436	0	0
T9	11310696	444	0	0
T10	5557800	357	0	0
T11	1002864	16119	0	0
T12	7946184	7258	0	0
T13	2342947	3406	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	440482025	0	0
T1	13821980	580098	0	0
T2	8853024	473561	0	0
T3	322488	16816	0	0
T4	55224	658	0	0
T7	51864	878	0	0
T8	10484880	543888	0	0
T9	11310696	572044	0	0
T10	5557800	194170	0	0
T11	1002864	21065	0	0
T12	7946184	2495962	0	0
T13	493252	16970	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7350777	0	0
T1	3455495	1467	0	0
T2	8853024	398	0	0
T3	322488	707	0	0
T4	55224	436	0	0
T7	51864	749	0	0
T8	10484880	436	0	0
T9	11310696	444	0	0
T10	5557800	357	0	0
T11	1002864	16119	0	0
T12	7946184	7258	0	0
T13	2342947	3406	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7350777	0	0
T1	3455495	1467	0	0
T2	8853024	398	0	0
T3	322488	707	0	0
T4	55224	436	0	0
T7	51864	749	0	0
T8	10484880	436	0	0
T9	11310696	444	0	0
T10	5557800	357	0	0
T11	1002864	16119	0	0
T12	7946184	7258	0	0
T13	2342947	3406	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33281707	0	0
T1	3455495	3384	0	0
T2	8853024	20255	0	0
T3	322488	1506	0	0
T4	55224	482	0	0
T7	51864	760	0	0
T8	10484880	21394	0	0
T9	11310696	25652	0	0
T10	5557800	567	0	0
T11	1002864	17189	0	0
T12	7946184	437828	0	0
T13	2342947	3695	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36412	0	21600
T1	691099	11	0	1
T2	368876	0	0	1
T3	13437	0	0	1
T4	4602	0	0	2
T7	4322	3	0	2
T8	873740	0	0	2
T9	942558	0	0	2
T10	463150	0	0	2
T11	83572	49	0	2
T12	662182	0	0	2
T13	123313	1	0	1
T14	28343	14	0	1
T15	0	24	0	0
T16	0	16	0	0
T17	0	9	0	0
T18	0	14	0	0
T19	0	13	0	0
T20	0	1	0	0
T21	0	13	0	0
T22	0	148	0	0
T23	0	7	0	0
T24	1797	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16586376	16585896	0	0
T2	8853024	8852064	0	0
T3	322488	320496	0	0
T4	55224	53736	0	0
T7	51864	51504	0	0
T8	10484880	10483512	0	0
T9	11310696	11310432	0	0
T10	5557800	5556648	0	0
T11	1002864	1001040	0	0
T12	7946184	7946016	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7350777	0	0
T1	3455495	1467	0	0
T2	8853024	398	0	0
T3	322488	707	0	0
T4	55224	436	0	0
T7	51864	749	0	0
T8	10484880	436	0	0
T9	11310696	444	0	0
T10	5557800	357	0	0
T11	1002864	16119	0	0
T12	7946184	7258	0	0
T13	2342947	3406	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	824562	0	0
GntImpliesValid_A	400253245	824562	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	824562	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	12114277	0	0
ReadyAndValidImplyGrant_A	400253245	824562	0	0
ReqAndReadyImplyGrant_A	400253245	824562	0	0
ReqImpliesValid_A	400253245	2478284	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	824562	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	824562	0	0
T1	691099	47	0	0
T2	368876	51	0	0
T3	13437	62	0	0
T4	2301	40	0	0
T7	2161	61	0	0
T8	436870	43	0	0
T9	471279	61	0	0
T10	231575	39	0	0
T11	41786	1778	0	0
T12	331091	816	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	824562	0	0
T1	691099	47	0	0
T2	368876	51	0	0
T3	13437	62	0	0
T4	2301	40	0	0
T7	2161	61	0	0
T8	436870	43	0	0
T9	471279	61	0	0
T10	231575	39	0	0
T11	41786	1778	0	0
T12	331091	816	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	824562	0	0
T1	691099	47	0	0
T2	368876	51	0	0
T3	13437	62	0	0
T4	2301	40	0	0
T7	2161	61	0	0
T8	436870	43	0	0
T9	471279	61	0	0
T10	231575	39	0	0
T11	41786	1778	0	0
T12	331091	816	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	12114277	0	0
T1	691099	176	0	0
T2	368876	15900	0	0
T3	13437	448	0	0
T4	2301	35	0	0
T7	2161	61	0	0
T8	436870	13450	0	0
T9	471279	20531	0	0
T10	231575	172	0	0
T11	41786	1618	0	0
T12	331091	245778	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	824562	0	0
T1	691099	47	0	0
T2	368876	51	0	0
T3	13437	62	0	0
T4	2301	40	0	0
T7	2161	61	0	0
T8	436870	43	0	0
T9	471279	61	0	0
T10	231575	39	0	0
T11	41786	1778	0	0
T12	331091	816	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	824562	0	0
T1	691099	47	0	0
T2	368876	51	0	0
T3	13437	62	0	0
T4	2301	40	0	0
T7	2161	61	0	0
T8	436870	43	0	0
T9	471279	61	0	0
T10	231575	39	0	0
T11	41786	1778	0	0
T12	331091	816	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2478284	0	0
T1	691099	48	0	0
T2	368876	2003	0	0
T3	13437	62	0	0
T4	2301	46	0	0
T7	2161	62	0	0
T8	436870	794	0	0
T9	471279	1401	0	0
T10	231575	44	0	0
T11	41786	1940	0	0
T12	331091	25492	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	824562	0	0
T1	691099	47	0	0
T2	368876	51	0	0
T3	13437	62	0	0
T4	2301	40	0	0
T7	2161	61	0	0
T8	436870	43	0	0
T9	471279	61	0	0
T10	231575	39	0	0
T11	41786	1778	0	0
T12	331091	816	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	829108	0	0
GntImpliesValid_A	400253245	829108	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	829108	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	11993887	0	0
ReadyAndValidImplyGrant_A	400253245	829108	0	0
ReqAndReadyImplyGrant_A	400253245	829108	0	0
ReqImpliesValid_A	400253245	2404345	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	829108	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	829108	0	0
T1	691099	53	0	0
T2	368876	46	0	0
T3	13437	65	0	0
T4	2301	51	0	0
T7	2161	89	0	0
T8	436870	46	0	0
T9	471279	55	0	0
T10	231575	50	0	0
T11	41786	1779	0	0
T12	331091	850	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	829108	0	0
T1	691099	53	0	0
T2	368876	46	0	0
T3	13437	65	0	0
T4	2301	51	0	0
T7	2161	89	0	0
T8	436870	46	0	0
T9	471279	55	0	0
T10	231575	50	0	0
T11	41786	1779	0	0
T12	331091	850	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	829108	0	0
T1	691099	53	0	0
T2	368876	46	0	0
T3	13437	65	0	0
T4	2301	51	0	0
T7	2161	89	0	0
T8	436870	46	0	0
T9	471279	55	0	0
T10	231575	50	0	0
T11	41786	1779	0	0
T12	331091	850	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	11993887	0	0
T1	691099	196	0	0
T2	368876	15883	0	0
T3	13437	525	0	0
T4	2301	42	0	0
T7	2161	88	0	0
T8	436870	15374	0	0
T9	471279	18484	0	0
T10	231575	172	0	0
T11	41786	1613	0	0
T12	331091	270518	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	829108	0	0
T1	691099	53	0	0
T2	368876	46	0	0
T3	13437	65	0	0
T4	2301	51	0	0
T7	2161	89	0	0
T8	436870	46	0	0
T9	471279	55	0	0
T10	231575	50	0	0
T11	41786	1779	0	0
T12	331091	850	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	829108	0	0
T1	691099	53	0	0
T2	368876	46	0	0
T3	13437	65	0	0
T4	2301	51	0	0
T7	2161	89	0	0
T8	436870	46	0	0
T9	471279	55	0	0
T10	231575	50	0	0
T11	41786	1779	0	0
T12	331091	850	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2404345	0	0
T1	691099	81	0	0
T2	368876	316	0	0
T3	13437	68	0	0
T4	2301	61	0	0
T7	2161	91	0	0
T8	436870	1934	0	0
T9	471279	1224	0	0
T10	231575	77	0	0
T11	41786	1947	0	0
T12	331091	29867	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	829108	0	0
T1	691099	53	0	0
T2	368876	46	0	0
T3	13437	65	0	0
T4	2301	51	0	0
T7	2161	89	0	0
T8	436870	46	0	0
T9	471279	55	0	0
T10	231575	50	0	0
T11	41786	1779	0	0
T12	331091	850	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T24
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T11,T12,T24

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T4,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	201218	0	0
GntImpliesValid_A	400253245	201218	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	201218	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3025632	0	0
ReadyAndValidImplyGrant_A	400253245	201218	0	0
ReqAndReadyImplyGrant_A	400253245	201218	0	0
ReqImpliesValid_A	400253245	527802	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	201218	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201218	0	0
T2	368876	15	0	0
T3	13437	17	0	0
T4	2301	13	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	2	0	0
T10	231575	5	0	0
T11	41786	411	0	0
T12	331091	195	0	0
T13	123313	206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201218	0	0
T2	368876	15	0	0
T3	13437	17	0	0
T4	2301	13	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	2	0	0
T10	231575	5	0	0
T11	41786	411	0	0
T12	331091	195	0	0
T13	123313	206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201218	0	0
T2	368876	15	0	0
T3	13437	17	0	0
T4	2301	13	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	2	0	0
T10	231575	5	0	0
T11	41786	411	0	0
T12	331091	195	0	0
T13	123313	206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3025632	0	0
T1	691099	1	0	0
T2	368876	6066	0	0
T3	13437	133	0	0
T4	2301	14	0	0
T7	2161	24	0	0
T8	436870	5566	0	0
T9	471279	401	0	0
T10	231575	27	0	0
T11	41786	404	0	0
T12	331091	63630	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201218	0	0
T2	368876	15	0	0
T3	13437	17	0	0
T4	2301	13	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	2	0	0
T10	231575	5	0	0
T11	41786	411	0	0
T12	331091	195	0	0
T13	123313	206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201218	0	0
T2	368876	15	0	0
T3	13437	17	0	0
T4	2301	13	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	2	0	0
T10	231575	5	0	0
T11	41786	411	0	0
T12	331091	195	0	0
T13	123313	206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	527802	0	0
T2	368876	15	0	0
T3	13437	17	0	0
T4	2301	13	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	2	0	0
T10	231575	5	0	0
T11	41786	420	0	0
T12	331091	2562	0	0
T13	123313	206	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201218	0	0
T2	368876	15	0	0
T3	13437	17	0	0
T4	2301	13	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	2	0	0
T10	231575	5	0	0
T11	41786	411	0	0
T12	331091	195	0	0
T13	123313	206	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T8,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	207391	0	0
GntImpliesValid_A	400253245	207391	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	207391	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3030768	0	0
ReadyAndValidImplyGrant_A	400253245	207391	0	0
ReqAndReadyImplyGrant_A	400253245	207391	0	0
ReqImpliesValid_A	400253245	548084	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	207391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207391	0	0
T2	368876	5	0	0
T3	13437	19	0	0
T4	2301	13	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	16	0	0
T11	41786	457	0	0
T12	331091	185	0	0
T13	123313	152	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207391	0	0
T2	368876	5	0	0
T3	13437	19	0	0
T4	2301	13	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	16	0	0
T11	41786	457	0	0
T12	331091	185	0	0
T13	123313	152	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207391	0	0
T2	368876	5	0	0
T3	13437	19	0	0
T4	2301	13	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	16	0	0
T11	41786	457	0	0
T12	331091	185	0	0
T13	123313	152	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3030768	0	0
T1	691099	1	0	0
T2	368876	2244	0	0
T3	13437	121	0	0
T4	2301	14	0	0
T7	2161	23	0	0
T8	436870	4562	0	0
T9	471279	4687	0	0
T10	231575	66	0	0
T11	41786	449	0	0
T12	331091	54189	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207391	0	0
T2	368876	5	0	0
T3	13437	19	0	0
T4	2301	13	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	16	0	0
T11	41786	457	0	0
T12	331091	185	0	0
T13	123313	152	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207391	0	0
T2	368876	5	0	0
T3	13437	19	0	0
T4	2301	13	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	16	0	0
T11	41786	457	0	0
T12	331091	185	0	0
T13	123313	152	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	548084	0	0
T2	368876	5	0	0
T3	13437	19	0	0
T4	2301	13	0	0
T7	2161	22	0	0
T8	436870	472	0	0
T9	471279	13	0	0
T10	231575	19	0	0
T11	41786	467	0	0
T12	331091	2331	0	0
T13	123313	171	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207391	0	0
T2	368876	5	0	0
T3	13437	19	0	0
T4	2301	13	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	16	0	0
T11	41786	457	0	0
T12	331091	185	0	0
T13	123313	152	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T8,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	205034	0	0
GntImpliesValid_A	400253245	205034	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	205034	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	5013552	0	0
ReadyAndValidImplyGrant_A	400253245	205034	0	0
ReqAndReadyImplyGrant_A	400253245	205034	0	0
ReqImpliesValid_A	400253245	1094141	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	205034	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	205034	0	0
T2	368876	4	0	0
T3	13437	25	0	0
T4	2301	18	0	0
T7	2161	18	0	0
T8	436870	17	0	0
T9	471279	9	0	0
T10	231575	7	0	0
T11	41786	437	0	0
T12	331091	191	0	0
T13	123313	157	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	205034	0	0
T2	368876	4	0	0
T3	13437	25	0	0
T4	2301	18	0	0
T7	2161	18	0	0
T8	436870	17	0	0
T9	471279	9	0	0
T10	231575	7	0	0
T11	41786	437	0	0
T12	331091	191	0	0
T13	123313	157	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	205034	0	0
T2	368876	4	0	0
T3	13437	25	0	0
T4	2301	18	0	0
T7	2161	18	0	0
T8	436870	17	0	0
T9	471279	9	0	0
T10	231575	7	0	0
T11	41786	437	0	0
T12	331091	191	0	0
T13	123313	157	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	5013552	0	0
T2	368876	5791	0	0
T3	13437	378	0	0
T4	2301	141	0	0
T7	2161	79	0	0
T8	436870	12550	0	0
T9	471279	573	0	0
T10	231575	61	0	0
T11	41786	2071	0	0
T12	331091	61059	0	0
T13	123313	9162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	205034	0	0
T2	368876	4	0	0
T3	13437	25	0	0
T4	2301	18	0	0
T7	2161	18	0	0
T8	436870	17	0	0
T9	471279	9	0	0
T10	231575	7	0	0
T11	41786	437	0	0
T12	331091	191	0	0
T13	123313	157	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	205034	0	0
T2	368876	4	0	0
T3	13437	25	0	0
T4	2301	18	0	0
T7	2161	18	0	0
T8	436870	17	0	0
T9	471279	9	0	0
T10	231575	7	0	0
T11	41786	437	0	0
T12	331091	191	0	0
T13	123313	157	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	1094141	0	0
T2	368876	660	0	0
T3	13437	25	0	0
T4	2301	33	0	0
T7	2161	18	0	0
T8	436870	1041	0	0
T9	471279	9	0	0
T10	231575	7	0	0
T11	41786	532	0	0
T12	331091	1643	0	0
T13	123313	285	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	205034	0	0
T2	368876	4	0	0
T3	13437	25	0	0
T4	2301	18	0	0
T7	2161	18	0	0
T8	436870	17	0	0
T9	471279	9	0	0
T10	231575	7	0	0
T11	41786	437	0	0
T12	331091	191	0	0
T13	123313	157	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	202389	0	0
GntImpliesValid_A	400253245	202389	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	202389	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	5224502	0	0
ReadyAndValidImplyGrant_A	400253245	202389	0	0
ReqAndReadyImplyGrant_A	400253245	202389	0	0
ReqImpliesValid_A	400253245	1105665	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	202389	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202389	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	9	0	0
T11	41786	454	0	0
T12	331091	199	0	0
T13	123313	201	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202389	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	9	0	0
T11	41786	454	0	0
T12	331091	199	0	0
T13	123313	201	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202389	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	9	0	0
T11	41786	454	0	0
T12	331091	199	0	0
T13	123313	201	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	5224502	0	0
T2	368876	2189	0	0
T3	13437	808	0	0
T4	2301	96	0	0
T7	2161	82	0	0
T8	436870	2072	0	0
T9	471279	554	0	0
T10	231575	93	0	0
T11	41786	2829	0	0
T12	331091	170366	0	0
T13	123313	3930	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202389	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	9	0	0
T11	41786	454	0	0
T12	331091	199	0	0
T13	123313	201	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202389	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	9	0	0
T11	41786	454	0	0
T12	331091	199	0	0
T13	123313	201	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	1105665	0	0
T2	368876	35	0	0
T3	13437	22	0	0
T4	2301	11	0	0
T7	2161	24	0	0
T8	436870	662	0	0
T9	471279	9	0	0
T10	231575	18	0	0
T11	41786	583	0	0
T12	331091	15004	0	0
T13	123313	221	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202389	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	9	0	0
T11	41786	454	0	0
T12	331091	199	0	0
T13	123313	201	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T7,T8,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T7,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	210320	0	0
GntImpliesValid_A	400253245	210320	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	210320	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	4792877	0	0
ReadyAndValidImplyGrant_A	400253245	210320	0	0
ReqAndReadyImplyGrant_A	400253245	210320	0	0
ReqImpliesValid_A	400253245	1151522	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	210320	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	210320	0	0
T2	368876	15	0	0
T3	13437	21	0	0
T4	2301	12	0	0
T7	2161	23	0	0
T8	436870	17	0	0
T9	471279	14	0	0
T10	231575	8	0	0
T11	41786	433	0	0
T12	331091	196	0	0
T13	123313	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	210320	0	0
T2	368876	15	0	0
T3	13437	21	0	0
T4	2301	12	0	0
T7	2161	23	0	0
T8	436870	17	0	0
T9	471279	14	0	0
T10	231575	8	0	0
T11	41786	433	0	0
T12	331091	196	0	0
T13	123313	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	210320	0	0
T2	368876	15	0	0
T3	13437	21	0	0
T4	2301	12	0	0
T7	2161	23	0	0
T8	436870	17	0	0
T9	471279	14	0	0
T10	231575	8	0	0
T11	41786	433	0	0
T12	331091	196	0	0
T13	123313	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	4792877	0	0
T2	368876	2652	0	0
T3	13437	333	0	0
T4	2301	63	0	0
T7	2161	108	0	0
T8	436870	3655	0	0
T9	471279	641	0	0
T10	231575	80	0	0
T11	41786	2004	0	0
T12	331091	62177	0	0
T13	123313	1991	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	210320	0	0
T2	368876	15	0	0
T3	13437	21	0	0
T4	2301	12	0	0
T7	2161	23	0	0
T8	436870	17	0	0
T9	471279	14	0	0
T10	231575	8	0	0
T11	41786	433	0	0
T12	331091	196	0	0
T13	123313	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	210320	0	0
T2	368876	15	0	0
T3	13437	21	0	0
T4	2301	12	0	0
T7	2161	23	0	0
T8	436870	17	0	0
T9	471279	14	0	0
T10	231575	8	0	0
T11	41786	433	0	0
T12	331091	196	0	0
T13	123313	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	1151522	0	0
T2	368876	15	0	0
T3	13437	21	0	0
T4	2301	21	0	0
T7	2161	28	0	0
T8	436870	210	0	0
T9	471279	14	0	0
T10	231575	8	0	0
T11	41786	530	0	0
T12	331091	5004	0	0
T13	123313	205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	210320	0	0
T2	368876	15	0	0
T3	13437	21	0	0
T4	2301	12	0	0
T7	2161	23	0	0
T8	436870	17	0	0
T9	471279	14	0	0
T10	231575	8	0	0
T11	41786	433	0	0
T12	331091	196	0	0
T13	123313	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	193588	0	0
GntImpliesValid_A	400253245	193588	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	193588	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	4766309	0	0
ReadyAndValidImplyGrant_A	400253245	193588	0	0
ReqAndReadyImplyGrant_A	400253245	193588	0	0
ReqImpliesValid_A	400253245	907756	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	193588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	193588	0	0
T2	368876	14	0	0
T3	13437	23	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	14	0	0
T10	231575	4	0	0
T11	41786	420	0	0
T12	331091	215	0	0
T13	123313	153	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	193588	0	0
T2	368876	14	0	0
T3	13437	23	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	14	0	0
T10	231575	4	0	0
T11	41786	420	0	0
T12	331091	215	0	0
T13	123313	153	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	193588	0	0
T2	368876	14	0	0
T3	13437	23	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	14	0	0
T10	231575	4	0	0
T11	41786	420	0	0
T12	331091	215	0	0
T13	123313	153	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	4766309	0	0
T2	368876	3287	0	0
T3	13437	318	0	0
T4	2301	68	0	0
T7	2161	80	0	0
T8	436870	3914	0	0
T9	471279	1089	0	0
T10	231575	51	0	0
T11	41786	3934	0	0
T12	331091	83337	0	0
T13	123313	1887	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	193588	0	0
T2	368876	14	0	0
T3	13437	23	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	14	0	0
T10	231575	4	0	0
T11	41786	420	0	0
T12	331091	215	0	0
T13	123313	153	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	193588	0	0
T2	368876	14	0	0
T3	13437	23	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	14	0	0
T10	231575	4	0	0
T11	41786	420	0	0
T12	331091	215	0	0
T13	123313	153	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	907756	0	0
T2	368876	400	0	0
T3	13437	23	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	74	0	0
T10	231575	4	0	0
T11	41786	645	0	0
T12	331091	4295	0	0
T13	123313	157	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	193588	0	0
T2	368876	14	0	0
T3	13437	23	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	13	0	0
T9	471279	14	0	0
T10	231575	4	0	0
T11	41786	420	0	0
T12	331091	215	0	0
T13	123313	153	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T8,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	202174	0	0
GntImpliesValid_A	400253245	202174	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	202174	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3024773	0	0
ReadyAndValidImplyGrant_A	400253245	202174	0	0
ReqAndReadyImplyGrant_A	400253245	202174	0	0
ReqImpliesValid_A	400253245	517934	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	202174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202174	0	0
T2	368876	7	0	0
T3	13437	22	0	0
T4	2301	12	0	0
T7	2161	21	0	0
T8	436870	10	0	0
T9	471279	6	0	0
T10	231575	7	0	0
T11	41786	425	0	0
T12	331091	185	0	0
T13	123313	209	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202174	0	0
T2	368876	7	0	0
T3	13437	22	0	0
T4	2301	12	0	0
T7	2161	21	0	0
T8	436870	10	0	0
T9	471279	6	0	0
T10	231575	7	0	0
T11	41786	425	0	0
T12	331091	185	0	0
T13	123313	209	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202174	0	0
T2	368876	7	0	0
T3	13437	22	0	0
T4	2301	12	0	0
T7	2161	21	0	0
T8	436870	10	0	0
T9	471279	6	0	0
T10	231575	7	0	0
T11	41786	425	0	0
T12	331091	185	0	0
T13	123313	209	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3024773	0	0
T1	691099	1	0	0
T2	368876	1357	0	0
T3	13437	164	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	4713	0	0
T9	471279	1742	0	0
T10	231575	26	0	0
T11	41786	414	0	0
T12	331091	63528	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202174	0	0
T2	368876	7	0	0
T3	13437	22	0	0
T4	2301	12	0	0
T7	2161	21	0	0
T8	436870	10	0	0
T9	471279	6	0	0
T10	231575	7	0	0
T11	41786	425	0	0
T12	331091	185	0	0
T13	123313	209	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202174	0	0
T2	368876	7	0	0
T3	13437	22	0	0
T4	2301	12	0	0
T7	2161	21	0	0
T8	436870	10	0	0
T9	471279	6	0	0
T10	231575	7	0	0
T11	41786	425	0	0
T12	331091	185	0	0
T13	123313	209	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	517934	0	0
T2	368876	7	0	0
T3	13437	23	0	0
T4	2301	14	0	0
T7	2161	21	0	0
T8	436870	77	0	0
T9	471279	6	0	0
T10	231575	7	0	0
T11	41786	438	0	0
T12	331091	2764	0	0
T13	123313	234	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	202174	0	0
T2	368876	7	0	0
T3	13437	22	0	0
T4	2301	12	0	0
T7	2161	21	0	0
T8	436870	10	0	0
T9	471279	6	0	0
T10	231575	7	0	0
T11	41786	425	0	0
T12	331091	185	0	0
T13	123313	209	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T8,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	201465	0	0
GntImpliesValid_A	400253245	201465	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	201465	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	2998624	0	0
ReadyAndValidImplyGrant_A	400253245	201465	0	0
ReqAndReadyImplyGrant_A	400253245	201465	0	0
ReqImpliesValid_A	400253245	568355	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	201465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201465	0	0
T2	368876	6	0	0
T3	13437	24	0	0
T4	2301	9	0	0
T7	2161	28	0	0
T8	436870	20	0	0
T9	471279	13	0	0
T10	231575	6	0	0
T11	41786	455	0	0
T12	331091	226	0	0
T13	123313	196	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201465	0	0
T2	368876	6	0	0
T3	13437	24	0	0
T4	2301	9	0	0
T7	2161	28	0	0
T8	436870	20	0	0
T9	471279	13	0	0
T10	231575	6	0	0
T11	41786	455	0	0
T12	331091	226	0	0
T13	123313	196	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201465	0	0
T2	368876	6	0	0
T3	13437	24	0	0
T4	2301	9	0	0
T7	2161	28	0	0
T8	436870	20	0	0
T9	471279	13	0	0
T10	231575	6	0	0
T11	41786	455	0	0
T12	331091	226	0	0
T13	123313	196	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2998624	0	0
T1	691099	1	0	0
T2	368876	1942	0	0
T3	13437	217	0	0
T4	2301	10	0	0
T7	2161	29	0	0
T8	436870	5886	0	0
T9	471279	4009	0	0
T10	231575	23	0	0
T11	41786	444	0	0
T12	331091	67162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201465	0	0
T2	368876	6	0	0
T3	13437	24	0	0
T4	2301	9	0	0
T7	2161	28	0	0
T8	436870	20	0	0
T9	471279	13	0	0
T10	231575	6	0	0
T11	41786	455	0	0
T12	331091	226	0	0
T13	123313	196	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201465	0	0
T2	368876	6	0	0
T3	13437	24	0	0
T4	2301	9	0	0
T7	2161	28	0	0
T8	436870	20	0	0
T9	471279	13	0	0
T10	231575	6	0	0
T11	41786	455	0	0
T12	331091	226	0	0
T13	123313	196	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	568355	0	0
T2	368876	6	0	0
T3	13437	24	0	0
T4	2301	9	0	0
T7	2161	28	0	0
T8	436870	237	0	0
T9	471279	13	0	0
T10	231575	9	0	0
T11	41786	468	0	0
T12	331091	6814	0	0
T13	123313	198	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201465	0	0
T2	368876	6	0	0
T3	13437	24	0	0
T4	2301	9	0	0
T7	2161	28	0	0
T8	436870	20	0	0
T9	471279	13	0	0
T10	231575	6	0	0
T11	41786	455	0	0
T12	331091	226	0	0
T13	123313	196	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	207718	0	0
GntImpliesValid_A	400253245	207718	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	207718	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3070893	0	0
ReadyAndValidImplyGrant_A	400253245	207718	0	0
ReqAndReadyImplyGrant_A	400253245	207718	0	0
ReqImpliesValid_A	400253245	571001	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	207718	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207718	0	0
T2	368876	7	0	0
T3	13437	16	0	0
T4	2301	12	0	0
T7	2161	29	0	0
T8	436870	11	0	0
T9	471279	13	0	0
T10	231575	3	0	0
T11	41786	418	0	0
T12	331091	193	0	0
T13	123313	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207718	0	0
T2	368876	7	0	0
T3	13437	16	0	0
T4	2301	12	0	0
T7	2161	29	0	0
T8	436870	11	0	0
T9	471279	13	0	0
T10	231575	3	0	0
T11	41786	418	0	0
T12	331091	193	0	0
T13	123313	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207718	0	0
T2	368876	7	0	0
T3	13437	16	0	0
T4	2301	12	0	0
T7	2161	29	0	0
T8	436870	11	0	0
T9	471279	13	0	0
T10	231575	3	0	0
T11	41786	418	0	0
T12	331091	193	0	0
T13	123313	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3070893	0	0
T1	691099	1	0	0
T2	368876	3391	0	0
T3	13437	114	0	0
T4	2301	12	0	0
T7	2161	30	0	0
T8	436870	3274	0	0
T9	471279	4771	0	0
T10	231575	16	0	0
T11	41786	410	0	0
T12	331091	60347	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207718	0	0
T2	368876	7	0	0
T3	13437	16	0	0
T4	2301	12	0	0
T7	2161	29	0	0
T8	436870	11	0	0
T9	471279	13	0	0
T10	231575	3	0	0
T11	41786	418	0	0
T12	331091	193	0	0
T13	123313	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207718	0	0
T2	368876	7	0	0
T3	13437	16	0	0
T4	2301	12	0	0
T7	2161	29	0	0
T8	436870	11	0	0
T9	471279	13	0	0
T10	231575	3	0	0
T11	41786	418	0	0
T12	331091	193	0	0
T13	123313	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	571001	0	0
T2	368876	753	0	0
T3	13437	16	0	0
T4	2301	13	0	0
T7	2161	29	0	0
T8	436870	11	0	0
T9	471279	155	0	0
T10	231575	3	0	0
T11	41786	428	0	0
T12	331091	2640	0	0
T13	123313	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	207718	0	0
T2	368876	7	0	0
T3	13437	16	0	0
T4	2301	12	0	0
T7	2161	29	0	0
T8	436870	11	0	0
T9	471279	13	0	0
T10	231575	3	0	0
T11	41786	418	0	0
T12	331091	193	0	0
T13	123313	166	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	209236	0	0
GntImpliesValid_A	400253245	209236	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	209236	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3023829	0	0
ReadyAndValidImplyGrant_A	400253245	209236	0	0
ReqAndReadyImplyGrant_A	400253245	209236	0	0
ReqImpliesValid_A	400253245	595243	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	209236	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	209236	0	0
T2	368876	16	0	0
T3	13437	18	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	8	0	0
T11	41786	447	0	0
T12	331091	211	0	0
T13	123313	193	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	209236	0	0
T2	368876	16	0	0
T3	13437	18	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	8	0	0
T11	41786	447	0	0
T12	331091	211	0	0
T13	123313	193	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	209236	0	0
T2	368876	16	0	0
T3	13437	18	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	8	0	0
T11	41786	447	0	0
T12	331091	211	0	0
T13	123313	193	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3023829	0	0
T1	691099	1	0	0
T2	368876	6078	0	0
T3	13437	135	0	0
T4	2301	11	0	0
T7	2161	23	0	0
T8	436870	2515	0	0
T9	471279	2270	0	0
T10	231575	33	0	0
T11	41786	434	0	0
T12	331091	64541	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	209236	0	0
T2	368876	16	0	0
T3	13437	18	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	8	0	0
T11	41786	447	0	0
T12	331091	211	0	0
T13	123313	193	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	209236	0	0
T2	368876	16	0	0
T3	13437	18	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	8	0	0
T11	41786	447	0	0
T12	331091	211	0	0
T13	123313	193	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	595243	0	0
T2	368876	102	0	0
T3	13437	18	0	0
T4	2301	12	0	0
T7	2161	22	0	0
T8	436870	48	0	0
T9	471279	48	0	0
T10	231575	10	0	0
T11	41786	462	0	0
T12	331091	2752	0	0
T13	123313	212	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	209236	0	0
T2	368876	16	0	0
T3	13437	18	0	0
T4	2301	11	0	0
T7	2161	22	0	0
T8	436870	6	0	0
T9	471279	9	0	0
T10	231575	8	0	0
T11	41786	447	0	0
T12	331091	211	0	0
T13	123313	193	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	201051	0	0
GntImpliesValid_A	400253245	201051	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	201051	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	2942347	0	0
ReadyAndValidImplyGrant_A	400253245	201051	0	0
ReqAndReadyImplyGrant_A	400253245	201051	0	0
ReqImpliesValid_A	400253245	537210	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	201051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201051	0	0
T2	368876	9	0	0
T3	13437	19	0	0
T4	2301	14	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	9	0	0
T11	41786	464	0	0
T12	331091	184	0	0
T13	123313	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201051	0	0
T2	368876	9	0	0
T3	13437	19	0	0
T4	2301	14	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	9	0	0
T11	41786	464	0	0
T12	331091	184	0	0
T13	123313	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201051	0	0
T2	368876	9	0	0
T3	13437	19	0	0
T4	2301	14	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	9	0	0
T11	41786	464	0	0
T12	331091	184	0	0
T13	123313	162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2942347	0	0
T1	691099	1	0	0
T2	368876	2341	0	0
T3	13437	146	0	0
T4	2301	15	0	0
T7	2161	23	0	0
T8	436870	4134	0	0
T9	471279	4512	0	0
T10	231575	46	0	0
T11	41786	453	0	0
T12	331091	64651	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201051	0	0
T2	368876	9	0	0
T3	13437	19	0	0
T4	2301	14	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	9	0	0
T11	41786	464	0	0
T12	331091	184	0	0
T13	123313	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201051	0	0
T2	368876	9	0	0
T3	13437	19	0	0
T4	2301	14	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	9	0	0
T11	41786	464	0	0
T12	331091	184	0	0
T13	123313	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	537210	0	0
T2	368876	867	0	0
T3	13437	19	0	0
T4	2301	14	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	443	0	0
T10	231575	11	0	0
T11	41786	477	0	0
T12	331091	1492	0	0
T13	123313	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	201051	0	0
T2	368876	9	0	0
T3	13437	19	0	0
T4	2301	14	0	0
T7	2161	22	0	0
T8	436870	14	0	0
T9	471279	13	0	0
T10	231575	9	0	0
T11	41786	464	0	0
T12	331091	184	0	0
T13	123313	162	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	200421	0	0
GntImpliesValid_A	400253245	200421	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	200421	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	2994936	0	0
ReadyAndValidImplyGrant_A	400253245	200421	0	0
ReqAndReadyImplyGrant_A	400253245	200421	0	0
ReqImpliesValid_A	400253245	539432	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	200421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200421	0	0
T1	691099	469	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	15	0	0
T7	2161	24	0	0
T8	436870	11	0	0
T9	471279	12	0	0
T10	231575	11	0	0
T11	41786	426	0	0
T12	331091	203	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200421	0	0
T1	691099	469	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	15	0	0
T7	2161	24	0	0
T8	436870	11	0	0
T9	471279	12	0	0
T10	231575	11	0	0
T11	41786	426	0	0
T12	331091	203	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200421	0	0
T1	691099	469	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	15	0	0
T7	2161	24	0	0
T8	436870	11	0	0
T9	471279	12	0	0
T10	231575	11	0	0
T11	41786	426	0	0
T12	331091	203	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2994936	0	0
T1	691099	1660	0	0
T2	368876	3597	0	0
T3	13437	209	0	0
T4	2301	16	0	0
T7	2161	25	0	0
T8	436870	3356	0	0
T9	471279	3280	0	0
T10	231575	53	0	0
T11	41786	420	0	0
T12	331091	58727	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200421	0	0
T1	691099	469	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	15	0	0
T7	2161	24	0	0
T8	436870	11	0	0
T9	471279	12	0	0
T10	231575	11	0	0
T11	41786	426	0	0
T12	331091	203	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200421	0	0
T1	691099	469	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	15	0	0
T7	2161	24	0	0
T8	436870	11	0	0
T9	471279	12	0	0
T10	231575	11	0	0
T11	41786	426	0	0
T12	331091	203	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	539432	0	0
T1	691099	1136	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	15	0	0
T7	2161	24	0	0
T8	436870	795	0	0
T9	471279	337	0	0
T10	231575	13	0	0
T11	41786	434	0	0
T12	331091	5600	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200421	0	0
T1	691099	469	0	0
T2	368876	12	0	0
T3	13437	22	0	0
T4	2301	15	0	0
T7	2161	24	0	0
T8	436870	11	0	0
T9	471279	12	0	0
T10	231575	11	0	0
T11	41786	426	0	0
T12	331091	203	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T4
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	200601	0	0
GntImpliesValid_A	400253245	200601	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	200601	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3025123	0	0
ReadyAndValidImplyGrant_A	400253245	200601	0	0
ReqAndReadyImplyGrant_A	400253245	200601	0	0
ReqImpliesValid_A	400253245	520351	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	200601	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200601	0	0
T2	368876	11	0	0
T3	13437	13	0	0
T4	2301	11	0	0
T7	2161	19	0	0
T8	436870	13	0	0
T9	471279	15	0	0
T10	231575	8	0	0
T11	41786	434	0	0
T12	331091	220	0	0
T13	123313	183	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200601	0	0
T2	368876	11	0	0
T3	13437	13	0	0
T4	2301	11	0	0
T7	2161	19	0	0
T8	436870	13	0	0
T9	471279	15	0	0
T10	231575	8	0	0
T11	41786	434	0	0
T12	331091	220	0	0
T13	123313	183	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200601	0	0
T2	368876	11	0	0
T3	13437	13	0	0
T4	2301	11	0	0
T7	2161	19	0	0
T8	436870	13	0	0
T9	471279	15	0	0
T10	231575	8	0	0
T11	41786	434	0	0
T12	331091	220	0	0
T13	123313	183	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3025123	0	0
T1	691099	1	0	0
T2	368876	2832	0	0
T3	13437	93	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	2476	0	0
T9	471279	4563	0	0
T10	231575	46	0	0
T11	41786	417	0	0
T12	331091	70743	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200601	0	0
T2	368876	11	0	0
T3	13437	13	0	0
T4	2301	11	0	0
T7	2161	19	0	0
T8	436870	13	0	0
T9	471279	15	0	0
T10	231575	8	0	0
T11	41786	434	0	0
T12	331091	220	0	0
T13	123313	183	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200601	0	0
T2	368876	11	0	0
T3	13437	13	0	0
T4	2301	11	0	0
T7	2161	19	0	0
T8	436870	13	0	0
T9	471279	15	0	0
T10	231575	8	0	0
T11	41786	434	0	0
T12	331091	220	0	0
T13	123313	183	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	520351	0	0
T2	368876	97	0	0
T3	13437	13	0	0
T4	2301	12	0	0
T7	2161	19	0	0
T8	436870	13	0	0
T9	471279	556	0	0
T10	231575	8	0	0
T11	41786	453	0	0
T12	331091	2513	0	0
T13	123313	183	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200601	0	0
T2	368876	11	0	0
T3	13437	13	0	0
T4	2301	11	0	0
T7	2161	19	0	0
T8	436870	13	0	0
T9	471279	15	0	0
T10	231575	8	0	0
T11	41786	434	0	0
T12	331091	220	0	0
T13	123313	183	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T8,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	211548	0	0
GntImpliesValid_A	400253245	211548	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	211548	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3043571	0	0
ReadyAndValidImplyGrant_A	400253245	211548	0	0
ReqAndReadyImplyGrant_A	400253245	211548	0	0
ReqImpliesValid_A	400253245	587909	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	211548	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	211548	0	0
T2	368876	7	0	0
T3	13437	19	0	0
T4	2301	15	0	0
T7	2161	18	0	0
T8	436870	15	0	0
T9	471279	18	0	0
T10	231575	14	0	0
T11	41786	444	0	0
T12	331091	193	0	0
T13	123313	210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	211548	0	0
T2	368876	7	0	0
T3	13437	19	0	0
T4	2301	15	0	0
T7	2161	18	0	0
T8	436870	15	0	0
T9	471279	18	0	0
T10	231575	14	0	0
T11	41786	444	0	0
T12	331091	193	0	0
T13	123313	210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	211548	0	0
T2	368876	7	0	0
T3	13437	19	0	0
T4	2301	15	0	0
T7	2161	18	0	0
T8	436870	15	0	0
T9	471279	18	0	0
T10	231575	14	0	0
T11	41786	444	0	0
T12	331091	193	0	0
T13	123313	210	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3043571	0	0
T1	691099	1	0	0
T2	368876	2507	0	0
T3	13437	163	0	0
T4	2301	16	0	0
T7	2161	19	0	0
T8	436870	4979	0	0
T9	471279	6818	0	0
T10	231575	62	0	0
T11	41786	432	0	0
T12	331091	62688	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	211548	0	0
T2	368876	7	0	0
T3	13437	19	0	0
T4	2301	15	0	0
T7	2161	18	0	0
T8	436870	15	0	0
T9	471279	18	0	0
T10	231575	14	0	0
T11	41786	444	0	0
T12	331091	193	0	0
T13	123313	210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	211548	0	0
T2	368876	7	0	0
T3	13437	19	0	0
T4	2301	15	0	0
T7	2161	18	0	0
T8	436870	15	0	0
T9	471279	18	0	0
T10	231575	14	0	0
T11	41786	444	0	0
T12	331091	193	0	0
T13	123313	210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	587909	0	0
T2	368876	7	0	0
T3	13437	19	0	0
T4	2301	15	0	0
T7	2161	18	0	0
T8	436870	731	0	0
T9	471279	325	0	0
T10	231575	14	0	0
T11	41786	458	0	0
T12	331091	2174	0	0
T13	123313	210	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	211548	0	0
T2	368876	7	0	0
T3	13437	19	0	0
T4	2301	15	0	0
T7	2161	18	0	0
T8	436870	15	0	0
T9	471279	18	0	0
T10	231575	14	0	0
T11	41786	444	0	0
T12	331091	193	0	0
T13	123313	210	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T13
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T11,T12,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T4,T11,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	216399	0	0
GntImpliesValid_A	400253245	216399	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	216399	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3017072	0	0
ReadyAndValidImplyGrant_A	400253245	216399	0	0
ReqAndReadyImplyGrant_A	400253245	216399	0	0
ReqImpliesValid_A	400253245	549455	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	216399	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	216399	0	0
T2	368876	10	0	0
T3	13437	18	0	0
T4	2301	8	0	0
T7	2161	23	0	0
T8	436870	8	0	0
T9	471279	14	0	0
T10	231575	13	0	0
T11	41786	537	0	0
T12	331091	214	0	0
T13	123313	180	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	216399	0	0
T2	368876	10	0	0
T3	13437	18	0	0
T4	2301	8	0	0
T7	2161	23	0	0
T8	436870	8	0	0
T9	471279	14	0	0
T10	231575	13	0	0
T11	41786	537	0	0
T12	331091	214	0	0
T13	123313	180	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	216399	0	0
T2	368876	10	0	0
T3	13437	18	0	0
T4	2301	8	0	0
T7	2161	23	0	0
T8	436870	8	0	0
T9	471279	14	0	0
T10	231575	13	0	0
T11	41786	537	0	0
T12	331091	214	0	0
T13	123313	180	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3017072	0	0
T1	691099	1	0	0
T2	368876	3088	0	0
T3	13437	106	0	0
T4	2301	9	0	0
T7	2161	24	0	0
T8	436870	4113	0	0
T9	471279	4427	0	0
T10	231575	75	0	0
T11	41786	516	0	0
T12	331091	70303	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	216399	0	0
T2	368876	10	0	0
T3	13437	18	0	0
T4	2301	8	0	0
T7	2161	23	0	0
T8	436870	8	0	0
T9	471279	14	0	0
T10	231575	13	0	0
T11	41786	537	0	0
T12	331091	214	0	0
T13	123313	180	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	216399	0	0
T2	368876	10	0	0
T3	13437	18	0	0
T4	2301	8	0	0
T7	2161	23	0	0
T8	436870	8	0	0
T9	471279	14	0	0
T10	231575	13	0	0
T11	41786	537	0	0
T12	331091	214	0	0
T13	123313	180	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	549455	0	0
T2	368876	10	0	0
T3	13437	18	0	0
T4	2301	8	0	0
T7	2161	23	0	0
T8	436870	8	0	0
T9	471279	14	0	0
T10	231575	13	0	0
T11	41786	560	0	0
T12	331091	6078	0	0
T13	123313	185	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	216399	0	0
T2	368876	10	0	0
T3	13437	18	0	0
T4	2301	8	0	0
T7	2161	23	0	0
T8	436870	8	0	0
T9	471279	14	0	0
T10	231575	13	0	0
T11	41786	537	0	0
T12	331091	214	0	0
T13	123313	180	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T8,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	208828	0	0
GntImpliesValid_A	400253245	208828	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	208828	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3066612	0	0
ReadyAndValidImplyGrant_A	400253245	208828	0	0
ReqAndReadyImplyGrant_A	400253245	208828	0	0
ReqImpliesValid_A	400253245	567650	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	208828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208828	0	0
T2	368876	9	0	0
T3	13437	15	0	0
T4	2301	16	0	0
T7	2161	29	0	0
T8	436870	16	0	0
T9	471279	13	0	0
T10	231575	13	0	0
T11	41786	445	0	0
T12	331091	170	0	0
T13	123313	164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208828	0	0
T2	368876	9	0	0
T3	13437	15	0	0
T4	2301	16	0	0
T7	2161	29	0	0
T8	436870	16	0	0
T9	471279	13	0	0
T10	231575	13	0	0
T11	41786	445	0	0
T12	331091	170	0	0
T13	123313	164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208828	0	0
T2	368876	9	0	0
T3	13437	15	0	0
T4	2301	16	0	0
T7	2161	29	0	0
T8	436870	16	0	0
T9	471279	13	0	0
T10	231575	13	0	0
T11	41786	445	0	0
T12	331091	170	0	0
T13	123313	164	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3066612	0	0
T1	691099	1	0	0
T2	368876	1825	0	0
T3	13437	102	0	0
T4	2301	17	0	0
T7	2161	30	0	0
T8	436870	2741	0	0
T9	471279	4893	0	0
T10	231575	48	0	0
T11	41786	438	0	0
T12	331091	55510	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208828	0	0
T2	368876	9	0	0
T3	13437	15	0	0
T4	2301	16	0	0
T7	2161	29	0	0
T8	436870	16	0	0
T9	471279	13	0	0
T10	231575	13	0	0
T11	41786	445	0	0
T12	331091	170	0	0
T13	123313	164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208828	0	0
T2	368876	9	0	0
T3	13437	15	0	0
T4	2301	16	0	0
T7	2161	29	0	0
T8	436870	16	0	0
T9	471279	13	0	0
T10	231575	13	0	0
T11	41786	445	0	0
T12	331091	170	0	0
T13	123313	164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	567650	0	0
T2	368876	9	0	0
T3	13437	15	0	0
T4	2301	16	0	0
T7	2161	29	0	0
T8	436870	1066	0	0
T9	471279	13	0	0
T10	231575	14	0	0
T11	41786	454	0	0
T12	331091	3006	0	0
T13	123313	169	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208828	0	0
T2	368876	9	0	0
T3	13437	15	0	0
T4	2301	16	0	0
T7	2161	29	0	0
T8	436870	16	0	0
T9	471279	13	0	0
T10	231575	13	0	0
T11	41786	445	0	0
T12	331091	170	0	0
T13	123313	164	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T4,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T4,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T9,T4,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	200517	0	0
GntImpliesValid_A	400253245	200517	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	200517	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	2948349	0	0
ReadyAndValidImplyGrant_A	400253245	200517	0	0
ReqAndReadyImplyGrant_A	400253245	200517	0	0
ReqImpliesValid_A	400253245	546271	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	200517	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200517	0	0
T2	368876	6	0	0
T3	13437	16	0	0
T4	2301	17	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	13	0	0
T10	231575	10	0	0
T11	41786	433	0	0
T12	331091	203	0	0
T13	123313	175	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200517	0	0
T2	368876	6	0	0
T3	13437	16	0	0
T4	2301	17	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	13	0	0
T10	231575	10	0	0
T11	41786	433	0	0
T12	331091	203	0	0
T13	123313	175	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200517	0	0
T2	368876	6	0	0
T3	13437	16	0	0
T4	2301	17	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	13	0	0
T10	231575	10	0	0
T11	41786	433	0	0
T12	331091	203	0	0
T13	123313	175	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2948349	0	0
T1	691099	1	0	0
T2	368876	1030	0	0
T3	13437	126	0	0
T4	2301	17	0	0
T7	2161	21	0	0
T8	436870	4946	0	0
T9	471279	4515	0	0
T10	231575	41	0	0
T11	41786	428	0	0
T12	331091	70603	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200517	0	0
T2	368876	6	0	0
T3	13437	16	0	0
T4	2301	17	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	13	0	0
T10	231575	10	0	0
T11	41786	433	0	0
T12	331091	203	0	0
T13	123313	175	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200517	0	0
T2	368876	6	0	0
T3	13437	16	0	0
T4	2301	17	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	13	0	0
T10	231575	10	0	0
T11	41786	433	0	0
T12	331091	203	0	0
T13	123313	175	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	546271	0	0
T2	368876	6	0	0
T3	13437	16	0	0
T4	2301	18	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	96	0	0
T10	231575	10	0	0
T11	41786	440	0	0
T12	331091	3799	0	0
T13	123313	189	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	200517	0	0
T2	368876	6	0	0
T3	13437	16	0	0
T4	2301	17	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	13	0	0
T10	231575	10	0	0
T11	41786	433	0	0
T12	331091	203	0	0
T13	123313	175	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T10
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T8,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	197009	0	0
GntImpliesValid_A	400253245	197009	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	197009	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	2988471	0	0
ReadyAndValidImplyGrant_A	400253245	197009	0	0
ReqAndReadyImplyGrant_A	400253245	197009	0	0
ReqImpliesValid_A	400253245	538708	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	197009	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197009	0	0
T2	368876	15	0	0
T3	13437	26	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	8	0	0
T10	231575	9	0	0
T11	41786	429	0	0
T12	331091	217	0	0
T13	123313	182	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197009	0	0
T2	368876	15	0	0
T3	13437	26	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	8	0	0
T10	231575	9	0	0
T11	41786	429	0	0
T12	331091	217	0	0
T13	123313	182	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197009	0	0
T2	368876	15	0	0
T3	13437	26	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	8	0	0
T10	231575	9	0	0
T11	41786	429	0	0
T12	331091	217	0	0
T13	123313	182	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2988471	0	0
T1	691099	1	0	0
T2	368876	6383	0	0
T3	13437	165	0	0
T4	2301	12	0	0
T7	2161	21	0	0
T8	436870	4991	0	0
T9	471279	2964	0	0
T10	231575	35	0	0
T11	41786	419	0	0
T12	331091	70934	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197009	0	0
T2	368876	15	0	0
T3	13437	26	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	8	0	0
T10	231575	9	0	0
T11	41786	429	0	0
T12	331091	217	0	0
T13	123313	182	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197009	0	0
T2	368876	15	0	0
T3	13437	26	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	8	0	0
T10	231575	9	0	0
T11	41786	429	0	0
T12	331091	217	0	0
T13	123313	182	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	538708	0	0
T2	368876	15	0	0
T3	13437	26	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	520	0	0
T9	471279	504	0	0
T10	231575	10	0	0
T11	41786	441	0	0
T12	331091	2601	0	0
T13	123313	182	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197009	0	0
T2	368876	15	0	0
T3	13437	26	0	0
T4	2301	11	0	0
T7	2161	20	0	0
T8	436870	13	0	0
T9	471279	8	0	0
T10	231575	9	0	0
T11	41786	429	0	0
T12	331091	217	0	0
T13	123313	182	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T11
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T7,T9,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	208527	0	0
GntImpliesValid_A	400253245	208527	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	208527	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	3020326	0	0
ReadyAndValidImplyGrant_A	400253245	208527	0	0
ReqAndReadyImplyGrant_A	400253245	208527	0	0
ReqImpliesValid_A	400253245	543506	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	208527	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208527	0	0
T2	368876	13	0	0
T3	13437	9	0	0
T4	2301	15	0	0
T7	2161	20	0	0
T8	436870	12	0	0
T9	471279	13	0	0
T10	231575	7	0	0
T11	41786	465	0	0
T12	331091	191	0	0
T13	123313	182	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208527	0	0
T2	368876	13	0	0
T3	13437	9	0	0
T4	2301	15	0	0
T7	2161	20	0	0
T8	436870	12	0	0
T9	471279	13	0	0
T10	231575	7	0	0
T11	41786	465	0	0
T12	331091	191	0	0
T13	123313	182	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208527	0	0
T2	368876	13	0	0
T3	13437	9	0	0
T4	2301	15	0	0
T7	2161	20	0	0
T8	436870	12	0	0
T9	471279	13	0	0
T10	231575	7	0	0
T11	41786	465	0	0
T12	331091	191	0	0
T13	123313	182	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	3020326	0	0
T1	691099	1	0	0
T2	368876	4448	0	0
T3	13437	57	0	0
T4	2301	16	0	0
T7	2161	20	0	0
T8	436870	3603	0	0
T9	471279	4291	0	0
T10	231575	34	0	0
T11	41786	460	0	0
T12	331091	57268	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208527	0	0
T2	368876	13	0	0
T3	13437	9	0	0
T4	2301	15	0	0
T7	2161	20	0	0
T8	436870	12	0	0
T9	471279	13	0	0
T10	231575	7	0	0
T11	41786	465	0	0
T12	331091	191	0	0
T13	123313	182	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208527	0	0
T2	368876	13	0	0
T3	13437	9	0	0
T4	2301	15	0	0
T7	2161	20	0	0
T8	436870	12	0	0
T9	471279	13	0	0
T10	231575	7	0	0
T11	41786	465	0	0
T12	331091	191	0	0
T13	123313	182	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	543506	0	0
T2	368876	13	0	0
T3	13437	9	0	0
T4	2301	15	0	0
T7	2161	21	0	0
T8	436870	12	0	0
T9	471279	590	0	0
T10	231575	7	0	0
T11	41786	472	0	0
T12	331091	5196	0	0
T13	123313	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	208527	0	0
T2	368876	13	0	0
T3	13437	9	0	0
T4	2301	15	0	0
T7	2161	20	0	0
T8	436870	12	0	0
T9	471279	13	0	0
T10	231575	7	0	0
T11	41786	465	0	0
T12	331091	191	0	0
T13	123313	182	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T11,T12
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T9,T4,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	197310	0	0
GntImpliesValid_A	400253245	197310	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	197310	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	2994143	0	0
ReadyAndValidImplyGrant_A	400253245	197310	0	0
ReqAndReadyImplyGrant_A	400253245	197310	0	0
ReqImpliesValid_A	400253245	550473	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	0	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	197310	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197310	0	0
T2	368876	11	0	0
T3	13437	27	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	9	0	0
T9	471279	10	0	0
T10	231575	14	0	0
T11	41786	465	0	0
T12	331091	197	0	0
T13	123313	148	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197310	0	0
T2	368876	11	0	0
T3	13437	27	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	9	0	0
T9	471279	10	0	0
T10	231575	14	0	0
T11	41786	465	0	0
T12	331091	197	0	0
T13	123313	148	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197310	0	0
T2	368876	11	0	0
T3	13437	27	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	9	0	0
T9	471279	10	0	0
T10	231575	14	0	0
T11	41786	465	0	0
T12	331091	197	0	0
T13	123313	148	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2994143	0	0
T1	691099	1	0	0
T2	368876	4664	0	0
T3	13437	187	0	0
T4	2301	10	0	0
T7	2161	24	0	0
T8	436870	3183	0	0
T9	471279	4354	0	0
T10	231575	49	0	0
T11	41786	455	0	0
T12	331091	69418	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197310	0	0
T2	368876	11	0	0
T3	13437	27	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	9	0	0
T9	471279	10	0	0
T10	231575	14	0	0
T11	41786	465	0	0
T12	331091	197	0	0
T13	123313	148	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197310	0	0
T2	368876	11	0	0
T3	13437	27	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	9	0	0
T9	471279	10	0	0
T10	231575	14	0	0
T11	41786	465	0	0
T12	331091	197	0	0
T13	123313	148	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	550473	0	0
T2	368876	11	0	0
T3	13437	27	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	9	0	0
T9	471279	70	0	0
T10	231575	14	0	0
T11	41786	477	0	0
T12	331091	2249	0	0
T13	123313	148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	197310	0	0
T2	368876	11	0	0
T3	13437	27	0	0
T4	2301	9	0	0
T7	2161	23	0	0
T8	436870	9	0	0
T9	471279	10	0	0
T10	231575	14	0	0
T11	41786	465	0	0
T12	331091	197	0	0
T13	123313	148	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	812257	0	0
GntImpliesValid_A	400253245	812257	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	812257	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	11376484	0	0
ReadyAndValidImplyGrant_A	400253245	812257	0	0
ReqAndReadyImplyGrant_A	400253245	812257	0	0
ReqImpliesValid_A	400253245	2182881	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	15228	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	812257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	812257	0	0
T1	691099	848	0	0
T2	368876	58	0	0
T3	13437	69	0	0
T4	2301	45	0	0
T7	2161	71	0	0
T8	436870	47	0	0
T9	471279	43	0	0
T10	231575	41	0	0
T11	41786	1824	0	0
T12	331091	841	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	812257	0	0
T1	691099	848	0	0
T2	368876	58	0	0
T3	13437	69	0	0
T4	2301	45	0	0
T7	2161	71	0	0
T8	436870	47	0	0
T9	471279	43	0	0
T10	231575	41	0	0
T11	41786	1824	0	0
T12	331091	841	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	812257	0	0
T1	691099	848	0	0
T2	368876	58	0	0
T3	13437	69	0	0
T4	2301	45	0	0
T7	2161	71	0	0
T8	436870	47	0	0
T9	471279	43	0	0
T10	231575	41	0	0
T11	41786	1824	0	0
T12	331091	841	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	11376484	0	0
T1	691099	2244	0	0
T2	368876	20675	0	0
T3	13437	409	0	0
T4	2301	1	0	0
T7	2161	1	0	0
T8	436870	14847	0	0
T9	471279	16012	0	0
T10	231575	139	0	0
T11	41786	2	0	0
T12	331091	275154	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	812257	0	0
T1	691099	848	0	0
T2	368876	58	0	0
T3	13437	69	0	0
T4	2301	45	0	0
T7	2161	71	0	0
T8	436870	47	0	0
T9	471279	43	0	0
T10	231575	41	0	0
T11	41786	1824	0	0
T12	331091	841	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	812257	0	0
T1	691099	848	0	0
T2	368876	58	0	0
T3	13437	69	0	0
T4	2301	45	0	0
T7	2161	71	0	0
T8	436870	47	0	0
T9	471279	43	0	0
T10	231575	41	0	0
T11	41786	1824	0	0
T12	331091	841	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	2182881	0	0
T1	691099	1893	0	0
T2	368876	151	0	0
T3	13437	103	0	0
T4	2301	45	0	0
T7	2161	71	0	0
T8	436870	361	0	0
T9	471279	1003	0	0
T10	231575	57	0	0
T11	41786	1824	0	0
T12	331091	30259	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	15228	0	900
T1	691099	11	0	1
T2	368876	0	0	1
T3	13437	0	0	1
T4	2301	0	0	1
T7	2161	0	0	1
T8	436870	0	0	1
T9	471279	0	0	1
T10	231575	0	0	1
T11	41786	23	0	1
T12	331091	0	0	1
T13	0	1	0	0
T15	0	16	0	0
T16	0	2	0	0
T17	0	4	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	0	13	0	0
T22	0	146	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	812257	0	0
T1	691099	848	0	0
T2	368876	58	0	0
T3	13437	69	0	0
T4	2301	45	0	0
T7	2161	71	0	0
T8	436870	47	0	0
T9	471279	43	0	0
T10	231575	41	0	0
T11	41786	1824	0	0
T12	331091	841	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400253245	400135589	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400253245	802106	0	0
GntImpliesValid_A	400253245	802106	0	0
GrantKnown_A	400253245	400135589	0	0
IdxKnown_A	400253245	400135589	0	0
IndexIsCorrect_A	400253245	802106	0	0
LockArbDecision_A	400253245	0	0	0
NoReadyValidNoGrant_A	400253245	336984668	0	0
ReadyAndValidImplyGrant_A	400253245	802106	0	0
ReqAndReadyImplyGrant_A	400253245	802106	0	0
ReqImpliesValid_A	400253245	13147729	0	0
ReqStaysHighUntilGranted0_M	400253245	0	0	0
RoundRobin_A	400253245	21184	0	900
ValidKnown_A	400253245	400135589	0	0
gen_data_port_assertion.DataFlow_A	400253245	802106	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	802106	0	0
T1	691099	50	0	0
T2	368876	39	0	0
T3	13437	120	0	0
T4	2301	49	0	0
T7	2161	79	0	0
T8	436870	49	0	0
T9	471279	54	0	0
T10	231575	46	0	0
T11	41786	1839	0	0
T12	331091	763	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	802106	0	0
T1	691099	50	0	0
T2	368876	39	0	0
T3	13437	120	0	0
T4	2301	49	0	0
T7	2161	79	0	0
T8	436870	49	0	0
T9	471279	54	0	0
T10	231575	46	0	0
T11	41786	1839	0	0
T12	331091	763	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	802106	0	0
T1	691099	50	0	0
T2	368876	39	0	0
T3	13437	120	0	0
T4	2301	49	0	0
T7	2161	79	0	0
T8	436870	49	0	0
T9	471279	54	0	0
T10	231575	46	0	0
T11	41786	1839	0	0
T12	331091	763	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	336984668	0	0
T1	691099	575807	0	0
T2	368876	353391	0	0
T3	13437	11359	0	0
T4	2301	1	0	0
T7	2161	1	0	0
T8	436870	412988	0	0
T9	471279	451663	0	0
T10	231575	192722	0	0
T11	41786	1	0	0
T12	331091	303331	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	802106	0	0
T1	691099	50	0	0
T2	368876	39	0	0
T3	13437	120	0	0
T4	2301	49	0	0
T7	2161	79	0	0
T8	436870	49	0	0
T9	471279	54	0	0
T10	231575	46	0	0
T11	41786	1839	0	0
T12	331091	763	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	802106	0	0
T1	691099	50	0	0
T2	368876	39	0	0
T3	13437	120	0	0
T4	2301	49	0	0
T7	2161	79	0	0
T8	436870	49	0	0
T9	471279	54	0	0
T10	231575	46	0	0
T11	41786	1839	0	0
T12	331091	763	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	13147729	0	0
T1	691099	226	0	0
T2	368876	14740	0	0
T3	13437	881	0	0
T4	2301	49	0	0
T7	2161	79	0	0
T8	436870	12340	0	0
T9	471279	18733	0	0
T10	231575	185	0	0
T11	41786	1839	0	0
T12	331091	271693	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	21184	0	900
T4	2301	0	0	1
T7	2161	3	0	1
T8	436870	0	0	1
T9	471279	0	0	1
T10	231575	0	0	1
T11	41786	26	0	1
T12	331091	0	0	1
T13	123313	0	0	1
T14	28343	14	0	1
T15	0	8	0	0
T16	0	14	0	0
T17	0	5	0	0
T18	0	14	0	0
T19	0	8	0	0
T22	0	2	0	0
T23	0	7	0	0
T24	1797	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	400135589	0	0
T1	691099	691079	0	0
T2	368876	368836	0	0
T3	13437	13354	0	0
T4	2301	2239	0	0
T7	2161	2146	0	0
T8	436870	436813	0	0
T9	471279	471268	0	0
T10	231575	231527	0	0
T11	41786	41710	0	0
T12	331091	331084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400253245	802106	0	0
T1	691099	50	0	0
T2	368876	39	0	0
T3	13437	120	0	0
T4	2301	49	0	0
T7	2161	79	0	0
T8	436870	49	0	0
T9	471279	54	0	0
T10	231575	46	0	0
T11	41786	1839	0	0
T12	331091	763	0	0