Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1500580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239342

1

T1

29

T2

19

T3

125

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	591026	1			T1	59		T2	50		T3	302
values[0x0]	560177	1			T1	47		T2	44		T3	260
values[0x1]	588719	1			T1	69		T2	37		T3	286

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1160131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

579791

1

T1

61

T2

46

T3

296

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27178	1			T1	4		T2	1		T3	13
valid_sources[0x01]	27626	1			T2	1		T3	6		T8	1
valid_sources[0x02]	26978	1			T2	2		T3	9		T8	3
valid_sources[0x03]	27376	1			T1	5		T3	12		T7	1
valid_sources[0x04]	27963	1			T1	2		T2	2		T3	11
valid_sources[0x05]	26948	1			T1	3		T3	15		T8	2
valid_sources[0x06]	27343	1			T1	3		T2	2		T3	10
valid_sources[0x07]	27081	1			T1	3		T2	1		T3	13
valid_sources[0x08]	27348	1			T1	5		T2	3		T3	9
valid_sources[0x09]	27010	1			T1	1		T2	2		T3	11
valid_sources[0x0a]	26673	1			T1	2		T2	1		T3	14
valid_sources[0x0b]	27403	1			T1	3		T2	2		T3	17
valid_sources[0x0c]	26564	1			T1	1		T2	2		T3	12
valid_sources[0x0d]	28130	1			T1	6		T2	3		T3	14
valid_sources[0x0e]	26555	1			T1	2		T2	1		T3	19
valid_sources[0x0f]	26222	1			T1	4		T2	3		T3	12
valid_sources[0x10]	27002	1			T1	4		T2	5		T3	10
valid_sources[0x11]	28000	1			T1	4		T2	1		T3	10
valid_sources[0x12]	26641	1			T1	1		T3	9		T7	1
valid_sources[0x13]	26912	1			T1	4		T2	4		T3	8
valid_sources[0x14]	26872	1			T1	2		T2	3		T3	14
valid_sources[0x15]	27081	1			T1	1		T2	2		T3	11
valid_sources[0x16]	27183	1			T1	1		T3	15		T7	3
valid_sources[0x17]	26841	1			T1	4		T2	2		T3	14
valid_sources[0x18]	27146	1			T1	3		T2	1		T3	14
valid_sources[0x19]	27092	1			T1	5		T2	4		T3	17
valid_sources[0x1a]	27439	1			T1	4		T3	13		T8	3
valid_sources[0x1b]	27567	1			T1	1		T2	1		T3	15
valid_sources[0x1c]	28107	1			T1	5		T2	1		T3	12
valid_sources[0x1d]	26487	1			T1	2		T2	1		T3	18
valid_sources[0x1e]	27659	1			T1	1		T2	3		T3	9
valid_sources[0x1f]	27424	1			T1	6		T2	1		T3	8
valid_sources[0x20]	26855	1			T1	1		T2	2		T3	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25111

1

T1

6

T3

17

T7

6

values[0x0]

all_enables

biggest_size

189087

1

T1

17

T2

17

T3

98

values[0x1]

all_enables

biggest_size

25144

1

T1

6

T2

2

T3

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1518928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246590

1

T1

23

T2

20

T3

102

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	604714	1			T1	37		T2	46		T3	248
values[0x0]	556448	1			T1	40		T2	41		T3	268
values[0x1]	604356	1			T1	38		T2	45		T3	252

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1165631	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

599887

1

T1

43

T2

44

T3

247

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27869	1			T2	5		T3	7		T7	4
valid_sources[0x01]	27859	1			T2	2		T3	16		T7	3
valid_sources[0x02]	27566	1			T2	2		T3	10		T8	4
valid_sources[0x03]	27382	1			T2	2		T3	23		T8	3
valid_sources[0x04]	28115	1			T2	1		T3	16		T7	2
valid_sources[0x05]	26863	1			T2	2		T3	24		T7	1
valid_sources[0x06]	27648	1			T2	3		T3	1		T7	11
valid_sources[0x07]	27796	1			T2	3		T3	10		T7	2
valid_sources[0x08]	26707	1			T1	37		T2	5		T3	5
valid_sources[0x09]	27555	1			T2	2		T3	9		T7	6
valid_sources[0x0a]	27005	1			T2	3		T3	10		T7	3
valid_sources[0x0b]	27315	1			T2	2		T3	7		T7	10
valid_sources[0x0c]	27275	1			T2	1		T3	7		T7	1
valid_sources[0x0d]	28444	1			T3	9		T8	6		T9	55
valid_sources[0x0e]	27724	1			T2	2		T3	10		T7	4
valid_sources[0x0f]	27396	1			T2	3		T3	28		T8	3
valid_sources[0x10]	27103	1			T1	28		T2	2		T3	14
valid_sources[0x11]	28632	1			T2	4		T3	3		T8	3
valid_sources[0x12]	27636	1			T2	2		T3	9		T7	1
valid_sources[0x13]	27162	1			T2	2		T3	12		T7	2
valid_sources[0x14]	28212	1			T2	4		T3	19		T7	4
valid_sources[0x15]	28269	1			T2	2		T3	12		T7	5
valid_sources[0x16]	27162	1			T3	5		T7	8		T8	4
valid_sources[0x17]	28394	1			T2	2		T3	8		T7	2
valid_sources[0x18]	27591	1			T2	3		T3	20		T8	3
valid_sources[0x19]	27780	1			T2	4		T3	8		T7	1
valid_sources[0x1a]	27672	1			T2	1		T3	4		T8	3
valid_sources[0x1b]	27368	1			T3	3		T8	4		T9	34
valid_sources[0x1c]	27312	1			T3	6		T8	2		T9	28
valid_sources[0x1d]	27442	1			T2	1		T3	27		T7	2
valid_sources[0x1e]	27935	1			T2	3		T7	1		T8	2
valid_sources[0x1f]	27396	1			T2	4		T3	12		T7	1
valid_sources[0x20]	27632	1			T1	26		T2	1		T3	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25983

1

T1

5

T2

5

T3

10

values[0x0]

all_enables

biggest_size

194671

1

T1

15

T2

13

T3

84

values[0x1]

all_enables

biggest_size

25936

1

T1

3

T2

2

T3

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1514109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241309

1

T1

15

T2

20

T3

102

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	596406	1			T1	52		T2	47		T3	296
values[0x0]	564446	1			T1	34		T2	53		T3	292
values[0x1]	594566	1			T1	48		T2	42		T3	319

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1170286	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

585132

1

T1

36

T2

45

T3

257

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27995	1			T1	1		T3	20		T7	2
valid_sources[0x01]	28229	1			T1	3		T2	1		T3	4
valid_sources[0x02]	27100	1			T1	3		T2	4		T3	7
valid_sources[0x03]	26839	1			T1	4		T3	21		T8	1
valid_sources[0x04]	27120	1			T1	1		T2	4		T3	4
valid_sources[0x05]	26798	1			T1	3		T2	1		T3	24
valid_sources[0x06]	27414	1			T1	3		T2	2		T3	7
valid_sources[0x07]	27728	1			T1	3		T2	6		T3	14
valid_sources[0x08]	26828	1			T1	1		T3	15		T7	3
valid_sources[0x09]	27687	1			T1	2		T2	2		T3	17
valid_sources[0x0a]	26499	1			T1	2		T3	4		T7	1
valid_sources[0x0b]	27599	1			T1	3		T3	13		T7	3
valid_sources[0x0c]	27871	1			T1	2		T2	1		T3	26
valid_sources[0x0d]	27284	1			T1	3		T2	1		T3	12
valid_sources[0x0e]	27279	1			T1	4		T2	4		T3	10
valid_sources[0x0f]	27251	1			T1	3		T2	5		T3	19
valid_sources[0x10]	27077	1			T1	1		T2	3		T3	20
valid_sources[0x11]	28121	1			T1	2		T2	4		T3	10
valid_sources[0x12]	27991	1			T1	1		T2	3		T3	17
valid_sources[0x13]	27124	1			T1	3		T3	10		T8	1
valid_sources[0x14]	26651	1			T2	3		T3	12		T7	1
valid_sources[0x15]	27124	1			T1	1		T2	6		T3	8
valid_sources[0x16]	26752	1			T1	4		T3	6		T7	4
valid_sources[0x17]	27818	1			T1	2		T3	14		T7	2
valid_sources[0x18]	28450	1			T1	1		T2	1		T3	15
valid_sources[0x19]	27598	1			T1	5		T3	9		T7	2
valid_sources[0x1a]	26620	1			T1	5		T2	2		T3	15
valid_sources[0x1b]	27221	1			T2	1		T3	5		T8	5
valid_sources[0x1c]	27715	1			T1	2		T2	10		T3	23
valid_sources[0x1d]	27189	1			T1	3		T3	14		T7	4
valid_sources[0x1e]	28013	1			T1	7		T2	3		T3	25
valid_sources[0x1f]	27819	1			T1	2		T2	5		T3	15
valid_sources[0x20]	27228	1			T1	1		T2	2		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25322

1

T1

2

T2

3

T3

10

values[0x0]

all_enables

biggest_size

190534

1

T1

11

T2

17

T3

76

values[0x1]

all_enables

biggest_size

25453

1

T1

2

T3

16

T7

1