Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_27.fifo_h.reqfifo

Module Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	97.50	84.09			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	173795914	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	173795914	0	0
T1	4226	1172	0	0
T2	1009	330	0	0
T3	499471	402827	0	0
T7	413184	111590	0	0
T8	20360	10140	0	0
T9	266150	154857	0	0
T10	34477	15622	0	0
T11	538030	173571	0	0
T12	163674	513554	0	0
T13	412892	76236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	65411722	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	65411722	0	0
T1	4226	986	0	0
T2	1009	132	0	0
T3	499471	4277	0	0
T7	413184	59598	0	0
T8	20360	3750	0	0
T9	266150	796230	0	0
T10	34477	5964	0	0
T11	538030	33044	0	0
T12	163674	131591	0	0
T13	412892	36191	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	1652293	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1652293	0	0
T1	4226	15	0	0
T2	1009	13	0	0
T3	499471	221	0	0
T7	413184	1515	0	0
T8	20360	1088	0	0
T9	266150	620	0	0
T10	34477	1454	0	0
T11	538030	4524	0	0
T12	163674	7566	0	0
T13	412892	3706	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	16198525	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	16198525	0	0
T1	4226	73	0	0
T2	1009	13	0	0
T3	499471	1613	0	0
T7	413184	15239	0	0
T8	20360	885	0	0
T9	266150	167713	0	0
T10	34477	1305	0	0
T11	538030	9002	0	0
T12	163674	23343	0	0
T13	412892	9354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	1827777	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1827777	0	0
T1	4226	21	0	0
T2	1009	21	0	0
T3	499471	320	0	0
T7	413184	29	0	0
T8	20360	1046	0	0
T9	266150	1753	0	0
T10	34477	1367	0	0
T11	538030	2138	0	0
T12	163674	11397	0	0
T13	412892	4577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	16142479	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	16142479	0	0
T1	4226	97	0	0
T2	1009	18	0	0
T3	499471	1263	0	0
T7	413184	10100	0	0
T8	20360	822	0	0
T9	266150	268248	0	0
T10	34477	1101	0	0
T11	538030	7121	0	0
T12	163674	32179	0	0
T13	412892	8784	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	9933314	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	9933314	0	0
T1	4226	128	0	0
T2	1009	14	0	0
T3	499471	763	0	0
T7	413184	17950	0	0
T8	20360	883	0	0
T9	266150	1998	0	0
T10	34477	2098	0	0
T11	538030	37456	0	0
T12	163674	126830	0	0
T13	412892	16578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	15633227	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	15633227	0	0
T1	4226	92	0	0
T2	1009	14	0	0
T3	499471	179	0	0
T7	413184	21416	0	0
T8	20360	878	0	0
T9	266150	159981	0	0
T10	34477	1554	0	0
T11	538030	9113	0	0
T12	163674	44568	0	0
T13	412892	8989	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	1799422	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1799422	0	0
T1	4226	24	0	0
T2	1009	25	0	0
T3	499471	261	0	0
T7	413184	1113	0	0
T8	20360	997	0	0
T9	266150	701	0	0
T10	34477	1330	0	0
T11	538030	1622	0	0
T12	163674	13587	0	0
T13	412892	3232	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	16609626	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	16609626	0	0
T1	4226	119	0	0
T2	1009	18	0	0
T3	499471	1221	0	0
T7	413184	12843	0	0
T8	20360	804	0	0
T9	266150	199436	0	0
T10	34477	1067	0	0
T11	538030	7808	0	0
T12	163674	31501	0	0
T13	412892	7552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	2	2	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Excluded	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	13439527	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	13439527	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	13439527	0	0
T1	4226	128	0	0
T2	1009	21	0	0
T3	499471	1117	0	0
T7	413184	17563	0	0
T8	20360	1292	0	0
T9	266150	2034	0	0
T10	34477	1890	0	0
T11	538030	59091	0	0
T12	163674	147205	0	0
T13	412892	23410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	13439527	0	0
T1	4226	128	0	0
T2	1009	21	0	0
T3	499471	1117	0	0
T7	413184	17563	0	0
T8	20360	1292	0	0
T9	266150	2034	0	0
T10	34477	1890	0	0
T11	538030	59091	0	0
T12	163674	147205	0	0
T13	412892	23410	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	20312191	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	20312191	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	20312191	0	0
T1	4226	105	0	0
T2	1009	21	0	0
T3	499471	1688	0	0
T7	413184	15764	0	0
T8	20360	1163	0	0
T9	266150	167713	0	0
T10	34477	1890	0	0
T11	538030	13210	0	0
T12	163674	40622	0	0
T13	412892	13784	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	20312191	0	0
T1	4226	105	0	0
T2	1009	21	0	0
T3	499471	1688	0	0
T7	413184	15764	0	0
T8	20360	1163	0	0
T9	266150	167713	0	0
T10	34477	1890	0	0
T11	538030	13210	0	0
T12	163674	40622	0	0
T13	412892	13784	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	1652293	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1652293	0	0
T1	4226	15	0	0
T2	1009	13	0	0
T3	499471	221	0	0
T7	413184	1515	0	0
T8	20360	1088	0	0
T9	266150	620	0	0
T10	34477	1454	0	0
T11	538030	4524	0	0
T12	163674	7566	0	0
T13	412892	3706	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	16198525	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	16198525	0	0
T1	4226	73	0	0
T2	1009	13	0	0
T3	499471	1613	0	0
T7	413184	15239	0	0
T8	20360	885	0	0
T9	266150	167713	0	0
T10	34477	1305	0	0
T11	538030	9002	0	0
T12	163674	23343	0	0
T13	412892	9354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0