SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.31 | 100.00 | 81.25 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.57 | 97.50 | 80.56 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.75 | 100.00 | 75.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.88 | 97.50 | 77.78 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 404154 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 404154 | 0 | 0 |
T1 | 4226 | 4 | 0 | 0 |
T2 | 1009 | 4 | 0 | 0 |
T3 | 499471 | 30 | 0 | 0 |
T7 | 413184 | 5 | 0 | 0 |
T8 | 20360 | 89 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 330 | 0 | 0 |
T11 | 538030 | 159 | 0 | 0 |
T12 | 163674 | 1103 | 0 | 0 |
T13 | 412892 | 599 | 0 | 0 |
T14 | 0 | 503 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 3575984 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3575984 | 0 | 0 |
T1 | 4226 | 32 | 0 | 0 |
T2 | 1009 | 4 | 0 | 0 |
T3 | 499471 | 30 | 0 | 0 |
T7 | 413184 | 520 | 0 | 0 |
T8 | 20360 | 85 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 318 | 0 | 0 |
T11 | 538030 | 3430 | 0 | 0 |
T12 | 163674 | 16955 | 0 | 0 |
T13 | 412892 | 3354 | 0 | 0 |
T14 | 0 | 261 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 512373 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 512373 | 0 | 0 |
T2 | 1009 | 4 | 0 | 0 |
T3 | 499471 | 57 | 0 | 0 |
T7 | 413184 | 5 | 0 | 0 |
T8 | 20360 | 272 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 298 | 0 | 0 |
T11 | 538030 | 1527 | 0 | 0 |
T12 | 163674 | 1819 | 0 | 0 |
T13 | 412892 | 1299 | 0 | 0 |
T14 | 20007 | 407 | 0 | 0 |
T15 | 0 | 71 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 537682 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 537682 | 0 | 0 |
T2 | 1009 | 4 | 0 | 0 |
T3 | 499471 | 45 | 0 | 0 |
T7 | 413184 | 5 | 0 | 0 |
T8 | 20360 | 193 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 267 | 0 | 0 |
T11 | 538030 | 778 | 0 | 0 |
T12 | 163674 | 324 | 0 | 0 |
T13 | 412892 | 1076 | 0 | 0 |
T14 | 20007 | 240 | 0 | 0 |
T15 | 0 | 71 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 13496374 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 403733496 | 13496374 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 13496374 | 0 | 0 |
T1 | 4226 | 199 | 0 | 0 |
T2 | 1009 | 26 | 0 | 0 |
T3 | 499471 | 1280 | 0 | 0 |
T7 | 413184 | 12165 | 0 | 0 |
T8 | 20360 | 995 | 0 | 0 |
T9 | 266150 | 5628 | 0 | 0 |
T10 | 34477 | 1196 | 0 | 0 |
T11 | 538030 | 49701 | 0 | 0 |
T12 | 163674 | 155240 | 0 | 0 |
T13 | 412892 | 24596 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 13496374 | 0 | 0 |
T1 | 4226 | 199 | 0 | 0 |
T2 | 1009 | 26 | 0 | 0 |
T3 | 499471 | 1280 | 0 | 0 |
T7 | 413184 | 12165 | 0 | 0 |
T8 | 20360 | 995 | 0 | 0 |
T9 | 266150 | 5628 | 0 | 0 |
T10 | 34477 | 1196 | 0 | 0 |
T11 | 538030 | 49701 | 0 | 0 |
T12 | 163674 | 155240 | 0 | 0 |
T13 | 412892 | 24596 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 20171558 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 403733496 | 20171558 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 20171558 | 0 | 0 |
T1 | 4226 | 111 | 0 | 0 |
T2 | 1009 | 26 | 0 | 0 |
T3 | 499471 | 1335 | 0 | 0 |
T7 | 413184 | 10825 | 0 | 0 |
T8 | 20360 | 995 | 0 | 0 |
T9 | 266150 | 360455 | 0 | 0 |
T10 | 34477 | 1196 | 0 | 0 |
T11 | 538030 | 13646 | 0 | 0 |
T12 | 163674 | 47170 | 0 | 0 |
T13 | 412892 | 13820 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 20171558 | 0 | 0 |
T1 | 4226 | 111 | 0 | 0 |
T2 | 1009 | 26 | 0 | 0 |
T3 | 499471 | 1335 | 0 | 0 |
T7 | 413184 | 10825 | 0 | 0 |
T8 | 20360 | 995 | 0 | 0 |
T9 | 266150 | 360455 | 0 | 0 |
T10 | 34477 | 1196 | 0 | 0 |
T11 | 538030 | 13646 | 0 | 0 |
T12 | 163674 | 47170 | 0 | 0 |
T13 | 412892 | 13820 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 1827777 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 1827777 | 0 | 0 |
T1 | 4226 | 21 | 0 | 0 |
T2 | 1009 | 21 | 0 | 0 |
T3 | 499471 | 320 | 0 | 0 |
T7 | 413184 | 29 | 0 | 0 |
T8 | 20360 | 1046 | 0 | 0 |
T9 | 266150 | 1753 | 0 | 0 |
T10 | 34477 | 1367 | 0 | 0 |
T11 | 538030 | 2138 | 0 | 0 |
T12 | 163674 | 11397 | 0 | 0 |
T13 | 412892 | 4577 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 16142479 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 16142479 | 0 | 0 |
T1 | 4226 | 97 | 0 | 0 |
T2 | 1009 | 18 | 0 | 0 |
T3 | 499471 | 1263 | 0 | 0 |
T7 | 413184 | 10100 | 0 | 0 |
T8 | 20360 | 822 | 0 | 0 |
T9 | 266150 | 268248 | 0 | 0 |
T10 | 34477 | 1101 | 0 | 0 |
T11 | 538030 | 7121 | 0 | 0 |
T12 | 163674 | 32179 | 0 | 0 |
T13 | 412892 | 8784 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 462809 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 462809 | 0 | 0 |
T1 | 4226 | 2 | 0 | 0 |
T2 | 1009 | 8 | 0 | 0 |
T3 | 499471 | 69 | 0 | 0 |
T7 | 413184 | 3 | 0 | 0 |
T8 | 20360 | 113 | 0 | 0 |
T9 | 266150 | 1105 | 0 | 0 |
T10 | 34477 | 49 | 0 | 0 |
T11 | 538030 | 2076 | 0 | 0 |
T12 | 163674 | 1025 | 0 | 0 |
T13 | 412892 | 818 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 3479536 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3479536 | 0 | 0 |
T1 | 4226 | 6 | 0 | 0 |
T2 | 1009 | 7 | 0 | 0 |
T3 | 499471 | 42 | 0 | 0 |
T7 | 413184 | 719 | 0 | 0 |
T8 | 20360 | 98 | 0 | 0 |
T9 | 266150 | 82409 | 0 | 0 |
T10 | 34477 | 47 | 0 | 0 |
T11 | 538030 | 6137 | 0 | 0 |
T12 | 163674 | 14344 | 0 | 0 |
T13 | 412892 | 4066 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 596530 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 596530 | 0 | 0 |
T1 | 4226 | 37 | 0 | 0 |
T2 | 1009 | 1 | 0 | 0 |
T3 | 499471 | 33 | 0 | 0 |
T7 | 413184 | 6 | 0 | 0 |
T8 | 20360 | 84 | 0 | 0 |
T9 | 266150 | 1327 | 0 | 0 |
T10 | 34477 | 49 | 0 | 0 |
T11 | 538030 | 12 | 0 | 0 |
T12 | 163674 | 2952 | 0 | 0 |
T13 | 412892 | 2065 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 549543 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 549543 | 0 | 0 |
T1 | 4226 | 8 | 0 | 0 |
T2 | 1009 | 1 | 0 | 0 |
T3 | 499471 | 30 | 0 | 0 |
T7 | 413184 | 6 | 0 | 0 |
T8 | 20360 | 75 | 0 | 0 |
T9 | 266150 | 9798 | 0 | 0 |
T10 | 34477 | 48 | 0 | 0 |
T11 | 538030 | 388 | 0 | 0 |
T12 | 163674 | 647 | 0 | 0 |
T13 | 412892 | 970 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 12923849 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 12923849 | 0 | 0 |
T1 | 4226 | 196 | 0 | 0 |
T2 | 1009 | 17 | 0 | 0 |
T3 | 499471 | 1111 | 0 | 0 |
T7 | 413184 | 21033 | 0 | 0 |
T8 | 20360 | 1035 | 0 | 0 |
T9 | 266150 | 1998 | 0 | 0 |
T10 | 34477 | 2654 | 0 | 0 |
T11 | 538030 | 47919 | 0 | 0 |
T12 | 163674 | 160941 | 0 | 0 |
T13 | 412892 | 20129 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 19172182 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 19172182 | 0 | 0 |
T1 | 4226 | 125 | 0 | 0 |
T2 | 1009 | 17 | 0 | 0 |
T3 | 499471 | 249 | 0 | 0 |
T7 | 413184 | 21632 | 0 | 0 |
T8 | 20360 | 1035 | 0 | 0 |
T9 | 266150 | 159981 | 0 | 0 |
T10 | 34477 | 2654 | 0 | 0 |
T11 | 538030 | 16429 | 0 | 0 |
T12 | 163674 | 70866 | 0 | 0 |
T13 | 412892 | 11251 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |