Line Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3281868 |
0 |
0 |
T1 |
4226 |
24 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
221 |
0 |
0 |
T7 |
413184 |
931 |
0 |
0 |
T8 |
20360 |
694 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
114 |
0 |
0 |
T11 |
538030 |
8596 |
0 |
0 |
T12 |
163674 |
44343 |
0 |
0 |
T13 |
412892 |
8688 |
0 |
0 |
T15 |
0 |
189 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3281868 |
0 |
0 |
T1 |
4226 |
24 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
221 |
0 |
0 |
T7 |
413184 |
931 |
0 |
0 |
T8 |
20360 |
694 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
114 |
0 |
0 |
T11 |
538030 |
8596 |
0 |
0 |
T12 |
163674 |
44343 |
0 |
0 |
T13 |
412892 |
8688 |
0 |
0 |
T15 |
0 |
189 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T11 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4180548 |
0 |
0 |
T1 |
4226 |
23 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
62 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
694 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
114 |
0 |
0 |
T11 |
538030 |
4536 |
0 |
0 |
T12 |
163674 |
15336 |
0 |
0 |
T13 |
412892 |
5040 |
0 |
0 |
T15 |
0 |
189 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4180548 |
0 |
0 |
T1 |
4226 |
23 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
62 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
694 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
114 |
0 |
0 |
T11 |
538030 |
4536 |
0 |
0 |
T12 |
163674 |
15336 |
0 |
0 |
T13 |
412892 |
5040 |
0 |
0 |
T15 |
0 |
189 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
282833 |
0 |
0 |
T1 |
4226 |
5 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
31 |
0 |
0 |
T7 |
413184 |
0 |
0 |
0 |
T8 |
20360 |
532 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
49 |
0 |
0 |
T11 |
538030 |
12 |
0 |
0 |
T12 |
163674 |
975 |
0 |
0 |
T13 |
412892 |
1049 |
0 |
0 |
T15 |
0 |
118 |
0 |
0 |
T16 |
0 |
401 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3440753 |
0 |
0 |
T1 |
4226 |
23 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
35 |
0 |
0 |
T7 |
413184 |
0 |
0 |
0 |
T8 |
20360 |
354 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
49 |
0 |
0 |
T11 |
538030 |
4168 |
0 |
0 |
T12 |
163674 |
14961 |
0 |
0 |
T13 |
412892 |
3566 |
0 |
0 |
T15 |
0 |
108 |
0 |
0 |
T16 |
0 |
2866 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
376035 |
0 |
0 |
T2 |
1009 |
1 |
0 |
0 |
T3 |
499471 |
29 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
467 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
65 |
0 |
0 |
T11 |
538030 |
666 |
0 |
0 |
T12 |
163674 |
842 |
0 |
0 |
T13 |
412892 |
2748 |
0 |
0 |
T14 |
20007 |
0 |
0 |
0 |
T15 |
0 |
82 |
0 |
0 |
T16 |
0 |
452 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
739795 |
0 |
0 |
T2 |
1009 |
1 |
0 |
0 |
T3 |
499471 |
27 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
340 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
65 |
0 |
0 |
T11 |
538030 |
368 |
0 |
0 |
T12 |
163674 |
375 |
0 |
0 |
T13 |
412892 |
1474 |
0 |
0 |
T14 |
20007 |
0 |
0 |
0 |
T15 |
0 |
81 |
0 |
0 |
T16 |
0 |
433 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3295945 |
0 |
0 |
T1 |
4226 |
44 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
416 |
0 |
0 |
T7 |
413184 |
4605 |
0 |
0 |
T8 |
20360 |
199 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
108 |
0 |
0 |
T11 |
538030 |
13061 |
0 |
0 |
T12 |
163674 |
41710 |
0 |
0 |
T13 |
412892 |
8831 |
0 |
0 |
T15 |
0 |
166 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3295945 |
0 |
0 |
T1 |
4226 |
44 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
416 |
0 |
0 |
T7 |
413184 |
4605 |
0 |
0 |
T8 |
20360 |
199 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
108 |
0 |
0 |
T11 |
538030 |
13061 |
0 |
0 |
T12 |
163674 |
41710 |
0 |
0 |
T13 |
412892 |
8831 |
0 |
0 |
T15 |
0 |
166 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T11,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4104810 |
0 |
0 |
T1 |
4226 |
22 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
74 |
0 |
0 |
T7 |
413184 |
10 |
0 |
0 |
T8 |
20360 |
199 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
108 |
0 |
0 |
T11 |
538030 |
7456 |
0 |
0 |
T12 |
163674 |
14809 |
0 |
0 |
T13 |
412892 |
5696 |
0 |
0 |
T15 |
0 |
166 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4104810 |
0 |
0 |
T1 |
4226 |
22 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
74 |
0 |
0 |
T7 |
413184 |
10 |
0 |
0 |
T8 |
20360 |
199 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
108 |
0 |
0 |
T11 |
538030 |
7456 |
0 |
0 |
T12 |
163674 |
14809 |
0 |
0 |
T13 |
412892 |
5696 |
0 |
0 |
T15 |
0 |
166 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
284625 |
0 |
0 |
T1 |
4226 |
5 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
27 |
0 |
0 |
T7 |
413184 |
3 |
0 |
0 |
T8 |
20360 |
98 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
52 |
0 |
0 |
T11 |
538030 |
353 |
0 |
0 |
T12 |
163674 |
683 |
0 |
0 |
T13 |
412892 |
952 |
0 |
0 |
T15 |
0 |
83 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3417503 |
0 |
0 |
T1 |
4226 |
22 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
22 |
0 |
0 |
T7 |
413184 |
3 |
0 |
0 |
T8 |
20360 |
96 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
51 |
0 |
0 |
T11 |
538030 |
6725 |
0 |
0 |
T12 |
163674 |
14263 |
0 |
0 |
T13 |
412892 |
3802 |
0 |
0 |
T15 |
0 |
79 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
387726 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
74 |
0 |
0 |
T7 |
413184 |
302 |
0 |
0 |
T8 |
20360 |
103 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
59 |
0 |
0 |
T11 |
538030 |
15 |
0 |
0 |
T12 |
163674 |
2423 |
0 |
0 |
T13 |
412892 |
2807 |
0 |
0 |
T14 |
20007 |
0 |
0 |
0 |
T15 |
0 |
93 |
0 |
0 |
T16 |
0 |
432 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
687307 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
52 |
0 |
0 |
T7 |
413184 |
7 |
0 |
0 |
T8 |
20360 |
103 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
57 |
0 |
0 |
T11 |
538030 |
731 |
0 |
0 |
T12 |
163674 |
546 |
0 |
0 |
T13 |
412892 |
1894 |
0 |
0 |
T14 |
20007 |
0 |
0 |
0 |
T15 |
0 |
87 |
0 |
0 |
T16 |
0 |
478 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3200457 |
0 |
0 |
T1 |
4226 |
89 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
293 |
0 |
0 |
T7 |
413184 |
2761 |
0 |
0 |
T8 |
20360 |
172 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
558 |
0 |
0 |
T11 |
538030 |
13917 |
0 |
0 |
T12 |
163674 |
37632 |
0 |
0 |
T13 |
412892 |
3722 |
0 |
0 |
T15 |
0 |
203 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3200457 |
0 |
0 |
T1 |
4226 |
89 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
293 |
0 |
0 |
T7 |
413184 |
2761 |
0 |
0 |
T8 |
20360 |
172 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
558 |
0 |
0 |
T11 |
538030 |
13917 |
0 |
0 |
T12 |
163674 |
37632 |
0 |
0 |
T13 |
412892 |
3722 |
0 |
0 |
T15 |
0 |
203 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3531435 |
0 |
0 |
T1 |
4226 |
35 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
68 |
0 |
0 |
T7 |
413184 |
1164 |
0 |
0 |
T8 |
20360 |
172 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
558 |
0 |
0 |
T11 |
538030 |
9865 |
0 |
0 |
T12 |
163674 |
16578 |
0 |
0 |
T13 |
412892 |
2280 |
0 |
0 |
T15 |
0 |
203 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3531435 |
0 |
0 |
T1 |
4226 |
35 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
68 |
0 |
0 |
T7 |
413184 |
1164 |
0 |
0 |
T8 |
20360 |
172 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
558 |
0 |
0 |
T11 |
538030 |
9865 |
0 |
0 |
T12 |
163674 |
16578 |
0 |
0 |
T13 |
412892 |
2280 |
0 |
0 |
T15 |
0 |
203 |
0 |
0 |