Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
277427 |
0 |
0 |
T1 |
4226 |
3 |
0 |
0 |
T2 |
1009 |
1 |
0 |
0 |
T3 |
499471 |
40 |
0 |
0 |
T7 |
413184 |
313 |
0 |
0 |
T8 |
20360 |
83 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
966 |
0 |
0 |
T11 |
538030 |
406 |
0 |
0 |
T12 |
163674 |
272 |
0 |
0 |
T13 |
412892 |
289 |
0 |
0 |
T15 |
0 |
126 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
2911781 |
0 |
0 |
T1 |
4226 |
27 |
0 |
0 |
T2 |
1009 |
1 |
0 |
0 |
T3 |
499471 |
35 |
0 |
0 |
T7 |
413184 |
1160 |
0 |
0 |
T8 |
20360 |
78 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
300 |
0 |
0 |
T11 |
538030 |
9308 |
0 |
0 |
T12 |
163674 |
16521 |
0 |
0 |
T13 |
412892 |
1945 |
0 |
0 |
T15 |
0 |
115 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
358483 |
0 |
0 |
T1 |
4226 |
8 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
39 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
97 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
673 |
0 |
0 |
T11 |
538030 |
659 |
0 |
0 |
T12 |
163674 |
1146 |
0 |
0 |
T13 |
412892 |
254 |
0 |
0 |
T15 |
0 |
90 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
619654 |
0 |
0 |
T1 |
4226 |
8 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
33 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
94 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
258 |
0 |
0 |
T11 |
538030 |
557 |
0 |
0 |
T12 |
163674 |
57 |
0 |
0 |
T13 |
412892 |
335 |
0 |
0 |
T15 |
0 |
88 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3261198 |
0 |
0 |
T1 |
4226 |
16 |
0 |
0 |
T2 |
1009 |
9 |
0 |
0 |
T3 |
499471 |
368 |
0 |
0 |
T7 |
413184 |
3789 |
0 |
0 |
T8 |
20360 |
184 |
0 |
0 |
T9 |
266150 |
2251 |
0 |
0 |
T10 |
34477 |
119 |
0 |
0 |
T11 |
538030 |
10742 |
0 |
0 |
T12 |
163674 |
37198 |
0 |
0 |
T13 |
412892 |
3387 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3261198 |
0 |
0 |
T1 |
4226 |
16 |
0 |
0 |
T2 |
1009 |
9 |
0 |
0 |
T3 |
499471 |
368 |
0 |
0 |
T7 |
413184 |
3789 |
0 |
0 |
T8 |
20360 |
184 |
0 |
0 |
T9 |
266150 |
2251 |
0 |
0 |
T10 |
34477 |
119 |
0 |
0 |
T11 |
538030 |
10742 |
0 |
0 |
T12 |
163674 |
37198 |
0 |
0 |
T13 |
412892 |
3387 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T7,T9 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4216277 |
0 |
0 |
T1 |
4226 |
9 |
0 |
0 |
T2 |
1009 |
9 |
0 |
0 |
T3 |
499471 |
74 |
0 |
0 |
T7 |
413184 |
503 |
0 |
0 |
T8 |
20360 |
183 |
0 |
0 |
T9 |
266150 |
93049 |
0 |
0 |
T10 |
34477 |
119 |
0 |
0 |
T11 |
538030 |
7104 |
0 |
0 |
T12 |
163674 |
12457 |
0 |
0 |
T13 |
412892 |
1908 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4216277 |
0 |
0 |
T1 |
4226 |
9 |
0 |
0 |
T2 |
1009 |
9 |
0 |
0 |
T3 |
499471 |
74 |
0 |
0 |
T7 |
413184 |
503 |
0 |
0 |
T8 |
20360 |
183 |
0 |
0 |
T9 |
266150 |
93049 |
0 |
0 |
T10 |
34477 |
119 |
0 |
0 |
T11 |
538030 |
7104 |
0 |
0 |
T12 |
163674 |
12457 |
0 |
0 |
T13 |
412892 |
1908 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
271853 |
0 |
0 |
T1 |
4226 |
1 |
0 |
0 |
T2 |
1009 |
7 |
0 |
0 |
T3 |
499471 |
38 |
0 |
0 |
T7 |
413184 |
5 |
0 |
0 |
T8 |
20360 |
106 |
0 |
0 |
T9 |
266150 |
722 |
0 |
0 |
T10 |
34477 |
58 |
0 |
0 |
T11 |
538030 |
13 |
0 |
0 |
T12 |
163674 |
49 |
0 |
0 |
T13 |
412892 |
215 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3509356 |
0 |
0 |
T1 |
4226 |
8 |
0 |
0 |
T2 |
1009 |
6 |
0 |
0 |
T3 |
499471 |
34 |
0 |
0 |
T7 |
413184 |
494 |
0 |
0 |
T8 |
20360 |
101 |
0 |
0 |
T9 |
266150 |
78394 |
0 |
0 |
T10 |
34477 |
53 |
0 |
0 |
T11 |
538030 |
5391 |
0 |
0 |
T12 |
163674 |
12277 |
0 |
0 |
T13 |
412892 |
1591 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
364861 |
0 |
0 |
T1 |
4226 |
1 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
43 |
0 |
0 |
T7 |
413184 |
119 |
0 |
0 |
T8 |
20360 |
82 |
0 |
0 |
T9 |
266150 |
925 |
0 |
0 |
T10 |
34477 |
67 |
0 |
0 |
T11 |
538030 |
48 |
0 |
0 |
T12 |
163674 |
561 |
0 |
0 |
T13 |
412892 |
299 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
706921 |
0 |
0 |
T1 |
4226 |
1 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
40 |
0 |
0 |
T7 |
413184 |
9 |
0 |
0 |
T8 |
20360 |
82 |
0 |
0 |
T9 |
266150 |
14655 |
0 |
0 |
T10 |
34477 |
66 |
0 |
0 |
T11 |
538030 |
1713 |
0 |
0 |
T12 |
163674 |
180 |
0 |
0 |
T13 |
412892 |
317 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3242521 |
0 |
0 |
T1 |
4226 |
47 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
251 |
0 |
0 |
T7 |
413184 |
3062 |
0 |
0 |
T8 |
20360 |
201 |
0 |
0 |
T9 |
266150 |
7024 |
0 |
0 |
T10 |
34477 |
115 |
0 |
0 |
T11 |
538030 |
12410 |
0 |
0 |
T12 |
163674 |
41797 |
0 |
0 |
T13 |
412892 |
8107 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3242521 |
0 |
0 |
T1 |
4226 |
47 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
251 |
0 |
0 |
T7 |
413184 |
3062 |
0 |
0 |
T8 |
20360 |
201 |
0 |
0 |
T9 |
266150 |
7024 |
0 |
0 |
T10 |
34477 |
115 |
0 |
0 |
T11 |
538030 |
12410 |
0 |
0 |
T12 |
163674 |
41797 |
0 |
0 |
T13 |
412892 |
8107 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4503242 |
0 |
0 |
T1 |
4226 |
15 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
321 |
0 |
0 |
T7 |
413184 |
167 |
0 |
0 |
T8 |
20360 |
201 |
0 |
0 |
T9 |
266150 |
289771 |
0 |
0 |
T10 |
34477 |
115 |
0 |
0 |
T11 |
538030 |
5152 |
0 |
0 |
T12 |
163674 |
19522 |
0 |
0 |
T13 |
412892 |
5232 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4503242 |
0 |
0 |
T1 |
4226 |
15 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
321 |
0 |
0 |
T7 |
413184 |
167 |
0 |
0 |
T8 |
20360 |
201 |
0 |
0 |
T9 |
266150 |
289771 |
0 |
0 |
T10 |
34477 |
115 |
0 |
0 |
T11 |
538030 |
5152 |
0 |
0 |
T12 |
163674 |
19522 |
0 |
0 |
T13 |
412892 |
5232 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
263100 |
0 |
0 |
T1 |
4226 |
4 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
33 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
109 |
0 |
0 |
T9 |
266150 |
2238 |
0 |
0 |
T10 |
34477 |
65 |
0 |
0 |
T11 |
538030 |
20 |
0 |
0 |
T12 |
163674 |
551 |
0 |
0 |
T13 |
412892 |
905 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3765871 |
0 |
0 |
T1 |
4226 |
11 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
289 |
0 |
0 |
T7 |
413184 |
161 |
0 |
0 |
T8 |
20360 |
103 |
0 |
0 |
T9 |
266150 |
254118 |
0 |
0 |
T10 |
34477 |
65 |
0 |
0 |
T11 |
538030 |
4955 |
0 |
0 |
T12 |
163674 |
19460 |
0 |
0 |
T13 |
412892 |
4144 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |