Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
352155 |
0 |
0 |
T1 |
4226 |
4 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
35 |
0 |
0 |
T7 |
413184 |
6 |
0 |
0 |
T8 |
20360 |
100 |
0 |
0 |
T9 |
266150 |
2633 |
0 |
0 |
T10 |
34477 |
50 |
0 |
0 |
T11 |
538030 |
70 |
0 |
0 |
T12 |
163674 |
1459 |
0 |
0 |
T13 |
412892 |
1672 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
737371 |
0 |
0 |
T1 |
4226 |
4 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
32 |
0 |
0 |
T7 |
413184 |
6 |
0 |
0 |
T8 |
20360 |
98 |
0 |
0 |
T9 |
266150 |
35653 |
0 |
0 |
T10 |
34477 |
50 |
0 |
0 |
T11 |
538030 |
197 |
0 |
0 |
T12 |
163674 |
62 |
0 |
0 |
T13 |
412892 |
1088 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3255561 |
0 |
0 |
T1 |
4226 |
30 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
287 |
0 |
0 |
T7 |
413184 |
2400 |
0 |
0 |
T8 |
20360 |
189 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
95 |
0 |
0 |
T11 |
538030 |
8583 |
0 |
0 |
T12 |
163674 |
42089 |
0 |
0 |
T13 |
412892 |
7263 |
0 |
0 |
T15 |
0 |
181 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3255561 |
0 |
0 |
T1 |
4226 |
30 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
287 |
0 |
0 |
T7 |
413184 |
2400 |
0 |
0 |
T8 |
20360 |
189 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
95 |
0 |
0 |
T11 |
538030 |
8583 |
0 |
0 |
T12 |
163674 |
42089 |
0 |
0 |
T13 |
412892 |
7263 |
0 |
0 |
T15 |
0 |
181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4103431 |
0 |
0 |
T1 |
4226 |
30 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
1545 |
0 |
0 |
T7 |
413184 |
352 |
0 |
0 |
T8 |
20360 |
189 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
95 |
0 |
0 |
T11 |
538030 |
5279 |
0 |
0 |
T12 |
163674 |
20553 |
0 |
0 |
T13 |
412892 |
5786 |
0 |
0 |
T15 |
0 |
181 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
4103431 |
0 |
0 |
T1 |
4226 |
30 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
1545 |
0 |
0 |
T7 |
413184 |
352 |
0 |
0 |
T8 |
20360 |
189 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
95 |
0 |
0 |
T11 |
538030 |
5279 |
0 |
0 |
T12 |
163674 |
20553 |
0 |
0 |
T13 |
412892 |
5786 |
0 |
0 |
T15 |
0 |
181 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
282168 |
0 |
0 |
T1 |
4226 |
4 |
0 |
0 |
T2 |
1009 |
1 |
0 |
0 |
T3 |
499471 |
32 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
94 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
48 |
0 |
0 |
T11 |
538030 |
351 |
0 |
0 |
T12 |
163674 |
62 |
0 |
0 |
T13 |
412892 |
755 |
0 |
0 |
T15 |
0 |
112 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3395529 |
0 |
0 |
T1 |
4226 |
30 |
0 |
0 |
T2 |
1009 |
1 |
0 |
0 |
T3 |
499471 |
1516 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
87 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
48 |
0 |
0 |
T11 |
538030 |
4768 |
0 |
0 |
T12 |
163674 |
20497 |
0 |
0 |
T13 |
412892 |
4440 |
0 |
0 |
T15 |
0 |
101 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
379961 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
32 |
0 |
0 |
T7 |
413184 |
3 |
0 |
0 |
T8 |
20360 |
105 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
48 |
0 |
0 |
T11 |
538030 |
10 |
0 |
0 |
T12 |
163674 |
507 |
0 |
0 |
T13 |
412892 |
885 |
0 |
0 |
T14 |
20007 |
0 |
0 |
0 |
T15 |
0 |
80 |
0 |
0 |
T16 |
0 |
397 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
707902 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
29 |
0 |
0 |
T7 |
413184 |
348 |
0 |
0 |
T8 |
20360 |
102 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
47 |
0 |
0 |
T11 |
538030 |
511 |
0 |
0 |
T12 |
163674 |
56 |
0 |
0 |
T13 |
412892 |
1346 |
0 |
0 |
T14 |
20007 |
0 |
0 |
0 |
T15 |
0 |
80 |
0 |
0 |
T16 |
0 |
480 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3303925 |
0 |
0 |
T1 |
4226 |
72 |
0 |
0 |
T2 |
1009 |
7 |
0 |
0 |
T3 |
499471 |
372 |
0 |
0 |
T7 |
413184 |
2357 |
0 |
0 |
T8 |
20360 |
195 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
663 |
0 |
0 |
T11 |
538030 |
8008 |
0 |
0 |
T12 |
163674 |
36624 |
0 |
0 |
T13 |
412892 |
4631 |
0 |
0 |
T15 |
0 |
187 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3303925 |
0 |
0 |
T1 |
4226 |
72 |
0 |
0 |
T2 |
1009 |
7 |
0 |
0 |
T3 |
499471 |
372 |
0 |
0 |
T7 |
413184 |
2357 |
0 |
0 |
T8 |
20360 |
195 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
663 |
0 |
0 |
T11 |
538030 |
8008 |
0 |
0 |
T12 |
163674 |
36624 |
0 |
0 |
T13 |
412892 |
4631 |
0 |
0 |
T15 |
0 |
187 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T7,T11 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3572430 |
0 |
0 |
T1 |
4226 |
41 |
0 |
0 |
T2 |
1009 |
7 |
0 |
0 |
T3 |
499471 |
87 |
0 |
0 |
T7 |
413184 |
363 |
0 |
0 |
T8 |
20360 |
195 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
663 |
0 |
0 |
T11 |
538030 |
5751 |
0 |
0 |
T12 |
163674 |
17398 |
0 |
0 |
T13 |
412892 |
2846 |
0 |
0 |
T15 |
0 |
187 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3572430 |
0 |
0 |
T1 |
4226 |
41 |
0 |
0 |
T2 |
1009 |
7 |
0 |
0 |
T3 |
499471 |
87 |
0 |
0 |
T7 |
413184 |
363 |
0 |
0 |
T8 |
20360 |
195 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
663 |
0 |
0 |
T11 |
538030 |
5751 |
0 |
0 |
T12 |
163674 |
17398 |
0 |
0 |
T13 |
412892 |
2846 |
0 |
0 |
T15 |
0 |
187 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
282490 |
0 |
0 |
T1 |
4226 |
7 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
42 |
0 |
0 |
T7 |
413184 |
5 |
0 |
0 |
T8 |
20360 |
91 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
1028 |
0 |
0 |
T11 |
538030 |
16 |
0 |
0 |
T12 |
163674 |
692 |
0 |
0 |
T13 |
412892 |
335 |
0 |
0 |
T15 |
0 |
118 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
2924742 |
0 |
0 |
T1 |
4226 |
40 |
0 |
0 |
T2 |
1009 |
3 |
0 |
0 |
T3 |
499471 |
41 |
0 |
0 |
T7 |
413184 |
360 |
0 |
0 |
T8 |
20360 |
87 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
335 |
0 |
0 |
T11 |
538030 |
5296 |
0 |
0 |
T12 |
163674 |
17256 |
0 |
0 |
T13 |
412892 |
2383 |
0 |
0 |
T15 |
0 |
106 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
362312 |
0 |
0 |
T1 |
4226 |
1 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
66 |
0 |
0 |
T7 |
413184 |
3 |
0 |
0 |
T8 |
20360 |
109 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
772 |
0 |
0 |
T11 |
538030 |
336 |
0 |
0 |
T12 |
163674 |
2382 |
0 |
0 |
T13 |
412892 |
368 |
0 |
0 |
T15 |
0 |
82 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
647688 |
0 |
0 |
T1 |
4226 |
1 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
46 |
0 |
0 |
T7 |
413184 |
3 |
0 |
0 |
T8 |
20360 |
108 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
328 |
0 |
0 |
T11 |
538030 |
455 |
0 |
0 |
T12 |
163674 |
142 |
0 |
0 |
T13 |
412892 |
463 |
0 |
0 |
T15 |
0 |
81 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |