Unified Coverage Report :: Module Instance :: tb.dut.u_sm1_52.u_devicefifo.reqfifo

Module Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3234405	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	3234405	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3234405	0	0
T1	4226	39	0	0
T2	1009	7	0	0
T3	499471	291	0	0
T7	413184	1271	0	0
T8	20360	195	0	0
T9	266150	2479	0	0
T10	34477	1610	0	0
T11	538030	6111	0	0
T12	163674	50291	0	0
T13	412892	4026	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3234405	0	0
T1	4226	39	0	0
T2	1009	7	0	0
T3	499471	291	0	0
T7	413184	1271	0	0
T8	20360	195	0	0
T9	266150	2479	0	0
T10	34477	1610	0	0
T11	538030	6111	0	0
T12	163674	50291	0	0
T13	412892	4026	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	4368316	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	4368316	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	4368316	0	0
T1	4226	51	0	0
T2	1009	7	0	0
T3	499471	573	0	0
T7	413184	988	0	0
T8	20360	195	0	0
T9	266150	101320	0	0
T10	34477	1610	0	0
T11	538030	5346	0	0
T12	163674	15419	0	0
T13	412892	2226	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	4368316	0	0
T1	4226	51	0	0
T2	1009	7	0	0
T3	499471	573	0	0
T7	413184	988	0	0
T8	20360	195	0	0
T9	266150	101320	0	0
T10	34477	1610	0	0
T11	538030	5346	0	0
T12	163674	15419	0	0
T13	412892	2226	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	291137	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	291137	0	0
T1	4226	6	0	0
T2	1009	0	0	0
T3	499471	52	0	0
T7	413184	3	0	0
T8	20360	103	0	0
T9	266150	808	0	0
T10	34477	1778	0	0
T11	538030	117	0	0
T12	163674	818	0	0
T13	412892	285	0	0
T15	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3635299	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3635299	0	0
T1	4226	50	0	0
T2	1009	0	0	0
T3	499471	539	0	0
T7	413184	925	0	0
T8	20360	95	0	0
T9	266150	85635	0	0
T10	34477	780	0	0
T11	538030	4860	0	0
T12	163674	14811	0	0
T13	412892	1953	0	0
T15	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	360714	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	360714	0	0
T1	4226	1	0	0
T2	1009	7	0	0
T3	499471	34	0	0
T7	413184	6	0	0
T8	20360	101	0	0
T9	266150	915	0	0
T10	34477	1568	0	0
T11	538030	9	0	0
T12	163674	897	0	0
T13	412892	331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	733017	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	733017	0	0
T1	4226	1	0	0
T2	1009	7	0	0
T3	499471	34	0	0
T7	413184	63	0	0
T8	20360	100	0	0
T9	266150	15685	0	0
T10	34477	830	0	0
T11	538030	486	0	0
T12	163674	608	0	0
T13	412892	273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3261086	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	3261086	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3261086	0	0
T1	4226	27	0	0
T2	1009	6	0	0
T3	499471	366	0	0
T7	413184	2545	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	14819	0	0
T12	163674	33987	0	0
T13	412892	3788	0	0
T14	0	906	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3261086	0	0
T1	4226	27	0	0
T2	1009	6	0	0
T3	499471	366	0	0
T7	413184	2545	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	14819	0	0
T12	163674	33987	0	0
T13	412892	3788	0	0
T14	0	906	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T7,T11
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3595597	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	3595597	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3595597	0	0
T1	4226	36	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	141	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	7259	0	0
T12	163674	16426	0	0
T13	412892	2004	0	0
T14	0	906	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3595597	0	0
T1	4226	36	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	141	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	7259	0	0
T12	163674	16426	0	0
T13	412892	2004	0	0
T14	0	906	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	269879	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	269879	0	0
T1	4226	2	0	0
T2	1009	4	0	0
T3	499471	29	0	0
T7	413184	6	0	0
T8	20360	94	0	0
T9	266150	0	0	0
T10	34477	50	0	0
T11	538030	343	0	0
T12	163674	479	0	0
T13	412892	249	0	0
T14	0	1667	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	2993154	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2993154	0	0
T1	4226	32	0	0
T2	1009	4	0	0
T3	499471	29	0	0
T7	413184	136	0	0
T8	20360	92	0	0
T9	266150	0	0	0
T10	34477	48	0	0
T11	538030	6210	0	0
T12	163674	16066	0	0
T13	412892	1678	0	0
T14	0	419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	352627	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	352627	0	0
T1	4226	9	0	0
T2	1009	2	0	0
T3	499471	61	0	0
T7	413184	686	0	0
T8	20360	76	0	0
T9	266150	0	0	0
T10	34477	49	0	0
T11	538030	320	0	0
T12	163674	250	0	0
T13	412892	255	0	0
T14	0	1320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	602443	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	602443	0	0
T1	4226	4	0	0
T2	1009	2	0	0
T3	499471	43	0	0
T7	413184	5	0	0
T8	20360	74	0	0
T9	266150	0	0	0
T10	34477	49	0	0
T11	538030	1049	0	0
T12	163674	360	0	0
T13	412892	326	0	0
T14	0	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3294480	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	3294480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3294480	0	0
T1	4226	37	0	0
T2	1009	4	0	0
T3	499471	332	0	0
T7	413184	1671	0	0
T8	20360	181	0	0
T9	266150	2261	0	0
T10	34477	600	0	0
T11	538030	16717	0	0
T12	163674	51625	0	0
T13	412892	3476	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3294480	0	0
T1	4226	37	0	0
T2	1009	4	0	0
T3	499471	332	0	0
T7	413184	1671	0	0
T8	20360	181	0	0
T9	266150	2261	0	0
T10	34477	600	0	0
T11	538030	16717	0	0
T12	163674	51625	0	0
T13	412892	3476	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T9,T11
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3831495	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	403733496	3831495	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3831495	0	0
T1	4226	21	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	93105	0	0
T10	34477	600	0	0
T11	538030	12348	0	0
T12	163674	27430	0	0
T13	412892	1947	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3831495	0	0
T1	4226	21	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	93105	0	0
T10	34477	600	0	0
T11	538030	12348	0	0
T12	163674	27430	0	0
T13	412892	1947	0	0