Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
266325 |
0 |
0 |
T1 |
4226 |
3 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
38 |
0 |
0 |
T7 |
413184 |
2 |
0 |
0 |
T8 |
20360 |
98 |
0 |
0 |
T9 |
266150 |
775 |
0 |
0 |
T10 |
34477 |
1033 |
0 |
0 |
T11 |
538030 |
631 |
0 |
0 |
T12 |
163674 |
1846 |
0 |
0 |
T13 |
412892 |
209 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3232490 |
0 |
0 |
T1 |
4226 |
19 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
35 |
0 |
0 |
T7 |
413184 |
2 |
0 |
0 |
T8 |
20360 |
97 |
0 |
0 |
T9 |
266150 |
84018 |
0 |
0 |
T10 |
34477 |
336 |
0 |
0 |
T11 |
538030 |
11287 |
0 |
0 |
T12 |
163674 |
27184 |
0 |
0 |
T13 |
412892 |
1620 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
333525 |
0 |
0 |
T1 |
4226 |
2 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
49 |
0 |
0 |
T7 |
413184 |
156 |
0 |
0 |
T8 |
20360 |
88 |
0 |
0 |
T9 |
266150 |
847 |
0 |
0 |
T10 |
34477 |
675 |
0 |
0 |
T11 |
538030 |
1481 |
0 |
0 |
T12 |
163674 |
2168 |
0 |
0 |
T13 |
412892 |
317 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
599005 |
0 |
0 |
T1 |
4226 |
2 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
43 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
84 |
0 |
0 |
T9 |
266150 |
9087 |
0 |
0 |
T10 |
34477 |
264 |
0 |
0 |
T11 |
538030 |
1061 |
0 |
0 |
T12 |
163674 |
246 |
0 |
0 |
T13 |
412892 |
327 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3260319 |
0 |
0 |
T1 |
4226 |
79 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
338 |
0 |
0 |
T7 |
413184 |
2114 |
0 |
0 |
T8 |
20360 |
184 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
110 |
0 |
0 |
T11 |
538030 |
11215 |
0 |
0 |
T12 |
163674 |
41573 |
0 |
0 |
T13 |
412892 |
3666 |
0 |
0 |
T14 |
0 |
476 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3260319 |
0 |
0 |
T1 |
4226 |
79 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
338 |
0 |
0 |
T7 |
413184 |
2114 |
0 |
0 |
T8 |
20360 |
184 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
110 |
0 |
0 |
T11 |
538030 |
11215 |
0 |
0 |
T12 |
163674 |
41573 |
0 |
0 |
T13 |
412892 |
3666 |
0 |
0 |
T14 |
0 |
476 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T7,T11 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3836659 |
0 |
0 |
T1 |
4226 |
28 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
77 |
0 |
0 |
T7 |
413184 |
540 |
0 |
0 |
T8 |
20360 |
183 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
110 |
0 |
0 |
T11 |
538030 |
6299 |
0 |
0 |
T12 |
163674 |
19711 |
0 |
0 |
T13 |
412892 |
2289 |
0 |
0 |
T14 |
0 |
476 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3836659 |
0 |
0 |
T1 |
4226 |
28 |
0 |
0 |
T2 |
1009 |
8 |
0 |
0 |
T3 |
499471 |
77 |
0 |
0 |
T7 |
413184 |
540 |
0 |
0 |
T8 |
20360 |
183 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
110 |
0 |
0 |
T11 |
538030 |
6299 |
0 |
0 |
T12 |
163674 |
19711 |
0 |
0 |
T13 |
412892 |
2289 |
0 |
0 |
T14 |
0 |
476 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
270153 |
0 |
0 |
T1 |
4226 |
2 |
0 |
0 |
T2 |
1009 |
5 |
0 |
0 |
T3 |
499471 |
39 |
0 |
0 |
T7 |
413184 |
3 |
0 |
0 |
T8 |
20360 |
106 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
53 |
0 |
0 |
T11 |
538030 |
473 |
0 |
0 |
T12 |
163674 |
197 |
0 |
0 |
T13 |
412892 |
262 |
0 |
0 |
T14 |
0 |
951 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3196827 |
0 |
0 |
T1 |
4226 |
19 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
39 |
0 |
0 |
T7 |
413184 |
148 |
0 |
0 |
T8 |
20360 |
100 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
51 |
0 |
0 |
T11 |
538030 |
5945 |
0 |
0 |
T12 |
163674 |
19641 |
0 |
0 |
T13 |
412892 |
1944 |
0 |
0 |
T14 |
0 |
246 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
348485 |
0 |
0 |
T1 |
4226 |
9 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
47 |
0 |
0 |
T7 |
413184 |
4 |
0 |
0 |
T8 |
20360 |
86 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
59 |
0 |
0 |
T11 |
538030 |
189 |
0 |
0 |
T12 |
163674 |
1922 |
0 |
0 |
T13 |
412892 |
294 |
0 |
0 |
T14 |
0 |
689 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
639832 |
0 |
0 |
T1 |
4226 |
9 |
0 |
0 |
T2 |
1009 |
4 |
0 |
0 |
T3 |
499471 |
38 |
0 |
0 |
T7 |
413184 |
392 |
0 |
0 |
T8 |
20360 |
83 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
59 |
0 |
0 |
T11 |
538030 |
354 |
0 |
0 |
T12 |
163674 |
70 |
0 |
0 |
T13 |
412892 |
345 |
0 |
0 |
T14 |
0 |
230 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3283571 |
0 |
0 |
T1 |
4226 |
67 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
343 |
0 |
0 |
T7 |
413184 |
1143 |
0 |
0 |
T8 |
20360 |
622 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
638 |
0 |
0 |
T11 |
538030 |
13268 |
0 |
0 |
T12 |
163674 |
29368 |
0 |
0 |
T13 |
412892 |
6754 |
0 |
0 |
T15 |
0 |
179 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3283571 |
0 |
0 |
T1 |
4226 |
67 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
343 |
0 |
0 |
T7 |
413184 |
1143 |
0 |
0 |
T8 |
20360 |
622 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
638 |
0 |
0 |
T11 |
538030 |
13268 |
0 |
0 |
T12 |
163674 |
29368 |
0 |
0 |
T13 |
412892 |
6754 |
0 |
0 |
T15 |
0 |
179 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T7,T11 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3928754 |
0 |
0 |
T1 |
4226 |
21 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
81 |
0 |
0 |
T7 |
413184 |
692 |
0 |
0 |
T8 |
20360 |
622 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
638 |
0 |
0 |
T11 |
538030 |
9737 |
0 |
0 |
T12 |
163674 |
11809 |
0 |
0 |
T13 |
412892 |
5264 |
0 |
0 |
T15 |
0 |
179 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3928754 |
0 |
0 |
T1 |
4226 |
21 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
81 |
0 |
0 |
T7 |
413184 |
692 |
0 |
0 |
T8 |
20360 |
622 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
638 |
0 |
0 |
T11 |
538030 |
9737 |
0 |
0 |
T12 |
163674 |
11809 |
0 |
0 |
T13 |
412892 |
5264 |
0 |
0 |
T15 |
0 |
179 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
304808 |
0 |
0 |
T1 |
4226 |
4 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
55 |
0 |
0 |
T7 |
413184 |
3 |
0 |
0 |
T8 |
20360 |
370 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
1101 |
0 |
0 |
T11 |
538030 |
299 |
0 |
0 |
T12 |
163674 |
124 |
0 |
0 |
T13 |
412892 |
650 |
0 |
0 |
T15 |
0 |
94 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
3261990 |
0 |
0 |
T1 |
4226 |
19 |
0 |
0 |
T2 |
1009 |
2 |
0 |
0 |
T3 |
499471 |
45 |
0 |
0 |
T7 |
413184 |
692 |
0 |
0 |
T8 |
20360 |
316 |
0 |
0 |
T9 |
266150 |
0 |
0 |
0 |
T10 |
34477 |
326 |
0 |
0 |
T11 |
538030 |
9362 |
0 |
0 |
T12 |
163674 |
11484 |
0 |
0 |
T13 |
412892 |
3803 |
0 |
0 |
T15 |
0 |
86 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
403733496 |
403619028 |
0 |
0 |
T1 |
4226 |
4176 |
0 |
0 |
T2 |
1009 |
944 |
0 |
0 |
T3 |
499471 |
499454 |
0 |
0 |
T7 |
413184 |
413136 |
0 |
0 |
T8 |
20360 |
19671 |
0 |
0 |
T9 |
266150 |
266147 |
0 |
0 |
T10 |
34477 |
34414 |
0 |
0 |
T11 |
538030 |
537973 |
0 |
0 |
T12 |
163674 |
163670 |
0 |
0 |
T13 |
412892 |
412780 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |