Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	968771	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	968771	0	0
T1	4226	2	0	0
T2	1009	2	0	0
T3	499471	36	0	0
T7	413184	5	0	0
T8	20360	90	0	0
T9	266150	0	0	0
T10	34477	1278	0	0
T11	538030	483	0	0
T12	163674	2951	0	0
T13	412892	271	0	0
T15	0	159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	730639	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	730639	0	0
T1	4226	2	0	0
T2	1009	2	0	0
T3	499471	36	0	0
T7	413184	5	0	0
T8	20360	77	0	0
T9	266150	0	0	0
T10	34477	266	0	0
T11	538030	782	0	0
T12	163674	131	0	0
T13	412892	319	0	0
T15	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	883509	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	883509	0	0
T1	4226	1	0	0
T2	1009	3	0	0
T3	499471	79	0	0
T7	413184	76	0	0
T8	20360	281	0	0
T9	266150	0	0	0
T10	34477	52	0	0
T11	538030	550	0	0
T12	163674	2774	0	0
T13	412892	32659	0	0
T14	0	3654	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	622284	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	622284	0	0
T1	4226	1	0	0
T2	1009	3	0	0
T3	499471	247	0	0
T7	413184	4	0	0
T8	20360	155	0	0
T9	266150	0	0	0
T10	34477	52	0	0
T11	538030	738	0	0
T12	163674	66	0	0
T13	412892	1015	0	0
T14	0	300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	750749	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	750749	0	0
T1	4226	2	0	0
T2	1009	2	0	0
T3	499471	51	0	0
T7	413184	465	0	0
T8	20360	240	0	0
T9	266150	0	0	0
T10	34477	704	0	0
T11	538030	20	0	0
T12	163674	2163	0	0
T13	412892	340	0	0
T15	0	139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	762264	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	762264	0	0
T1	4226	2	0	0
T2	1009	2	0	0
T3	499471	37	0	0
T7	413184	30	0	0
T8	20360	77	0	0
T9	266150	0	0	0
T10	34477	290	0	0
T11	538030	526	0	0
T12	163674	146	0	0
T13	412892	299	0	0
T15	0	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	824777	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	824777	0	0
T1	4226	4	0	0
T2	1009	1	0	0
T3	499471	22	0	0
T7	413184	5	0	0
T8	20360	105	0	0
T9	266150	0	0	0
T10	34477	1305	0	0
T11	538030	549	0	0
T12	163674	3850	0	0
T13	412892	372	0	0
T14	0	7298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	736756	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	736756	0	0
T1	4226	4	0	0
T2	1009	1	0	0
T3	499471	22	0	0
T7	413184	5	0	0
T8	20360	87	0	0
T9	266150	0	0	0
T10	34477	244	0	0
T11	538030	750	0	0
T12	163674	52	0	0
T13	412892	277	0	0
T14	0	220	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	360681	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	360681	0	0
T1	4226	4	0	0
T2	1009	2	0	0
T3	499471	58	0	0
T7	413184	7	0	0
T8	20360	399	0	0
T9	266150	0	0	0
T10	34477	434	0	0
T11	538030	560	0	0
T12	163674	1849	0	0
T13	412892	311	0	0
T14	0	650	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	633657	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	633657	0	0
T1	4226	5	0	0
T2	1009	2	0	0
T3	499471	43	0	0
T7	413184	117	0	0
T8	20360	365	0	0
T9	266150	0	0	0
T10	34477	333	0	0
T11	538030	524	0	0
T12	163674	57	0	0
T13	412892	302	0	0
T14	0	217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	359076	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	359076	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	35	0	0
T7	413184	69	0	0
T8	20360	90	0	0
T9	266150	897	0	0
T10	34477	65	0	0
T11	538030	19	0	0
T12	163674	1428	0	0
T13	412892	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	667088	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	667088	0	0
T1	4226	9	0	0
T2	1009	3	0	0
T3	499471	34	0	0
T7	413184	8	0	0
T8	20360	90	0	0
T9	266150	9482	0	0
T10	34477	65	0	0
T11	538030	264	0	0
T12	163674	175	0	0
T13	412892	331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	558396	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	558396	0	0
T1	4226	19	0	0
T2	1009	8	0	0
T3	499471	56	0	0
T7	413184	126	0	0
T8	20360	90	0	0
T9	266150	0	0	0
T10	34477	61	0	0
T11	538030	536	0	0
T12	163674	3309	0	0
T13	412892	424	0	0
T15	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	553875	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	553875	0	0
T1	4226	5	0	0
T2	1009	6	0	0
T3	499471	34	0	0
T7	413184	9	0	0
T8	20360	77	0	0
T9	266150	0	0	0
T10	34477	55	0	0
T11	538030	425	0	0
T12	163674	295	0	0
T13	412892	351	0	0
T15	0	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0