Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	284625	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	284625	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	27	0	0
T7	413184	3	0	0
T8	20360	98	0	0
T9	266150	0	0	0
T10	34477	52	0	0
T11	538030	353	0	0
T12	163674	683	0	0
T13	412892	952	0	0
T15	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3417503	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3417503	0	0
T1	4226	22	0	0
T2	1009	3	0	0
T3	499471	22	0	0
T7	413184	3	0	0
T8	20360	96	0	0
T9	266150	0	0	0
T10	34477	51	0	0
T11	538030	6725	0	0
T12	163674	14263	0	0
T13	412892	3802	0	0
T15	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	277427	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	277427	0	0
T1	4226	3	0	0
T2	1009	1	0	0
T3	499471	40	0	0
T7	413184	313	0	0
T8	20360	83	0	0
T9	266150	0	0	0
T10	34477	966	0	0
T11	538030	406	0	0
T12	163674	272	0	0
T13	412892	289	0	0
T15	0	126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	2911781	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2911781	0	0
T1	4226	27	0	0
T2	1009	1	0	0
T3	499471	35	0	0
T7	413184	1160	0	0
T8	20360	78	0	0
T9	266150	0	0	0
T10	34477	300	0	0
T11	538030	9308	0	0
T12	163674	16521	0	0
T13	412892	1945	0	0
T15	0	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	271853	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	271853	0	0
T1	4226	1	0	0
T2	1009	7	0	0
T3	499471	38	0	0
T7	413184	5	0	0
T8	20360	106	0	0
T9	266150	722	0	0
T10	34477	58	0	0
T11	538030	13	0	0
T12	163674	49	0	0
T13	412892	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3509356	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3509356	0	0
T1	4226	8	0	0
T2	1009	6	0	0
T3	499471	34	0	0
T7	413184	494	0	0
T8	20360	101	0	0
T9	266150	78394	0	0
T10	34477	53	0	0
T11	538030	5391	0	0
T12	163674	12277	0	0
T13	412892	1591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	263100	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	263100	0	0
T1	4226	4	0	0
T2	1009	2	0	0
T3	499471	33	0	0
T7	413184	4	0	0
T8	20360	109	0	0
T9	266150	2238	0	0
T10	34477	65	0	0
T11	538030	20	0	0
T12	163674	551	0	0
T13	412892	905	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3765871	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3765871	0	0
T1	4226	11	0	0
T2	1009	2	0	0
T3	499471	289	0	0
T7	413184	161	0	0
T8	20360	103	0	0
T9	266150	254118	0	0
T10	34477	65	0	0
T11	538030	4955	0	0
T12	163674	19460	0	0
T13	412892	4144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	282168	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	282168	0	0
T1	4226	4	0	0
T2	1009	1	0	0
T3	499471	32	0	0
T7	413184	4	0	0
T8	20360	94	0	0
T9	266150	0	0	0
T10	34477	48	0	0
T11	538030	351	0	0
T12	163674	62	0	0
T13	412892	755	0	0
T15	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3395529	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3395529	0	0
T1	4226	30	0	0
T2	1009	1	0	0
T3	499471	1516	0	0
T7	413184	4	0	0
T8	20360	87	0	0
T9	266150	0	0	0
T10	34477	48	0	0
T11	538030	4768	0	0
T12	163674	20497	0	0
T13	412892	4440	0	0
T15	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	282490	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	282490	0	0
T1	4226	7	0	0
T2	1009	3	0	0
T3	499471	42	0	0
T7	413184	5	0	0
T8	20360	91	0	0
T9	266150	0	0	0
T10	34477	1028	0	0
T11	538030	16	0	0
T12	163674	692	0	0
T13	412892	335	0	0
T15	0	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	2924742	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2924742	0	0
T1	4226	40	0	0
T2	1009	3	0	0
T3	499471	41	0	0
T7	413184	360	0	0
T8	20360	87	0	0
T9	266150	0	0	0
T10	34477	335	0	0
T11	538030	5296	0	0
T12	163674	17256	0	0
T13	412892	2383	0	0
T15	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	291137	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	291137	0	0
T1	4226	6	0	0
T2	1009	0	0	0
T3	499471	52	0	0
T7	413184	3	0	0
T8	20360	103	0	0
T9	266150	808	0	0
T10	34477	1778	0	0
T11	538030	117	0	0
T12	163674	818	0	0
T13	412892	285	0	0
T15	0	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403733496	3635299	0	0
DepthKnown_A	403733496	403619028	0	0
RvalidKnown_A	403733496	403619028	0	0
WreadyKnown_A	403733496	403619028	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	3635299	0	0
T1	4226	50	0	0
T2	1009	0	0	0
T3	499471	539	0	0
T7	413184	925	0	0
T8	20360	95	0	0
T9	266150	85635	0	0
T10	34477	780	0	0
T11	538030	4860	0	0
T12	163674	14811	0	0
T13	412892	1953	0	0
T15	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0