SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.31 | 100.00 | 81.25 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.57 | 97.50 | 80.56 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.75 | 100.00 | 75.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.88 | 97.50 | 77.78 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 3218609 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 403733496 | 3218609 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3218609 | 0 | 0 |
T1 | 4226 | 36 | 0 | 0 |
T2 | 1009 | 5 | 0 | 0 |
T3 | 499471 | 323 | 0 | 0 |
T7 | 413184 | 4648 | 0 | 0 |
T8 | 20360 | 186 | 0 | 0 |
T9 | 266150 | 2424 | 0 | 0 |
T10 | 34477 | 594 | 0 | 0 |
T11 | 538030 | 10626 | 0 | 0 |
T12 | 163674 | 33194 | 0 | 0 |
T13 | 412892 | 10445 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3218609 | 0 | 0 |
T1 | 4226 | 36 | 0 | 0 |
T2 | 1009 | 5 | 0 | 0 |
T3 | 499471 | 323 | 0 | 0 |
T7 | 413184 | 4648 | 0 | 0 |
T8 | 20360 | 186 | 0 | 0 |
T9 | 266150 | 2424 | 0 | 0 |
T10 | 34477 | 594 | 0 | 0 |
T11 | 538030 | 10626 | 0 | 0 |
T12 | 163674 | 33194 | 0 | 0 |
T13 | 412892 | 10445 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T7,T9 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 3371410 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 403733496 | 3371410 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3371410 | 0 | 0 |
T1 | 4226 | 13 | 0 | 0 |
T2 | 1009 | 5 | 0 | 0 |
T3 | 499471 | 76 | 0 | 0 |
T7 | 413184 | 1054 | 0 | 0 |
T8 | 20360 | 186 | 0 | 0 |
T9 | 266150 | 108622 | 0 | 0 |
T10 | 34477 | 594 | 0 | 0 |
T11 | 538030 | 7107 | 0 | 0 |
T12 | 163674 | 14237 | 0 | 0 |
T13 | 412892 | 8902 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3371410 | 0 | 0 |
T1 | 4226 | 13 | 0 | 0 |
T2 | 1009 | 5 | 0 | 0 |
T3 | 499471 | 76 | 0 | 0 |
T7 | 413184 | 1054 | 0 | 0 |
T8 | 20360 | 186 | 0 | 0 |
T9 | 266150 | 108622 | 0 | 0 |
T10 | 34477 | 594 | 0 | 0 |
T11 | 538030 | 7107 | 0 | 0 |
T12 | 163674 | 14237 | 0 | 0 |
T13 | 412892 | 8902 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 270260 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 270260 | 0 | 0 |
T1 | 4226 | 2 | 0 | 0 |
T2 | 1009 | 1 | 0 | 0 |
T3 | 499471 | 43 | 0 | 0 |
T7 | 413184 | 9 | 0 | 0 |
T8 | 20360 | 99 | 0 | 0 |
T9 | 266150 | 847 | 0 | 0 |
T10 | 34477 | 980 | 0 | 0 |
T11 | 538030 | 63 | 0 | 0 |
T12 | 163674 | 710 | 0 | 0 |
T13 | 412892 | 948 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 2802718 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 2802718 | 0 | 0 |
T1 | 4226 | 10 | 0 | 0 |
T2 | 1009 | 1 | 0 | 0 |
T3 | 499471 | 40 | 0 | 0 |
T7 | 413184 | 945 | 0 | 0 |
T8 | 20360 | 95 | 0 | 0 |
T9 | 266150 | 99012 | 0 | 0 |
T10 | 34477 | 312 | 0 | 0 |
T11 | 538030 | 7092 | 0 | 0 |
T12 | 163674 | 14176 | 0 | 0 |
T13 | 412892 | 5650 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 356171 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 356171 | 0 | 0 |
T1 | 4226 | 3 | 0 | 0 |
T2 | 1009 | 4 | 0 | 0 |
T3 | 499471 | 49 | 0 | 0 |
T7 | 413184 | 4 | 0 | 0 |
T8 | 20360 | 93 | 0 | 0 |
T9 | 266150 | 861 | 0 | 0 |
T10 | 34477 | 715 | 0 | 0 |
T11 | 538030 | 293 | 0 | 0 |
T12 | 163674 | 1408 | 0 | 0 |
T13 | 412892 | 2203 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 568692 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 568692 | 0 | 0 |
T1 | 4226 | 3 | 0 | 0 |
T2 | 1009 | 4 | 0 | 0 |
T3 | 499471 | 36 | 0 | 0 |
T7 | 413184 | 109 | 0 | 0 |
T8 | 20360 | 91 | 0 | 0 |
T9 | 266150 | 9610 | 0 | 0 |
T10 | 34477 | 282 | 0 | 0 |
T11 | 538030 | 15 | 0 | 0 |
T12 | 163674 | 61 | 0 | 0 |
T13 | 412892 | 3252 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 1405467 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 1405467 | 0 | 0 |
T1 | 4226 | 4 | 0 | 0 |
T2 | 1009 | 3 | 0 | 0 |
T3 | 499471 | 115 | 0 | 0 |
T7 | 413184 | 630 | 0 | 0 |
T8 | 20360 | 299 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 2408 | 0 | 0 |
T11 | 538030 | 502 | 0 | 0 |
T12 | 163674 | 4434 | 0 | 0 |
T13 | 412892 | 558 | 0 | 0 |
T15 | 0 | 400 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 4511369 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 4511369 | 0 | 0 |
T1 | 4226 | 13 | 0 | 0 |
T2 | 1009 | 3 | 0 | 0 |
T3 | 499471 | 84 | 0 | 0 |
T7 | 413184 | 7 | 0 | 0 |
T8 | 20360 | 167 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 587 | 0 | 0 |
T11 | 538030 | 7389 | 0 | 0 |
T12 | 163674 | 16524 | 0 | 0 |
T13 | 412892 | 2247 | 0 | 0 |
T15 | 0 | 178 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 865916 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 865916 | 0 | 0 |
T1 | 4226 | 2 | 0 | 0 |
T2 | 1009 | 1 | 0 | 0 |
T3 | 499471 | 79 | 0 | 0 |
T7 | 413184 | 625 | 0 | 0 |
T8 | 20360 | 209 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 1796 | 0 | 0 |
T11 | 538030 | 19 | 0 | 0 |
T12 | 163674 | 2323 | 0 | 0 |
T13 | 412892 | 287 | 0 | 0 |
T15 | 0 | 263 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 3780730 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3780730 | 0 | 0 |
T1 | 4226 | 11 | 0 | 0 |
T2 | 1009 | 1 | 0 | 0 |
T3 | 499471 | 48 | 0 | 0 |
T7 | 413184 | 2 | 0 | 0 |
T8 | 20360 | 90 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 321 | 0 | 0 |
T11 | 538030 | 6607 | 0 | 0 |
T12 | 163674 | 16393 | 0 | 0 |
T13 | 412892 | 1928 | 0 | 0 |
T15 | 0 | 104 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 968771 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 968771 | 0 | 0 |
T1 | 4226 | 2 | 0 | 0 |
T2 | 1009 | 2 | 0 | 0 |
T3 | 499471 | 36 | 0 | 0 |
T7 | 413184 | 5 | 0 | 0 |
T8 | 20360 | 90 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 1278 | 0 | 0 |
T11 | 538030 | 483 | 0 | 0 |
T12 | 163674 | 2951 | 0 | 0 |
T13 | 412892 | 271 | 0 | 0 |
T15 | 0 | 159 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 730639 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 730639 | 0 | 0 |
T1 | 4226 | 2 | 0 | 0 |
T2 | 1009 | 2 | 0 | 0 |
T3 | 499471 | 36 | 0 | 0 |
T7 | 413184 | 5 | 0 | 0 |
T8 | 20360 | 77 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 266 | 0 | 0 |
T11 | 538030 | 782 | 0 | 0 |
T12 | 163674 | 131 | 0 | 0 |
T13 | 412892 | 319 | 0 | 0 |
T15 | 0 | 74 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 1222669 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 1222669 | 0 | 0 |
T1 | 4226 | 3 | 0 | 0 |
T2 | 1009 | 3 | 0 | 0 |
T3 | 499471 | 107 | 0 | 0 |
T7 | 413184 | 79 | 0 | 0 |
T8 | 20360 | 620 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 122 | 0 | 0 |
T11 | 538030 | 729 | 0 | 0 |
T12 | 163674 | 7065 | 0 | 0 |
T13 | 412892 | 36596 | 0 | 0 |
T14 | 0 | 3892 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 403733496 | 3756300 | 0 | 0 |
DepthKnown_A | 403733496 | 403619028 | 0 | 0 |
RvalidKnown_A | 403733496 | 403619028 | 0 | 0 |
WreadyKnown_A | 403733496 | 403619028 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 3756300 | 0 | 0 |
T1 | 4226 | 12 | 0 | 0 |
T2 | 1009 | 3 | 0 | 0 |
T3 | 499471 | 275 | 0 | 0 |
T7 | 413184 | 7 | 0 | 0 |
T8 | 20360 | 333 | 0 | 0 |
T9 | 266150 | 0 | 0 | 0 |
T10 | 34477 | 118 | 0 | 0 |
T11 | 538030 | 4178 | 0 | 0 |
T12 | 163674 | 18037 | 0 | 0 |
T13 | 412892 | 8974 | 0 | 0 |
T14 | 0 | 538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 403733496 | 403619028 | 0 | 0 |
T1 | 4226 | 4176 | 0 | 0 |
T2 | 1009 | 944 | 0 | 0 |
T3 | 499471 | 499454 | 0 | 0 |
T7 | 413184 | 413136 | 0 | 0 |
T8 | 20360 | 19671 | 0 | 0 |
T9 | 266150 | 266147 | 0 | 0 |
T10 | 34477 | 34414 | 0 | 0 |
T11 | 538030 | 537973 | 0 | 0 |
T12 | 163674 | 163670 | 0 | 0 |
T13 | 412892 | 412780 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |