Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7709152	0	0
GntImpliesValid_A	2147483647	7709152	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7709152	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	443276223	0	0
ReadyAndValidImplyGrant_A	2147483647	7709152	0	0
ReqAndReadyImplyGrant_A	2147483647	7709152	0	0
ReqImpliesValid_A	2147483647	33597114	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44414	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7709152	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101424	100224	0	0
T2	24216	22656	0	0
T3	11987304	11986896	0	0
T7	9916416	9915264	0	0
T8	488640	472104	0	0
T9	6387600	6387528	0	0
T10	827448	825936	0	0
T11	12912720	12911352	0	0
T12	3928176	3928080	0	0
T13	9909408	9906720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7709152	0	0
T1	101424	214	0	0
T2	24216	196	0	0
T3	11987304	2522	0	0
T7	9916416	397	0	0
T8	488640	9651	0	0
T9	6387600	6705	0	0
T10	827448	15054	0	0
T11	12912720	1224	0	0
T12	3928176	4064	0	0
T13	9909408	26524	0	0
T14	0	2885	0	0
T15	0	1644	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7709152	0	0
T1	101424	214	0	0
T2	24216	196	0	0
T3	11987304	2522	0	0
T7	9916416	397	0	0
T8	488640	9651	0	0
T9	6387600	6705	0	0
T10	827448	15054	0	0
T11	12912720	1224	0	0
T12	3928176	4064	0	0
T13	9909408	26524	0	0
T14	0	2885	0	0
T15	0	1644	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101424	100224	0	0
T2	24216	22656	0	0
T3	11987304	11986896	0	0
T7	9916416	9915264	0	0
T8	488640	472104	0	0
T9	6387600	6387528	0	0
T10	827448	825936	0	0
T11	12912720	12911352	0	0
T12	3928176	3928080	0	0
T13	9909408	9906720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101424	100224	0	0
T2	24216	22656	0	0
T3	11987304	11986896	0	0
T7	9916416	9915264	0	0
T8	488640	472104	0	0
T9	6387600	6387528	0	0
T10	827448	825936	0	0
T11	12912720	12911352	0	0
T12	3928176	3928080	0	0
T13	9909408	9906720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7709152	0	0
T1	101424	214	0	0
T2	24216	196	0	0
T3	11987304	2522	0	0
T7	9916416	397	0	0
T8	488640	9651	0	0
T9	6387600	6705	0	0
T10	827448	15054	0	0
T11	12912720	1224	0	0
T12	3928176	4064	0	0
T13	9909408	26524	0	0
T14	0	2885	0	0
T15	0	1644	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	443276223	0	0
T1	101424	5275	0	0
T2	24216	267	0	0
T3	11987304	424910	0	0
T7	9916416	510946	0	0
T8	488640	14603	0	0
T9	6387600	242769	0	0
T10	827448	14280	0	0
T11	12912720	837174	0	0
T12	3928176	1416035	0	0
T13	9909408	562556	0	0
T14	0	82	0	0
T15	0	2460	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7709152	0	0
T1	101424	214	0	0
T2	24216	196	0	0
T3	11987304	2522	0	0
T7	9916416	397	0	0
T8	488640	9651	0	0
T9	6387600	6705	0	0
T10	827448	15054	0	0
T11	12912720	1224	0	0
T12	3928176	4064	0	0
T13	9909408	26524	0	0
T14	0	2885	0	0
T15	0	1644	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7709152	0	0
T1	101424	214	0	0
T2	24216	196	0	0
T3	11987304	2522	0	0
T7	9916416	397	0	0
T8	488640	9651	0	0
T9	6387600	6705	0	0
T10	827448	15054	0	0
T11	12912720	1224	0	0
T12	3928176	4064	0	0
T13	9909408	26524	0	0
T14	0	2885	0	0
T15	0	1644	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33597114	0	0
T1	101424	475	0	0
T2	24216	209	0	0
T3	11987304	3940	0	0
T7	9916416	27695	0	0
T8	488640	11241	0	0
T9	6387600	15494	0	0
T10	827448	25022	0	0
T11	12912720	74342	0	0
T12	3928176	260584	0	0
T13	9909408	95581	0	0
T14	0	16332	0	0
T15	0	2064	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44414	0	21600
T4	422434	0	0	2
T8	40720	157	0	2
T9	532300	0	0	2
T10	68954	831	0	2
T11	1076060	0	0	2
T12	327348	0	0	2
T13	825784	24	0	2
T14	40014	308	0	2
T15	26608	18	0	2
T16	663548	7	0	2
T17	0	28	0	0
T18	0	10	0	0
T19	0	7	0	0
T20	0	437	0	0
T21	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101424	100224	0	0
T2	24216	22656	0	0
T3	11987304	11986896	0	0
T7	9916416	9915264	0	0
T8	488640	472104	0	0
T9	6387600	6387528	0	0
T10	827448	825936	0	0
T11	12912720	12911352	0	0
T12	3928176	3928080	0	0
T13	9909408	9906720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7709152	0	0
T1	101424	214	0	0
T2	24216	196	0	0
T3	11987304	2522	0	0
T7	9916416	397	0	0
T8	488640	9651	0	0
T9	6387600	6705	0	0
T10	827448	15054	0	0
T11	12912720	1224	0	0
T12	3928176	4064	0	0
T13	9909408	26524	0	0
T14	0	2885	0	0
T15	0	1644	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	873563	0	0
GntImpliesValid_A	403733496	873563	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	873563	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	11918726	0	0
ReadyAndValidImplyGrant_A	403733496	873563	0	0
ReqAndReadyImplyGrant_A	403733496	873563	0	0
ReqImpliesValid_A	403733496	2453160	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	873563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	873563	0	0
T1	4226	23	0	0
T2	1009	26	0	0
T3	499471	291	0	0
T7	413184	38	0	0
T8	20360	995	0	0
T9	266150	1229	0	0
T10	34477	1196	0	0
T11	538030	128	0	0
T12	163674	450	0	0
T13	412892	3295	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	873563	0	0
T1	4226	23	0	0
T2	1009	26	0	0
T3	499471	291	0	0
T7	413184	38	0	0
T8	20360	995	0	0
T9	266150	1229	0	0
T10	34477	1196	0	0
T11	538030	128	0	0
T12	163674	450	0	0
T13	412892	3295	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	873563	0	0
T1	4226	23	0	0
T2	1009	26	0	0
T3	499471	291	0	0
T7	413184	38	0	0
T8	20360	995	0	0
T9	266150	1229	0	0
T10	34477	1196	0	0
T11	538030	128	0	0
T12	163674	450	0	0
T13	412892	3295	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	11918726	0	0
T1	4226	163	0	0
T2	1009	23	0	0
T3	499471	1150	0	0
T7	413184	12166	0	0
T8	20360	764	0	0
T9	266150	4410	0	0
T10	34477	936	0	0
T11	538030	45824	0	0
T12	163674	140480	0	0
T13	412892	21438	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	873563	0	0
T1	4226	23	0	0
T2	1009	26	0	0
T3	499471	291	0	0
T7	413184	38	0	0
T8	20360	995	0	0
T9	266150	1229	0	0
T10	34477	1196	0	0
T11	538030	128	0	0
T12	163674	450	0	0
T13	412892	3295	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	873563	0	0
T1	4226	23	0	0
T2	1009	26	0	0
T3	499471	291	0	0
T7	413184	38	0	0
T8	20360	995	0	0
T9	266150	1229	0	0
T10	34477	1196	0	0
T11	538030	128	0	0
T12	163674	450	0	0
T13	412892	3295	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2453160	0	0
T1	4226	60	0	0
T2	1009	30	0	0
T3	499471	422	0	0
T7	413184	38	0	0
T8	20360	1231	0	0
T9	266150	2448	0	0
T10	34477	1458	0	0
T11	538030	4006	0	0
T12	163674	15211	0	0
T13	412892	6455	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	873563	0	0
T1	4226	23	0	0
T2	1009	26	0	0
T3	499471	291	0	0
T7	413184	38	0	0
T8	20360	995	0	0
T9	266150	1229	0	0
T10	34477	1196	0	0
T11	538030	128	0	0
T12	163674	450	0	0
T13	412892	3295	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	855933	0	0
GntImpliesValid_A	403733496	855933	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	855933	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	11848576	0	0
ReadyAndValidImplyGrant_A	403733496	855933	0	0
ReqAndReadyImplyGrant_A	403733496	855933	0	0
ReqImpliesValid_A	403733496	2388627	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	855933	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	855933	0	0
T1	4226	24	0	0
T2	1009	27	0	0
T3	499471	251	0	0
T7	413184	58	0	0
T8	20360	981	0	0
T9	266150	507	0	0
T10	34477	1183	0	0
T11	538030	133	0	0
T12	163674	452	0	0
T13	412892	2541	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	855933	0	0
T1	4226	24	0	0
T2	1009	27	0	0
T3	499471	251	0	0
T7	413184	58	0	0
T8	20360	981	0	0
T9	266150	507	0	0
T10	34477	1183	0	0
T11	538030	133	0	0
T12	163674	452	0	0
T13	412892	2541	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	855933	0	0
T1	4226	24	0	0
T2	1009	27	0	0
T3	499471	251	0	0
T7	413184	58	0	0
T8	20360	981	0	0
T9	266150	507	0	0
T10	34477	1183	0	0
T11	538030	133	0	0
T12	163674	452	0	0
T13	412892	2541	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	11848576	0	0
T1	4226	163	0	0
T2	1009	21	0	0
T3	499471	987	0	0
T7	413184	18385	0	0
T8	20360	781	0	0
T9	266150	2108	0	0
T10	34477	921	0	0
T11	538030	38857	0	0
T12	163674	143632	0	0
T13	412892	18969	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	855933	0	0
T1	4226	24	0	0
T2	1009	27	0	0
T3	499471	251	0	0
T7	413184	58	0	0
T8	20360	981	0	0
T9	266150	507	0	0
T10	34477	1183	0	0
T11	538030	133	0	0
T12	163674	452	0	0
T13	412892	2541	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	855933	0	0
T1	4226	24	0	0
T2	1009	27	0	0
T3	499471	251	0	0
T7	413184	58	0	0
T8	20360	981	0	0
T9	266150	507	0	0
T10	34477	1183	0	0
T11	538030	133	0	0
T12	163674	452	0	0
T13	412892	2541	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2388627	0	0
T1	4226	62	0	0
T2	1009	34	0	0
T3	499471	353	0	0
T7	413184	1244	0	0
T8	20360	1185	0	0
T9	266150	701	0	0
T10	34477	1447	0	0
T11	538030	2597	0	0
T12	163674	20070	0	0
T13	412892	4008	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	855933	0	0
T1	4226	24	0	0
T2	1009	27	0	0
T3	499471	251	0	0
T7	413184	58	0	0
T8	20360	981	0	0
T9	266150	507	0	0
T10	34477	1183	0	0
T11	538030	133	0	0
T12	163674	452	0	0
T13	412892	2541	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	214328	0	0
GntImpliesValid_A	403733496	214328	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	214328	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2928411	0	0
ReadyAndValidImplyGrant_A	403733496	214328	0	0
ReqAndReadyImplyGrant_A	403733496	214328	0	0
ReqImpliesValid_A	403733496	575284	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	214328	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214328	0	0
T1	4226	8	0	0
T2	1009	8	0	0
T3	499471	79	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	117	0	0
T11	538030	40	0	0
T12	163674	106	0	0
T13	412892	498	0	0
T15	0	175	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214328	0	0
T1	4226	8	0	0
T2	1009	8	0	0
T3	499471	79	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	117	0	0
T11	538030	40	0	0
T12	163674	106	0	0
T13	412892	498	0	0
T15	0	175	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214328	0	0
T1	4226	8	0	0
T2	1009	8	0	0
T3	499471	79	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	117	0	0
T11	538030	40	0	0
T12	163674	106	0	0
T13	412892	498	0	0
T15	0	175	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2928411	0	0
T1	4226	55	0	0
T2	1009	9	0	0
T3	499471	350	0	0
T7	413184	3826	0	0
T8	20360	184	0	0
T9	266150	1	0	0
T10	34477	114	0	0
T11	538030	13958	0	0
T12	163674	33719	0	0
T13	412892	3801	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214328	0	0
T1	4226	8	0	0
T2	1009	8	0	0
T3	499471	79	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	117	0	0
T11	538030	40	0	0
T12	163674	106	0	0
T13	412892	498	0	0
T15	0	175	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214328	0	0
T1	4226	8	0	0
T2	1009	8	0	0
T3	499471	79	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	117	0	0
T11	538030	40	0	0
T12	163674	106	0	0
T13	412892	498	0	0
T15	0	175	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	575284	0	0
T1	4226	8	0	0
T2	1009	8	0	0
T3	499471	99	0	0
T7	413184	489	0	0
T8	20360	189	0	0
T9	266150	0	0	0
T10	34477	122	0	0
T11	538030	1381	0	0
T12	163674	4618	0	0
T13	412892	673	0	0
T15	0	185	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214328	0	0
T1	4226	8	0	0
T2	1009	8	0	0
T3	499471	79	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	117	0	0
T11	538030	40	0	0
T12	163674	106	0	0
T13	412892	498	0	0
T15	0	175	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	208197	0	0
GntImpliesValid_A	403733496	208197	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	208197	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2900810	0	0
ReadyAndValidImplyGrant_A	403733496	208197	0	0
ReqAndReadyImplyGrant_A	403733496	208197	0	0
ReqImpliesValid_A	403733496	527945	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	208197	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208197	0	0
T1	4226	5	0	0
T2	1009	5	0	0
T3	499471	76	0	0
T7	413184	13	0	0
T8	20360	186	0	0
T9	266150	511	0	0
T10	34477	594	0	0
T11	538030	36	0	0
T12	163674	104	0	0
T13	412892	1497	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208197	0	0
T1	4226	5	0	0
T2	1009	5	0	0
T3	499471	76	0	0
T7	413184	13	0	0
T8	20360	186	0	0
T9	266150	511	0	0
T10	34477	594	0	0
T11	538030	36	0	0
T12	163674	104	0	0
T13	412892	1497	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208197	0	0
T1	4226	5	0	0
T2	1009	5	0	0
T3	499471	76	0	0
T7	413184	13	0	0
T8	20360	186	0	0
T9	266150	511	0	0
T10	34477	594	0	0
T11	538030	36	0	0
T12	163674	104	0	0
T13	412892	1497	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2900810	0	0
T1	4226	37	0	0
T2	1009	6	0	0
T3	499471	308	0	0
T7	413184	4649	0	0
T8	20360	187	0	0
T9	266150	1670	0	0
T10	34477	143	0	0
T11	538030	10307	0	0
T12	163674	31181	0	0
T13	412892	8925	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208197	0	0
T1	4226	5	0	0
T2	1009	5	0	0
T3	499471	76	0	0
T7	413184	13	0	0
T8	20360	186	0	0
T9	266150	511	0	0
T10	34477	594	0	0
T11	538030	36	0	0
T12	163674	104	0	0
T13	412892	1497	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208197	0	0
T1	4226	5	0	0
T2	1009	5	0	0
T3	499471	76	0	0
T7	413184	13	0	0
T8	20360	186	0	0
T9	266150	511	0	0
T10	34477	594	0	0
T11	538030	36	0	0
T12	163674	104	0	0
T13	412892	1497	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	527945	0	0
T1	4226	5	0	0
T2	1009	5	0	0
T3	499471	92	0	0
T7	413184	13	0	0
T8	20360	190	0	0
T9	266150	1266	0	0
T10	34477	1047	0	0
T11	538030	356	0	0
T12	163674	2118	0	0
T13	412892	3019	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208197	0	0
T1	4226	5	0	0
T2	1009	5	0	0
T3	499471	76	0	0
T7	413184	13	0	0
T8	20360	186	0	0
T9	266150	511	0	0
T10	34477	594	0	0
T11	538030	36	0	0
T12	163674	104	0	0
T13	412892	1497	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	217166	0	0
GntImpliesValid_A	403733496	217166	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	217166	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	5809812	0	0
ReadyAndValidImplyGrant_A	403733496	217166	0	0
ReqAndReadyImplyGrant_A	403733496	217166	0	0
ReqImpliesValid_A	403733496	1405467	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	217166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217166	0	0
T1	4226	4	0	0
T2	1009	3	0	0
T3	499471	84	0	0
T7	413184	7	0	0
T8	20360	169	0	0
T9	266150	0	0	0
T10	34477	587	0	0
T11	538030	31	0	0
T12	163674	116	0	0
T13	412892	503	0	0
T15	0	178	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217166	0	0
T1	4226	4	0	0
T2	1009	3	0	0
T3	499471	84	0	0
T7	413184	7	0	0
T8	20360	169	0	0
T9	266150	0	0	0
T10	34477	587	0	0
T11	538030	31	0	0
T12	163674	116	0	0
T13	412892	503	0	0
T15	0	178	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217166	0	0
T1	4226	4	0	0
T2	1009	3	0	0
T3	499471	84	0	0
T7	413184	7	0	0
T8	20360	169	0	0
T9	266150	0	0	0
T10	34477	587	0	0
T11	538030	31	0	0
T12	163674	116	0	0
T13	412892	503	0	0
T15	0	178	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	5809812	0	0
T1	4226	59	0	0
T2	1009	43	0	0
T3	499471	788	0	0
T7	413184	6472	0	0
T8	20360	2620	0	0
T9	266150	0	0	0
T10	34477	1367	0	0
T11	538030	7338	0	0
T12	163674	66202	0	0
T13	412892	4937	0	0
T15	0	1279	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217166	0	0
T1	4226	4	0	0
T2	1009	3	0	0
T3	499471	84	0	0
T7	413184	7	0	0
T8	20360	169	0	0
T9	266150	0	0	0
T10	34477	587	0	0
T11	538030	31	0	0
T12	163674	116	0	0
T13	412892	503	0	0
T15	0	178	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217166	0	0
T1	4226	4	0	0
T2	1009	3	0	0
T3	499471	84	0	0
T7	413184	7	0	0
T8	20360	169	0	0
T9	266150	0	0	0
T10	34477	587	0	0
T11	538030	31	0	0
T12	163674	116	0	0
T13	412892	503	0	0
T15	0	178	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1405467	0	0
T1	4226	4	0	0
T2	1009	3	0	0
T3	499471	115	0	0
T7	413184	630	0	0
T8	20360	299	0	0
T9	266150	0	0	0
T10	34477	2408	0	0
T11	538030	502	0	0
T12	163674	4434	0	0
T13	412892	558	0	0
T15	0	400	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217166	0	0
T1	4226	4	0	0
T2	1009	3	0	0
T3	499471	84	0	0
T7	413184	7	0	0
T8	20360	169	0	0
T9	266150	0	0	0
T10	34477	587	0	0
T11	538030	31	0	0
T12	163674	116	0	0
T13	412892	503	0	0
T15	0	178	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	214425	0	0
GntImpliesValid_A	403733496	214425	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	214425	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	5507353	0	0
ReadyAndValidImplyGrant_A	403733496	214425	0	0
ReqAndReadyImplyGrant_A	403733496	214425	0	0
ReqImpliesValid_A	403733496	1222669	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	214425	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214425	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	82	0	0
T7	413184	7	0	0
T8	20360	334	0	0
T9	266150	0	0	0
T10	34477	118	0	0
T11	538030	31	0	0
T12	163674	121	0	0
T13	412892	2028	0	0
T14	0	538	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214425	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	82	0	0
T7	413184	7	0	0
T8	20360	334	0	0
T9	266150	0	0	0
T10	34477	118	0	0
T11	538030	31	0	0
T12	163674	121	0	0
T13	412892	2028	0	0
T14	0	538	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214425	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	82	0	0
T7	413184	7	0	0
T8	20360	334	0	0
T9	266150	0	0	0
T10	34477	118	0	0
T11	538030	31	0	0
T12	163674	121	0	0
T13	412892	2028	0	0
T14	0	538	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	5507353	0	0
T1	4226	35	0	0
T2	1009	22	0	0
T3	499471	378	0	0
T7	413184	2586	0	0
T8	20360	1580	0	0
T9	266150	0	0	0
T10	34477	585	0	0
T11	538030	15704	0	0
T12	163674	61311	0	0
T13	412892	50875	0	0
T14	0	70	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214425	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	82	0	0
T7	413184	7	0	0
T8	20360	334	0	0
T9	266150	0	0	0
T10	34477	118	0	0
T11	538030	31	0	0
T12	163674	121	0	0
T13	412892	2028	0	0
T14	0	538	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214425	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	82	0	0
T7	413184	7	0	0
T8	20360	334	0	0
T9	266150	0	0	0
T10	34477	118	0	0
T11	538030	31	0	0
T12	163674	121	0	0
T13	412892	2028	0	0
T14	0	538	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1222669	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	107	0	0
T7	413184	79	0	0
T8	20360	620	0	0
T9	266150	0	0	0
T10	34477	122	0	0
T11	538030	729	0	0
T12	163674	7065	0	0
T13	412892	36596	0	0
T14	0	3892	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	214425	0	0
T1	4226	3	0	0
T2	1009	3	0	0
T3	499471	82	0	0
T7	413184	7	0	0
T8	20360	334	0	0
T9	266150	0	0	0
T10	34477	118	0	0
T11	538030	31	0	0
T12	163674	121	0	0
T13	412892	2028	0	0
T14	0	538	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	215376	0	0
GntImpliesValid_A	403733496	215376	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	215376	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	5296329	0	0
ReadyAndValidImplyGrant_A	403733496	215376	0	0
ReqAndReadyImplyGrant_A	403733496	215376	0	0
ReqImpliesValid_A	403733496	1115096	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	215376	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215376	0	0
T1	4226	8	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	17	0	0
T8	20360	186	0	0
T9	266150	0	0	0
T10	34477	560	0	0
T11	538030	39	0	0
T12	163674	87	0	0
T13	412892	448	0	0
T15	0	186	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215376	0	0
T1	4226	8	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	17	0	0
T8	20360	186	0	0
T9	266150	0	0	0
T10	34477	560	0	0
T11	538030	39	0	0
T12	163674	87	0	0
T13	412892	448	0	0
T15	0	186	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215376	0	0
T1	4226	8	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	17	0	0
T8	20360	186	0	0
T9	266150	0	0	0
T10	34477	560	0	0
T11	538030	39	0	0
T12	163674	87	0	0
T13	412892	448	0	0
T15	0	186	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	5296329	0	0
T1	4226	173	0	0
T2	1009	32	0	0
T3	499471	400	0	0
T7	413184	4564	0	0
T8	20360	3593	0	0
T9	266150	0	0	0
T10	34477	3161	0	0
T11	538030	15093	0	0
T12	163674	55128	0	0
T13	412892	5273	0	0
T15	0	1181	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215376	0	0
T1	4226	8	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	17	0	0
T8	20360	186	0	0
T9	266150	0	0	0
T10	34477	560	0	0
T11	538030	39	0	0
T12	163674	87	0	0
T13	412892	448	0	0
T15	0	186	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215376	0	0
T1	4226	8	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	17	0	0
T8	20360	186	0	0
T9	266150	0	0	0
T10	34477	560	0	0
T11	538030	39	0	0
T12	163674	87	0	0
T13	412892	448	0	0
T15	0	186	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1115096	0	0
T1	4226	10	0	0
T2	1009	5	0	0
T3	499471	93	0	0
T7	413184	854	0	0
T8	20360	494	0	0
T9	266150	0	0	0
T10	34477	2607	0	0
T11	538030	39	0	0
T12	163674	2929	0	0
T13	412892	559	0	0
T15	0	314	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215376	0	0
T1	4226	8	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	17	0	0
T8	20360	186	0	0
T9	266150	0	0	0
T10	34477	560	0	0
T11	538030	39	0	0
T12	163674	87	0	0
T13	412892	448	0	0
T15	0	186	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T8,T10,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	217866	0	0
GntImpliesValid_A	403733496	217866	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	217866	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	5430969	0	0
ReadyAndValidImplyGrant_A	403733496	217866	0	0
ReqAndReadyImplyGrant_A	403733496	217866	0	0
ReqImpliesValid_A	403733496	1165339	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	217866	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217866	0	0
T1	4226	6	0	0
T2	1009	3	0	0
T3	499471	61	0	0
T7	413184	11	0	0
T8	20360	179	0	0
T9	266150	0	0	0
T10	34477	559	0	0
T11	538030	31	0	0
T12	163674	100	0	0
T13	412892	477	0	0
T14	0	518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217866	0	0
T1	4226	6	0	0
T2	1009	3	0	0
T3	499471	61	0	0
T7	413184	11	0	0
T8	20360	179	0	0
T9	266150	0	0	0
T10	34477	559	0	0
T11	538030	31	0	0
T12	163674	100	0	0
T13	412892	477	0	0
T14	0	518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217866	0	0
T1	4226	6	0	0
T2	1009	3	0	0
T3	499471	61	0	0
T7	413184	11	0	0
T8	20360	179	0	0
T9	266150	0	0	0
T10	34477	559	0	0
T11	538030	31	0	0
T12	163674	100	0	0
T13	412892	477	0	0
T14	0	518	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	5430969	0	0
T1	4226	146	0	0
T2	1009	19	0	0
T3	499471	256	0	0
T7	413184	15773	0	0
T8	20360	1079	0	0
T9	266150	0	0	0
T10	34477	4365	0	0
T11	538030	18947	0	0
T12	163674	64344	0	0
T13	412892	7037	0	0
T14	0	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217866	0	0
T1	4226	6	0	0
T2	1009	3	0	0
T3	499471	61	0	0
T7	413184	11	0	0
T8	20360	179	0	0
T9	266150	0	0	0
T10	34477	559	0	0
T11	538030	31	0	0
T12	163674	100	0	0
T13	412892	477	0	0
T14	0	518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217866	0	0
T1	4226	6	0	0
T2	1009	3	0	0
T3	499471	61	0	0
T7	413184	11	0	0
T8	20360	179	0	0
T9	266150	0	0	0
T10	34477	559	0	0
T11	538030	31	0	0
T12	163674	100	0	0
T13	412892	477	0	0
T14	0	518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	1165339	0	0
T1	4226	6	0	0
T2	1009	3	0	0
T3	499471	61	0	0
T7	413184	11	0	0
T8	20360	226	0	0
T9	266150	0	0	0
T10	34477	2732	0	0
T11	538030	1346	0	0
T12	163674	6168	0	0
T13	412892	721	0	0
T14	0	8854	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217866	0	0
T1	4226	6	0	0
T2	1009	3	0	0
T3	499471	61	0	0
T7	413184	11	0	0
T8	20360	179	0	0
T9	266150	0	0	0
T10	34477	559	0	0
T11	538030	31	0	0
T12	163674	100	0	0
T13	412892	477	0	0
T14	0	518	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	204944	0	0
GntImpliesValid_A	403733496	204944	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	204944	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2884680	0	0
ReadyAndValidImplyGrant_A	403733496	204944	0	0
ReqAndReadyImplyGrant_A	403733496	204944	0	0
ReqImpliesValid_A	403733496	536564	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	204944	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	204944	0	0
T1	4226	12	0	0
T2	1009	5	0	0
T3	499471	84	0	0
T7	413184	9	0	0
T8	20360	735	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	45	0	0
T12	163674	110	0	0
T13	412892	461	0	0
T14	0	447	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	204944	0	0
T1	4226	12	0	0
T2	1009	5	0	0
T3	499471	84	0	0
T7	413184	9	0	0
T8	20360	735	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	45	0	0
T12	163674	110	0	0
T13	412892	461	0	0
T14	0	447	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	204944	0	0
T1	4226	12	0	0
T2	1009	5	0	0
T3	499471	84	0	0
T7	413184	9	0	0
T8	20360	735	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	45	0	0
T12	163674	110	0	0
T13	412892	461	0	0
T14	0	447	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2884680	0	0
T1	4226	75	0	0
T2	1009	6	0	0
T3	499471	332	0	0
T7	413184	3905	0	0
T8	20360	681	0	0
T9	266150	1	0	0
T10	34477	483	0	0
T11	538030	14881	0	0
T12	163674	35786	0	0
T13	412892	3527	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	204944	0	0
T1	4226	12	0	0
T2	1009	5	0	0
T3	499471	84	0	0
T7	413184	9	0	0
T8	20360	735	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	45	0	0
T12	163674	110	0	0
T13	412892	461	0	0
T14	0	447	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	204944	0	0
T1	4226	12	0	0
T2	1009	5	0	0
T3	499471	84	0	0
T7	413184	9	0	0
T8	20360	735	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	45	0	0
T12	163674	110	0	0
T13	412892	461	0	0
T14	0	447	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	536564	0	0
T1	4226	13	0	0
T2	1009	5	0	0
T3	499471	104	0	0
T7	413184	9	0	0
T8	20360	794	0	0
T9	266150	0	0	0
T10	34477	845	0	0
T11	538030	1297	0	0
T12	163674	2143	0	0
T13	412892	568	0	0
T14	0	893	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	204944	0	0
T1	4226	12	0	0
T2	1009	5	0	0
T3	499471	84	0	0
T7	413184	9	0	0
T8	20360	735	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	45	0	0
T12	163674	110	0	0
T13	412892	461	0	0
T14	0	447	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	211864	0	0
GntImpliesValid_A	403733496	211864	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	211864	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2928629	0	0
ReadyAndValidImplyGrant_A	403733496	211864	0	0
ReqAndReadyImplyGrant_A	403733496	211864	0	0
ReqImpliesValid_A	403733496	542738	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	211864	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	211864	0	0
T1	4226	6	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	14	0	0
T8	20360	192	0	0
T9	266150	532	0	0
T10	34477	106	0	0
T11	538030	34	0	0
T12	163674	105	0	0
T13	412892	480	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	211864	0	0
T1	4226	6	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	14	0	0
T8	20360	192	0	0
T9	266150	532	0	0
T10	34477	106	0	0
T11	538030	34	0	0
T12	163674	105	0	0
T13	412892	480	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	211864	0	0
T1	4226	6	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	14	0	0
T8	20360	192	0	0
T9	266150	532	0	0
T10	34477	106	0	0
T11	538030	34	0	0
T12	163674	105	0	0
T13	412892	480	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2928629	0	0
T1	4226	50	0	0
T2	1009	6	0	0
T3	499471	262	0	0
T7	413184	4117	0	0
T8	20360	195	0	0
T9	266150	1747	0	0
T10	34477	108	0	0
T11	538030	11180	0	0
T12	163674	32643	0	0
T13	412892	3512	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	211864	0	0
T1	4226	6	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	14	0	0
T8	20360	192	0	0
T9	266150	532	0	0
T10	34477	106	0	0
T11	538030	34	0	0
T12	163674	105	0	0
T13	412892	480	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	211864	0	0
T1	4226	6	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	14	0	0
T8	20360	192	0	0
T9	266150	532	0	0
T10	34477	106	0	0
T11	538030	34	0	0
T12	163674	105	0	0
T13	412892	480	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	542738	0	0
T1	4226	6	0	0
T2	1009	5	0	0
T3	499471	69	0	0
T7	413184	126	0	0
T8	20360	194	0	0
T9	266150	1228	0	0
T10	34477	106	0	0
T11	538030	34	0	0
T12	163674	2341	0	0
T13	412892	552	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	211864	0	0
T1	4226	6	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	14	0	0
T8	20360	192	0	0
T9	266150	532	0	0
T10	34477	106	0	0
T11	538030	34	0	0
T12	163674	105	0	0
T13	412892	480	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	215832	0	0
GntImpliesValid_A	403733496	215832	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	215832	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2944230	0	0
ReadyAndValidImplyGrant_A	403733496	215832	0	0
ReqAndReadyImplyGrant_A	403733496	215832	0	0
ReqImpliesValid_A	403733496	555419	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	215832	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215832	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	58	0	0
T7	413184	4	0	0
T8	20360	694	0	0
T9	266150	0	0	0
T10	34477	114	0	0
T11	538030	26	0	0
T12	163674	121	0	0
T13	412892	1021	0	0
T15	0	189	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215832	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	58	0	0
T7	413184	4	0	0
T8	20360	694	0	0
T9	266150	0	0	0
T10	34477	114	0	0
T11	538030	26	0	0
T12	163674	121	0	0
T13	412892	1021	0	0
T15	0	189	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215832	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	58	0	0
T7	413184	4	0	0
T8	20360	694	0	0
T9	266150	0	0	0
T10	34477	114	0	0
T11	538030	26	0	0
T12	163674	121	0	0
T13	412892	1021	0	0
T15	0	189	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2944230	0	0
T1	4226	25	0	0
T2	1009	4	0	0
T3	499471	220	0	0
T7	413184	932	0	0
T8	20360	512	0	0
T9	266150	1	0	0
T10	34477	116	0	0
T11	538030	7945	0	0
T12	163674	42648	0	0
T13	412892	6343	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215832	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	58	0	0
T7	413184	4	0	0
T8	20360	694	0	0
T9	266150	0	0	0
T10	34477	114	0	0
T11	538030	26	0	0
T12	163674	121	0	0
T13	412892	1021	0	0
T15	0	189	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215832	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	58	0	0
T7	413184	4	0	0
T8	20360	694	0	0
T9	266150	0	0	0
T10	34477	114	0	0
T11	538030	26	0	0
T12	163674	121	0	0
T13	412892	1021	0	0
T15	0	189	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	555419	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	60	0	0
T7	413184	4	0	0
T8	20360	881	0	0
T9	266150	0	0	0
T10	34477	114	0	0
T11	538030	678	0	0
T12	163674	1817	0	0
T13	412892	3368	0	0
T15	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	215832	0	0
T1	4226	5	0	0
T2	1009	3	0	0
T3	499471	58	0	0
T7	413184	4	0	0
T8	20360	694	0	0
T9	266150	0	0	0
T10	34477	114	0	0
T11	538030	26	0	0
T12	163674	121	0	0
T13	412892	1021	0	0
T15	0	189	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	216542	0	0
GntImpliesValid_A	403733496	216542	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	216542	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2950274	0	0
ReadyAndValidImplyGrant_A	403733496	216542	0	0
ReqAndReadyImplyGrant_A	403733496	216542	0	0
ReqImpliesValid_A	403733496	564162	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	216542	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	216542	0	0
T1	4226	5	0	0
T2	1009	8	0	0
T3	499471	74	0	0
T7	413184	10	0	0
T8	20360	199	0	0
T9	266150	0	0	0
T10	34477	108	0	0
T11	538030	34	0	0
T12	163674	118	0	0
T13	412892	1028	0	0
T15	0	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	216542	0	0
T1	4226	5	0	0
T2	1009	8	0	0
T3	499471	74	0	0
T7	413184	10	0	0
T8	20360	199	0	0
T9	266150	0	0	0
T10	34477	108	0	0
T11	538030	34	0	0
T12	163674	118	0	0
T13	412892	1028	0	0
T15	0	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	216542	0	0
T1	4226	5	0	0
T2	1009	8	0	0
T3	499471	74	0	0
T7	413184	10	0	0
T8	20360	199	0	0
T9	266150	0	0	0
T10	34477	108	0	0
T11	538030	34	0	0
T12	163674	118	0	0
T13	412892	1028	0	0
T15	0	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2950274	0	0
T1	4226	45	0	0
T2	1009	9	0	0
T3	499471	390	0	0
T7	413184	4311	0	0
T8	20360	202	0	0
T9	266150	1	0	0
T10	34477	108	0	0
T11	538030	12728	0	0
T12	163674	38723	0	0
T13	412892	6381	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	216542	0	0
T1	4226	5	0	0
T2	1009	8	0	0
T3	499471	74	0	0
T7	413184	10	0	0
T8	20360	199	0	0
T9	266150	0	0	0
T10	34477	108	0	0
T11	538030	34	0	0
T12	163674	118	0	0
T13	412892	1028	0	0
T15	0	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	216542	0	0
T1	4226	5	0	0
T2	1009	8	0	0
T3	499471	74	0	0
T7	413184	10	0	0
T8	20360	199	0	0
T9	266150	0	0	0
T10	34477	108	0	0
T11	538030	34	0	0
T12	163674	118	0	0
T13	412892	1028	0	0
T15	0	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	564162	0	0
T1	4226	5	0	0
T2	1009	8	0	0
T3	499471	101	0	0
T7	413184	305	0	0
T8	20360	201	0	0
T9	266150	0	0	0
T10	34477	110	0	0
T11	538030	368	0	0
T12	163674	3106	0	0
T13	412892	3480	0	0
T15	0	173	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	216542	0	0
T1	4226	5	0	0
T2	1009	8	0	0
T3	499471	74	0	0
T7	413184	10	0	0
T8	20360	199	0	0
T9	266150	0	0	0
T10	34477	108	0	0
T11	538030	34	0	0
T12	163674	118	0	0
T13	412892	1028	0	0
T15	0	166	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	208555	0	0
GntImpliesValid_A	403733496	208555	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	208555	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2878786	0	0
ReadyAndValidImplyGrant_A	403733496	208555	0	0
ReqAndReadyImplyGrant_A	403733496	208555	0	0
ReqImpliesValid_A	403733496	532175	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	208555	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208555	0	0
T1	4226	11	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	11	0	0
T8	20360	172	0	0
T9	266150	0	0	0
T10	34477	558	0	0
T11	538030	42	0	0
T12	163674	114	0	0
T13	412892	486	0	0
T15	0	203	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208555	0	0
T1	4226	11	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	11	0	0
T8	20360	172	0	0
T9	266150	0	0	0
T10	34477	558	0	0
T11	538030	42	0	0
T12	163674	114	0	0
T13	412892	486	0	0
T15	0	203	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208555	0	0
T1	4226	11	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	11	0	0
T8	20360	172	0	0
T9	266150	0	0	0
T10	34477	558	0	0
T11	538030	42	0	0
T12	163674	114	0	0
T13	412892	486	0	0
T15	0	203	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2878786	0	0
T1	4226	90	0	0
T2	1009	6	0	0
T3	499471	283	0	0
T7	413184	2456	0	0
T8	20360	170	0	0
T9	266150	1	0	0
T10	34477	102	0	0
T11	538030	12895	0	0
T12	163674	36329	0	0
T13	412892	3667	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208555	0	0
T1	4226	11	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	11	0	0
T8	20360	172	0	0
T9	266150	0	0	0
T10	34477	558	0	0
T11	538030	42	0	0
T12	163674	114	0	0
T13	412892	486	0	0
T15	0	203	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208555	0	0
T1	4226	11	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	11	0	0
T8	20360	172	0	0
T9	266150	0	0	0
T10	34477	558	0	0
T11	538030	42	0	0
T12	163674	114	0	0
T13	412892	486	0	0
T15	0	203	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	532175	0	0
T1	4226	11	0	0
T2	1009	5	0	0
T3	499471	79	0	0
T7	413184	317	0	0
T8	20360	179	0	0
T9	266150	0	0	0
T10	34477	1016	0	0
T11	538030	1065	0	0
T12	163674	1418	0	0
T13	412892	543	0	0
T15	0	215	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208555	0	0
T1	4226	11	0	0
T2	1009	5	0	0
T3	499471	68	0	0
T7	413184	11	0	0
T8	20360	172	0	0
T9	266150	0	0	0
T10	34477	558	0	0
T11	538030	42	0	0
T12	163674	114	0	0
T13	412892	486	0	0
T15	0	203	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	209222	0	0
GntImpliesValid_A	403733496	209222	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	209222	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2938855	0	0
ReadyAndValidImplyGrant_A	403733496	209222	0	0
ReqAndReadyImplyGrant_A	403733496	209222	0	0
ReqImpliesValid_A	403733496	533514	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	209222	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	209222	0	0
T1	4226	2	0	0
T2	1009	9	0	0
T3	499471	74	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	493	0	0
T10	34477	119	0	0
T11	538030	29	0	0
T12	163674	110	0	0
T13	412892	446	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	209222	0	0
T1	4226	2	0	0
T2	1009	9	0	0
T3	499471	74	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	493	0	0
T10	34477	119	0	0
T11	538030	29	0	0
T12	163674	110	0	0
T13	412892	446	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	209222	0	0
T1	4226	2	0	0
T2	1009	9	0	0
T3	499471	74	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	493	0	0
T10	34477	119	0	0
T11	538030	29	0	0
T12	163674	110	0	0
T13	412892	446	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2938855	0	0
T1	4226	17	0	0
T2	1009	9	0	0
T3	499471	362	0	0
T7	413184	3680	0	0
T8	20360	185	0	0
T9	266150	1529	0	0
T10	34477	117	0	0
T11	538030	10711	0	0
T12	163674	36699	0	0
T13	412892	3321	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	209222	0	0
T1	4226	2	0	0
T2	1009	9	0	0
T3	499471	74	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	493	0	0
T10	34477	119	0	0
T11	538030	29	0	0
T12	163674	110	0	0
T13	412892	446	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	209222	0	0
T1	4226	2	0	0
T2	1009	9	0	0
T3	499471	74	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	493	0	0
T10	34477	119	0	0
T11	538030	29	0	0
T12	163674	110	0	0
T13	412892	446	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	533514	0	0
T1	4226	2	0	0
T2	1009	10	0	0
T3	499471	81	0	0
T7	413184	124	0	0
T8	20360	188	0	0
T9	266150	1216	0	0
T10	34477	123	0	0
T11	538030	61	0	0
T12	163674	610	0	0
T13	412892	514	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	209222	0	0
T1	4226	2	0	0
T2	1009	9	0	0
T3	499471	74	0	0
T7	413184	14	0	0
T8	20360	184	0	0
T9	266150	493	0	0
T10	34477	119	0	0
T11	538030	29	0	0
T12	163674	110	0	0
T13	412892	446	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	217276	0	0
GntImpliesValid_A	403733496	217276	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	217276	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2940761	0	0
ReadyAndValidImplyGrant_A	403733496	217276	0	0
ReqAndReadyImplyGrant_A	403733496	217276	0	0
ReqImpliesValid_A	403733496	520985	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	217276	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217276	0	0
T1	4226	8	0	0
T2	1009	4	0	0
T3	499471	65	0	0
T7	413184	10	0	0
T8	20360	201	0	0
T9	266150	1530	0	0
T10	34477	115	0	0
T11	538030	31	0	0
T12	163674	115	0	0
T13	412892	960	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217276	0	0
T1	4226	8	0	0
T2	1009	4	0	0
T3	499471	65	0	0
T7	413184	10	0	0
T8	20360	201	0	0
T9	266150	1530	0	0
T10	34477	115	0	0
T11	538030	31	0	0
T12	163674	115	0	0
T13	412892	960	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217276	0	0
T1	4226	8	0	0
T2	1009	4	0	0
T3	499471	65	0	0
T7	413184	10	0	0
T8	20360	201	0	0
T9	266150	1530	0	0
T10	34477	115	0	0
T11	538030	31	0	0
T12	163674	115	0	0
T13	412892	960	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2940761	0	0
T1	4226	48	0	0
T2	1009	5	0	0
T3	499471	249	0	0
T7	413184	3063	0	0
T8	20360	199	0	0
T9	266150	4947	0	0
T10	34477	117	0	0
T11	538030	12352	0	0
T12	163674	39903	0	0
T13	412892	6693	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217276	0	0
T1	4226	8	0	0
T2	1009	4	0	0
T3	499471	65	0	0
T7	413184	10	0	0
T8	20360	201	0	0
T9	266150	1530	0	0
T10	34477	115	0	0
T11	538030	31	0	0
T12	163674	115	0	0
T13	412892	960	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217276	0	0
T1	4226	8	0	0
T2	1009	4	0	0
T3	499471	65	0	0
T7	413184	10	0	0
T8	20360	201	0	0
T9	266150	1530	0	0
T10	34477	115	0	0
T11	538030	31	0	0
T12	163674	115	0	0
T13	412892	960	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	520985	0	0
T1	4226	8	0	0
T2	1009	4	0	0
T3	499471	68	0	0
T7	413184	10	0	0
T8	20360	208	0	0
T9	266150	3608	0	0
T10	34477	115	0	0
T11	538030	90	0	0
T12	163674	2010	0	0
T13	412892	2376	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217276	0	0
T1	4226	8	0	0
T2	1009	4	0	0
T3	499471	65	0	0
T7	413184	10	0	0
T8	20360	201	0	0
T9	266150	1530	0	0
T10	34477	115	0	0
T11	538030	31	0	0
T12	163674	115	0	0
T13	412892	960	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	217289	0	0
GntImpliesValid_A	403733496	217289	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	217289	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2915314	0	0
ReadyAndValidImplyGrant_A	403733496	217289	0	0
ReqAndReadyImplyGrant_A	403733496	217289	0	0
ReqImpliesValid_A	403733496	559485	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	217289	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217289	0	0
T1	4226	4	0	0
T2	1009	5	0	0
T3	499471	61	0	0
T7	413184	7	0	0
T8	20360	189	0	0
T9	266150	0	0	0
T10	34477	95	0	0
T11	538030	24	0	0
T12	163674	118	0	0
T13	412892	1044	0	0
T15	0	181	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217289	0	0
T1	4226	4	0	0
T2	1009	5	0	0
T3	499471	61	0	0
T7	413184	7	0	0
T8	20360	189	0	0
T9	266150	0	0	0
T10	34477	95	0	0
T11	538030	24	0	0
T12	163674	118	0	0
T13	412892	1044	0	0
T15	0	181	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217289	0	0
T1	4226	4	0	0
T2	1009	5	0	0
T3	499471	61	0	0
T7	413184	7	0	0
T8	20360	189	0	0
T9	266150	0	0	0
T10	34477	95	0	0
T11	538030	24	0	0
T12	163674	118	0	0
T13	412892	1044	0	0
T15	0	181	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2915314	0	0
T1	4226	31	0	0
T2	1009	6	0	0
T3	499471	285	0	0
T7	413184	2401	0	0
T8	20360	186	0	0
T9	266150	1	0	0
T10	34477	96	0	0
T11	538030	8247	0	0
T12	163674	41639	0	0
T13	412892	6703	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217289	0	0
T1	4226	4	0	0
T2	1009	5	0	0
T3	499471	61	0	0
T7	413184	7	0	0
T8	20360	189	0	0
T9	266150	0	0	0
T10	34477	95	0	0
T11	538030	24	0	0
T12	163674	118	0	0
T13	412892	1044	0	0
T15	0	181	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217289	0	0
T1	4226	4	0	0
T2	1009	5	0	0
T3	499471	61	0	0
T7	413184	7	0	0
T8	20360	189	0	0
T9	266150	0	0	0
T10	34477	95	0	0
T11	538030	24	0	0
T12	163674	118	0	0
T13	412892	1044	0	0
T15	0	181	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	559485	0	0
T1	4226	4	0	0
T2	1009	5	0	0
T3	499471	64	0	0
T7	413184	7	0	0
T8	20360	197	0	0
T9	266150	0	0	0
T10	34477	96	0	0
T11	538030	361	0	0
T12	163674	569	0	0
T13	412892	1606	0	0
T15	0	191	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	217289	0	0
T1	4226	4	0	0
T2	1009	5	0	0
T3	499471	61	0	0
T7	413184	7	0	0
T8	20360	189	0	0
T9	266150	0	0	0
T10	34477	95	0	0
T11	538030	24	0	0
T12	163674	118	0	0
T13	412892	1044	0	0
T15	0	181	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	229582	0	0
GntImpliesValid_A	403733496	229582	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	229582	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2985744	0	0
ReadyAndValidImplyGrant_A	403733496	229582	0	0
ReqAndReadyImplyGrant_A	403733496	229582	0	0
ReqImpliesValid_A	403733496	549712	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	229582	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	229582	0	0
T1	4226	8	0	0
T2	1009	7	0	0
T3	499471	87	0	0
T7	413184	8	0	0
T8	20360	196	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	25	0	0
T12	163674	113	0	0
T13	412892	601	0	0
T15	0	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	229582	0	0
T1	4226	8	0	0
T2	1009	7	0	0
T3	499471	87	0	0
T7	413184	8	0	0
T8	20360	196	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	25	0	0
T12	163674	113	0	0
T13	412892	601	0	0
T15	0	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	229582	0	0
T1	4226	8	0	0
T2	1009	7	0	0
T3	499471	87	0	0
T7	413184	8	0	0
T8	20360	196	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	25	0	0
T12	163674	113	0	0
T13	412892	601	0	0
T15	0	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2985744	0	0
T1	4226	73	0	0
T2	1009	8	0	0
T3	499471	352	0	0
T7	413184	2358	0	0
T8	20360	196	0	0
T9	266150	1	0	0
T10	34477	195	0	0
T11	538030	7682	0	0
T12	163674	33664	0	0
T13	412892	4531	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	229582	0	0
T1	4226	8	0	0
T2	1009	7	0	0
T3	499471	87	0	0
T7	413184	8	0	0
T8	20360	196	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	25	0	0
T12	163674	113	0	0
T13	412892	601	0	0
T15	0	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	229582	0	0
T1	4226	8	0	0
T2	1009	7	0	0
T3	499471	87	0	0
T7	413184	8	0	0
T8	20360	196	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	25	0	0
T12	163674	113	0	0
T13	412892	601	0	0
T15	0	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	549712	0	0
T1	4226	8	0	0
T2	1009	7	0	0
T3	499471	108	0	0
T7	413184	8	0	0
T8	20360	200	0	0
T9	266150	0	0	0
T10	34477	1133	0	0
T11	538030	352	0	0
T12	163674	3074	0	0
T13	412892	703	0	0
T15	0	198	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	229582	0	0
T1	4226	8	0	0
T2	1009	7	0	0
T3	499471	87	0	0
T7	413184	8	0	0
T8	20360	196	0	0
T9	266150	0	0	0
T10	34477	663	0	0
T11	538030	25	0	0
T12	163674	113	0	0
T13	412892	601	0	0
T15	0	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	219307	0	0
GntImpliesValid_A	403733496	219307	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	219307	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2914430	0	0
ReadyAndValidImplyGrant_A	403733496	219307	0	0
ReqAndReadyImplyGrant_A	403733496	219307	0	0
ReqImpliesValid_A	403733496	541231	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	219307	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	219307	0	0
T1	4226	7	0	0
T2	1009	7	0	0
T3	499471	74	0	0
T7	413184	9	0	0
T8	20360	195	0	0
T9	266150	531	0	0
T10	34477	1610	0	0
T11	538030	22	0	0
T12	163674	129	0	0
T13	412892	498	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	219307	0	0
T1	4226	7	0	0
T2	1009	7	0	0
T3	499471	74	0	0
T7	413184	9	0	0
T8	20360	195	0	0
T9	266150	531	0	0
T10	34477	1610	0	0
T11	538030	22	0	0
T12	163674	129	0	0
T13	412892	498	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	219307	0	0
T1	4226	7	0	0
T2	1009	7	0	0
T3	499471	74	0	0
T7	413184	9	0	0
T8	20360	195	0	0
T9	266150	531	0	0
T10	34477	1610	0	0
T11	538030	22	0	0
T12	163674	129	0	0
T13	412892	498	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2914430	0	0
T1	4226	40	0	0
T2	1009	8	0	0
T3	499471	280	0	0
T7	413184	1272	0	0
T8	20360	191	0	0
T9	266150	1770	0	0
T10	34477	813	0	0
T11	538030	6008	0	0
T12	163674	48706	0	0
T13	412892	3910	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	219307	0	0
T1	4226	7	0	0
T2	1009	7	0	0
T3	499471	74	0	0
T7	413184	9	0	0
T8	20360	195	0	0
T9	266150	531	0	0
T10	34477	1610	0	0
T11	538030	22	0	0
T12	163674	129	0	0
T13	412892	498	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	219307	0	0
T1	4226	7	0	0
T2	1009	7	0	0
T3	499471	74	0	0
T7	413184	9	0	0
T8	20360	195	0	0
T9	266150	531	0	0
T10	34477	1610	0	0
T11	538030	22	0	0
T12	163674	129	0	0
T13	412892	498	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	541231	0	0
T1	4226	7	0	0
T2	1009	7	0	0
T3	499471	86	0	0
T7	413184	9	0	0
T8	20360	204	0	0
T9	266150	1241	0	0
T10	34477	2409	0	0
T11	538030	126	0	0
T12	163674	1715	0	0
T13	412892	616	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	219307	0	0
T1	4226	7	0	0
T2	1009	7	0	0
T3	499471	74	0	0
T7	413184	9	0	0
T8	20360	195	0	0
T9	266150	531	0	0
T10	34477	1610	0	0
T11	538030	22	0	0
T12	163674	129	0	0
T13	412892	498	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	208329	0	0
GntImpliesValid_A	403733496	208329	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	208329	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2946006	0	0
ReadyAndValidImplyGrant_A	403733496	208329	0	0
ReqAndReadyImplyGrant_A	403733496	208329	0	0
ReqImpliesValid_A	403733496	525358	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	208329	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208329	0	0
T1	4226	6	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	11	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	40	0	0
T12	163674	100	0	0
T13	412892	462	0	0
T14	0	906	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208329	0	0
T1	4226	6	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	11	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	40	0	0
T12	163674	100	0	0
T13	412892	462	0	0
T14	0	906	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208329	0	0
T1	4226	6	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	11	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	40	0	0
T12	163674	100	0	0
T13	412892	462	0	0
T14	0	906	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2946006	0	0
T1	4226	23	0	0
T2	1009	7	0	0
T3	499471	349	0	0
T7	413184	1865	0	0
T8	20360	168	0	0
T9	266150	1	0	0
T10	34477	97	0	0
T11	538030	14197	0	0
T12	163674	33359	0	0
T13	412892	3748	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208329	0	0
T1	4226	6	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	11	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	40	0	0
T12	163674	100	0	0
T13	412892	462	0	0
T14	0	906	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208329	0	0
T1	4226	6	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	11	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	40	0	0
T12	163674	100	0	0
T13	412892	462	0	0
T14	0	906	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	525358	0	0
T1	4226	11	0	0
T2	1009	6	0	0
T3	499471	90	0	0
T7	413184	692	0	0
T8	20360	169	0	0
T9	266150	0	0	0
T10	34477	99	0	0
T11	538030	663	0	0
T12	163674	729	0	0
T13	412892	504	0	0
T14	0	1742	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208329	0	0
T1	4226	6	0	0
T2	1009	6	0	0
T3	499471	72	0	0
T7	413184	11	0	0
T8	20360	166	0	0
T9	266150	0	0	0
T10	34477	97	0	0
T11	538030	40	0	0
T12	163674	100	0	0
T13	412892	462	0	0
T14	0	906	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	208273	0	0
GntImpliesValid_A	403733496	208273	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	208273	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2993858	0	0
ReadyAndValidImplyGrant_A	403733496	208273	0	0
ReqAndReadyImplyGrant_A	403733496	208273	0	0
ReqImpliesValid_A	403733496	510844	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	208273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208273	0	0
T1	4226	5	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	461	0	0
T10	34477	600	0	0
T11	538030	49	0	0
T12	163674	153	0	0
T13	412892	471	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208273	0	0
T1	4226	5	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	461	0	0
T10	34477	600	0	0
T11	538030	49	0	0
T12	163674	153	0	0
T13	412892	471	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208273	0	0
T1	4226	5	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	461	0	0
T10	34477	600	0	0
T11	538030	49	0	0
T12	163674	153	0	0
T13	412892	471	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2993858	0	0
T1	4226	38	0	0
T2	1009	5	0	0
T3	499471	324	0	0
T7	413184	1520	0	0
T8	20360	183	0	0
T9	266150	1555	0	0
T10	34477	111	0	0
T11	538030	14655	0	0
T12	163674	47765	0	0
T13	412892	3423	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208273	0	0
T1	4226	5	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	461	0	0
T10	34477	600	0	0
T11	538030	49	0	0
T12	163674	153	0	0
T13	412892	471	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208273	0	0
T1	4226	5	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	461	0	0
T10	34477	600	0	0
T11	538030	49	0	0
T12	163674	153	0	0
T13	412892	471	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	510844	0	0
T1	4226	5	0	0
T2	1009	4	0	0
T3	499471	87	0	0
T7	413184	158	0	0
T8	20360	184	0	0
T9	266150	1168	0	0
T10	34477	1091	0	0
T11	538030	2112	0	0
T12	163674	4014	0	0
T13	412892	526	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	208273	0	0
T1	4226	5	0	0
T2	1009	4	0	0
T3	499471	78	0	0
T7	413184	6	0	0
T8	20360	181	0	0
T9	266150	461	0	0
T10	34477	600	0	0
T11	538030	49	0	0
T12	163674	153	0	0
T13	412892	471	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	202293	0	0
GntImpliesValid_A	403733496	202293	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	202293	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2941765	0	0
ReadyAndValidImplyGrant_A	403733496	202293	0	0
ReqAndReadyImplyGrant_A	403733496	202293	0	0
ReqImpliesValid_A	403733496	522796	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	202293	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	202293	0	0
T1	4226	11	0	0
T2	1009	8	0	0
T3	499471	77	0	0
T7	413184	7	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	110	0	0
T11	538030	29	0	0
T12	163674	127	0	0
T13	412892	494	0	0
T14	0	476	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	202293	0	0
T1	4226	11	0	0
T2	1009	8	0	0
T3	499471	77	0	0
T7	413184	7	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	110	0	0
T11	538030	29	0	0
T12	163674	127	0	0
T13	412892	494	0	0
T14	0	476	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	202293	0	0
T1	4226	11	0	0
T2	1009	8	0	0
T3	499471	77	0	0
T7	413184	7	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	110	0	0
T11	538030	29	0	0
T12	163674	127	0	0
T13	412892	494	0	0
T14	0	476	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2941765	0	0
T1	4226	80	0	0
T2	1009	8	0	0
T3	499471	330	0	0
T7	413184	2115	0	0
T8	20360	182	0	0
T9	266150	1	0	0
T10	34477	110	0	0
T11	538030	10583	0	0
T12	163674	39582	0	0
T13	412892	3606	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	202293	0	0
T1	4226	11	0	0
T2	1009	8	0	0
T3	499471	77	0	0
T7	413184	7	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	110	0	0
T11	538030	29	0	0
T12	163674	127	0	0
T13	412892	494	0	0
T14	0	476	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	202293	0	0
T1	4226	11	0	0
T2	1009	8	0	0
T3	499471	77	0	0
T7	413184	7	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	110	0	0
T11	538030	29	0	0
T12	163674	127	0	0
T13	412892	494	0	0
T14	0	476	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	522796	0	0
T1	4226	11	0	0
T2	1009	9	0	0
T3	499471	86	0	0
T7	413184	7	0	0
T8	20360	191	0	0
T9	266150	0	0	0
T10	34477	112	0	0
T11	538030	662	0	0
T12	163674	2119	0	0
T13	412892	556	0	0
T14	0	951	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	202293	0	0
T1	4226	11	0	0
T2	1009	8	0	0
T3	499471	77	0	0
T7	413184	7	0	0
T8	20360	184	0	0
T9	266150	0	0	0
T10	34477	110	0	0
T11	538030	29	0	0
T12	163674	127	0	0
T13	412892	494	0	0
T14	0	476	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	220340	0	0
GntImpliesValid_A	403733496	220340	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	220340	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	2918416	0	0
ReadyAndValidImplyGrant_A	403733496	220340	0	0
ReqAndReadyImplyGrant_A	403733496	220340	0	0
ReqImpliesValid_A	403733496	587444	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	0	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	220340	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	220340	0	0
T1	4226	6	0	0
T2	1009	2	0	0
T3	499471	81	0	0
T7	413184	3	0	0
T8	20360	622	0	0
T9	266150	0	0	0
T10	34477	638	0	0
T11	538030	35	0	0
T12	163674	93	0	0
T13	412892	941	0	0
T15	0	179	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	220340	0	0
T1	4226	6	0	0
T2	1009	2	0	0
T3	499471	81	0	0
T7	413184	3	0	0
T8	20360	622	0	0
T9	266150	0	0	0
T10	34477	638	0	0
T11	538030	35	0	0
T12	163674	93	0	0
T13	412892	941	0	0
T15	0	179	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	220340	0	0
T1	4226	6	0	0
T2	1009	2	0	0
T3	499471	81	0	0
T7	413184	3	0	0
T8	20360	622	0	0
T9	266150	0	0	0
T10	34477	638	0	0
T11	538030	35	0	0
T12	163674	93	0	0
T13	412892	941	0	0
T15	0	179	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2918416	0	0
T1	4226	68	0	0
T2	1009	3	0	0
T3	499471	329	0	0
T7	413184	1144	0	0
T8	20360	559	0	0
T9	266150	1	0	0
T10	34477	112	0	0
T11	538030	11916	0	0
T12	163674	28501	0	0
T13	412892	6012	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	220340	0	0
T1	4226	6	0	0
T2	1009	2	0	0
T3	499471	81	0	0
T7	413184	3	0	0
T8	20360	622	0	0
T9	266150	0	0	0
T10	34477	638	0	0
T11	538030	35	0	0
T12	163674	93	0	0
T13	412892	941	0	0
T15	0	179	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	220340	0	0
T1	4226	6	0	0
T2	1009	2	0	0
T3	499471	81	0	0
T7	413184	3	0	0
T8	20360	622	0	0
T9	266150	0	0	0
T10	34477	638	0	0
T11	538030	35	0	0
T12	163674	93	0	0
T13	412892	941	0	0
T15	0	179	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	587444	0	0
T1	4226	6	0	0
T2	1009	2	0	0
T3	499471	96	0	0
T7	413184	3	0	0
T8	20360	690	0	0
T9	266150	0	0	0
T10	34477	1166	0	0
T11	538030	1388	0	0
T12	163674	961	0	0
T13	412892	1685	0	0
T15	0	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	220340	0	0
T1	4226	6	0	0
T2	1009	2	0	0
T3	499471	81	0	0
T7	413184	3	0	0
T8	20360	622	0	0
T9	266150	0	0	0
T10	34477	638	0	0
T11	538030	35	0	0
T12	163674	93	0	0
T13	412892	941	0	0
T15	0	179	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	854545	0	0
GntImpliesValid_A	403733496	854545	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	854545	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	11204225	0	0
ReadyAndValidImplyGrant_A	403733496	854545	0	0
ReqAndReadyImplyGrant_A	403733496	854545	0	0
ReqImpliesValid_A	403733496	2237251	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	14780	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	854545	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	854545	0	0
T1	4226	14	0	0
T2	1009	21	0	0
T3	499471	261	0	0
T7	413184	49	0	0
T8	20360	1292	0	0
T9	266150	447	0	0
T10	34477	1890	0	0
T11	538030	151	0	0
T12	163674	446	0	0
T13	412892	3297	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	854545	0	0
T1	4226	14	0	0
T2	1009	21	0	0
T3	499471	261	0	0
T7	413184	49	0	0
T8	20360	1292	0	0
T9	266150	447	0	0
T10	34477	1890	0	0
T11	538030	151	0	0
T12	163674	446	0	0
T13	412892	3297	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	854545	0	0
T1	4226	14	0	0
T2	1009	21	0	0
T3	499471	261	0	0
T7	413184	49	0	0
T8	20360	1292	0	0
T9	266150	447	0	0
T10	34477	1890	0	0
T11	538030	151	0	0
T12	163674	446	0	0
T13	412892	3297	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	11204225	0	0
T1	4226	110	0	0
T2	1009	1	0	0
T3	499471	810	0	0
T7	413184	16039	0	0
T8	20360	5	0	0
T9	266150	1415	0	0
T10	34477	2	0	0
T11	538030	52882	0	0
T12	163674	136802	0	0
T13	412892	18146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	854545	0	0
T1	4226	14	0	0
T2	1009	21	0	0
T3	499471	261	0	0
T7	413184	49	0	0
T8	20360	1292	0	0
T9	266150	447	0	0
T10	34477	1890	0	0
T11	538030	151	0	0
T12	163674	446	0	0
T13	412892	3297	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	854545	0	0
T1	4226	14	0	0
T2	1009	21	0	0
T3	499471	261	0	0
T7	413184	49	0	0
T8	20360	1292	0	0
T9	266150	447	0	0
T10	34477	1890	0	0
T11	538030	151	0	0
T12	163674	446	0	0
T13	412892	3297	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	2237251	0	0
T1	4226	19	0	0
T2	1009	21	0	0
T3	499471	308	0	0
T7	413184	1525	0	0
T8	20360	1292	0	0
T9	266150	620	0	0
T10	34477	1890	0	0
T11	538030	6210	0	0
T12	163674	10404	0	0
T13	412892	5266	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	14780	0	900
T4	211217	0	0	1
T8	20360	150	0	1
T9	266150	0	0	1
T10	34477	173	0	1
T11	538030	0	0	1
T12	163674	0	0	1
T13	412892	23	0	1
T14	20007	308	0	1
T15	13304	8	0	1
T16	331774	2	0	1
T17	0	16	0	0
T18	0	3	0	0
T19	0	6	0	0
T20	0	418	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	854545	0	0
T1	4226	14	0	0
T2	1009	21	0	0
T3	499471	261	0	0
T7	413184	49	0	0
T8	20360	1292	0	0
T9	266150	447	0	0
T10	34477	1890	0	0
T11	538030	151	0	0
T12	163674	446	0	0
T13	412892	3297	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403733496	403619028	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	403733496	848105	0	0
GntImpliesValid_A	403733496	848105	0	0
GrantKnown_A	403733496	403619028	0	0
IdxKnown_A	403733496	403619028	0	0
IndexIsCorrect_A	403733496	848105	0	0
LockArbDecision_A	403733496	0	0	0
NoReadyValidNoGrant_A	403733496	339349264	0	0
ReadyAndValidImplyGrant_A	403733496	848105	0	0
ReqAndReadyImplyGrant_A	403733496	848105	0	0
ReqImpliesValid_A	403733496	12923849	0	0
ReqStaysHighUntilGranted0_M	403733496	0	0	0
RoundRobin_A	403733496	29634	0	900
ValidKnown_A	403733496	403619028	0	0
gen_data_port_assertion.DataFlow_A	403733496	848105	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	848105	0	0
T1	4226	23	0	0
T2	1009	17	0	0
T3	499471	248	0	0
T7	413184	60	0	0
T8	20360	1035	0	0
T9	266150	464	0	0
T10	34477	2654	0	0
T11	538030	139	0	0
T12	163674	456	0	0
T13	412892	2547	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	848105	0	0
T1	4226	23	0	0
T2	1009	17	0	0
T3	499471	248	0	0
T7	413184	60	0	0
T8	20360	1035	0	0
T9	266150	464	0	0
T10	34477	2654	0	0
T11	538030	139	0	0
T12	163674	456	0	0
T13	412892	2547	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	848105	0	0
T1	4226	23	0	0
T2	1009	17	0	0
T3	499471	248	0	0
T7	413184	60	0	0
T8	20360	1035	0	0
T9	266150	464	0	0
T10	34477	2654	0	0
T11	538030	139	0	0
T12	163674	456	0	0
T13	412892	2547	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	339349264	0	0
T1	4226	3631	0	0
T2	1009	1	0	0
T3	499471	415136	0	0
T7	413184	391347	0	0
T8	20360	1	0	0
T9	266150	221608	0	0
T10	34477	1	0	0
T11	538030	462284	0	0
T12	163674	147289	0	0
T13	412892	357778	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	848105	0	0
T1	4226	23	0	0
T2	1009	17	0	0
T3	499471	248	0	0
T7	413184	60	0	0
T8	20360	1035	0	0
T9	266150	464	0	0
T10	34477	2654	0	0
T11	538030	139	0	0
T12	163674	456	0	0
T13	412892	2547	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	848105	0	0
T1	4226	23	0	0
T2	1009	17	0	0
T3	499471	248	0	0
T7	413184	60	0	0
T8	20360	1035	0	0
T9	266150	464	0	0
T10	34477	2654	0	0
T11	538030	139	0	0
T12	163674	456	0	0
T13	412892	2547	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	12923849	0	0
T1	4226	196	0	0
T2	1009	17	0	0
T3	499471	1111	0	0
T7	413184	21033	0	0
T8	20360	1035	0	0
T9	266150	1998	0	0
T10	34477	2654	0	0
T11	538030	47919	0	0
T12	163674	160941	0	0
T13	412892	20129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	29634	0	900
T4	211217	0	0	1
T8	20360	7	0	1
T9	266150	0	0	1
T10	34477	658	0	1
T11	538030	0	0	1
T12	163674	0	0	1
T13	412892	1	0	1
T14	20007	0	0	1
T15	13304	10	0	1
T16	331774	5	0	1
T17	0	12	0	0
T18	0	7	0	0
T19	0	1	0	0
T20	0	19	0	0
T21	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	403619028	0	0
T1	4226	4176	0	0
T2	1009	944	0	0
T3	499471	499454	0	0
T7	413184	413136	0	0
T8	20360	19671	0	0
T9	266150	266147	0	0
T10	34477	34414	0	0
T11	538030	537973	0	0
T12	163674	163670	0	0
T13	412892	412780	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403733496	848105	0	0
T1	4226	23	0	0
T2	1009	17	0	0
T3	499471	248	0	0
T7	413184	60	0	0
T8	20360	1035	0	0
T9	266150	464	0	0
T10	34477	2654	0	0
T11	538030	139	0	0
T12	163674	456	0	0
T13	412892	2547	0	0