Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1519509	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241296

1

T1

413

T2

18

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	597857	1			T1	1067		T2	53		T3	16
values[0x0]	564782	1			T1	1017		T2	53		T3	8
values[0x1]	598166	1			T1	1058		T2	44		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1174147	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

586658

1

T1

999

T2

45

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27372	1			T1	37		T2	3		T3	4
valid_sources[0x01]	27523	1			T1	36		T2	5		T9	9
valid_sources[0x02]	25793	1			T1	35		T2	2		T3	2
valid_sources[0x03]	27939	1			T1	70		T2	2		T7	9
valid_sources[0x04]	27103	1			T1	66		T2	8		T3	1
valid_sources[0x05]	28711	1			T1	49		T2	2		T9	16
valid_sources[0x06]	27624	1			T1	60		T2	2		T3	1
valid_sources[0x07]	28030	1			T1	46		T2	3		T7	10
valid_sources[0x08]	28537	1			T1	54		T2	2		T3	1
valid_sources[0x09]	27097	1			T1	36		T2	4		T7	7
valid_sources[0x0a]	27380	1			T1	52		T2	3		T3	1
valid_sources[0x0b]	27053	1			T1	26		T2	2		T9	22
valid_sources[0x0c]	27206	1			T1	39		T2	3		T9	22
valid_sources[0x0d]	28884	1			T1	51		T2	2		T3	1
valid_sources[0x0e]	28528	1			T1	55		T2	1		T3	1
valid_sources[0x0f]	27482	1			T1	33		T2	3		T3	2
valid_sources[0x10]	26799	1			T1	26		T2	1		T3	1
valid_sources[0x11]	27717	1			T1	41		T2	1		T9	19
valid_sources[0x12]	28418	1			T1	63		T2	1		T7	41
valid_sources[0x13]	27680	1			T1	44		T2	3		T3	1
valid_sources[0x14]	27151	1			T1	24		T7	33		T9	18
valid_sources[0x15]	27941	1			T1	46		T2	3		T3	1
valid_sources[0x16]	27901	1			T1	68		T2	9		T7	12
valid_sources[0x17]	27848	1			T1	58		T3	1		T7	17
valid_sources[0x18]	27554	1			T1	36		T9	17		T10	21
valid_sources[0x19]	28415	1			T1	47		T2	3		T9	22
valid_sources[0x1a]	26600	1			T1	57		T2	3		T3	2
valid_sources[0x1b]	27635	1			T1	31		T2	1		T9	12
valid_sources[0x1c]	27616	1			T1	73		T3	1		T7	46
valid_sources[0x1d]	28406	1			T1	66		T2	2		T3	2
valid_sources[0x1e]	29288	1			T1	51		T2	1		T3	1
valid_sources[0x1f]	27426	1			T1	24		T2	1		T9	29
valid_sources[0x20]	26838	1			T1	40		T2	3		T7	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25634

1

T1

30

T2

1

T7

6

values[0x0]

all_enables

biggest_size

190243

1

T1

336

T2

16

T3

4

values[0x1]

all_enables

biggest_size

25419

1

T1

47

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1534690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248889

1

T1

459

T2

15

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611230	1			T1	1090		T2	45		T3	35
values[0x0]	561626	1			T1	1059		T2	37		T3	1
values[0x1]	610723	1			T1	1115		T2	39		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1177670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

605909

1

T1

1115

T2

40

T3

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28140	1			T1	19		T2	1		T7	12
valid_sources[0x01]	27258	1			T1	47		T7	13		T9	19
valid_sources[0x02]	27948	1			T1	69		T2	4		T3	1
valid_sources[0x03]	28447	1			T1	96		T2	1		T3	1
valid_sources[0x04]	28157	1			T1	46		T3	1		T7	13
valid_sources[0x05]	27279	1			T1	50		T2	2		T3	1
valid_sources[0x06]	27774	1			T1	33		T2	2		T3	1
valid_sources[0x07]	27630	1			T1	36		T2	5		T7	7
valid_sources[0x08]	27995	1			T1	55		T2	1		T3	1
valid_sources[0x09]	27717	1			T1	58		T3	3		T7	6
valid_sources[0x0a]	28069	1			T1	28		T3	1		T7	12
valid_sources[0x0b]	27044	1			T1	72		T2	2		T7	11
valid_sources[0x0c]	28042	1			T1	28		T2	1		T7	7
valid_sources[0x0d]	28612	1			T1	50		T2	7		T7	7
valid_sources[0x0e]	28622	1			T1	48		T2	4		T3	7
valid_sources[0x0f]	27506	1			T1	69		T2	4		T7	6
valid_sources[0x10]	27237	1			T1	41		T7	10		T9	17
valid_sources[0x11]	27943	1			T1	41		T3	1		T7	8
valid_sources[0x12]	28176	1			T1	60		T3	1		T7	13
valid_sources[0x13]	27878	1			T1	41		T7	8		T9	18
valid_sources[0x14]	27578	1			T1	73		T2	7		T7	8
valid_sources[0x15]	27410	1			T1	26		T7	6		T9	24
valid_sources[0x16]	28163	1			T1	66		T2	6		T3	1
valid_sources[0x17]	28133	1			T1	66		T3	4		T7	14
valid_sources[0x18]	28064	1			T1	27		T7	10		T9	22
valid_sources[0x19]	27887	1			T1	33		T2	1		T3	1
valid_sources[0x1a]	28228	1			T1	36		T2	8		T3	2
valid_sources[0x1b]	28404	1			T1	38		T2	1		T3	2
valid_sources[0x1c]	27933	1			T1	26		T2	2		T3	1
valid_sources[0x1d]	27876	1			T1	40		T2	1		T3	1
valid_sources[0x1e]	28150	1			T1	76		T7	6		T9	24
valid_sources[0x1f]	28115	1			T1	47		T2	2		T3	1
valid_sources[0x20]	28122	1			T1	65		T2	1		T7	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26113

1

T1

41

T2

3

T3

2

values[0x0]

all_enables

biggest_size

196616

1

T1

378

T2

11

T3

1

values[0x1]

all_enables

biggest_size

26160

1

T1

40

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1533167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241828

1

T1

446

T2

26

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	603454	1			T1	1223		T2	69		T3	25
values[0x0]	568477	1			T1	1069		T2	68		T3	4
values[0x1]	603064	1			T1	1141		T2	57		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1184526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

590469

1

T1

1130

T2

56

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27307	1			T1	49		T2	9		T3	2
valid_sources[0x01]	28579	1			T1	48		T3	2		T7	4
valid_sources[0x02]	27783	1			T1	49		T2	1		T7	9
valid_sources[0x03]	28179	1			T1	53		T2	3		T7	9
valid_sources[0x04]	26970	1			T1	45		T2	3		T7	11
valid_sources[0x05]	27374	1			T1	43		T3	2		T7	13
valid_sources[0x06]	27522	1			T1	54		T2	4		T7	12
valid_sources[0x07]	27242	1			T1	55		T2	6		T7	4
valid_sources[0x08]	28122	1			T1	59		T3	3		T7	13
valid_sources[0x09]	28092	1			T1	60		T2	3		T3	1
valid_sources[0x0a]	27272	1			T1	45		T3	5		T7	7
valid_sources[0x0b]	27149	1			T1	59		T2	10		T7	11
valid_sources[0x0c]	27146	1			T1	69		T3	1		T7	7
valid_sources[0x0d]	28916	1			T1	60		T3	2		T7	7
valid_sources[0x0e]	27630	1			T1	63		T2	1		T3	1
valid_sources[0x0f]	28046	1			T1	46		T2	11		T3	1
valid_sources[0x10]	28001	1			T1	51		T2	3		T7	7
valid_sources[0x11]	28027	1			T1	43		T7	7		T9	24
valid_sources[0x12]	28409	1			T1	84		T2	2		T7	7
valid_sources[0x13]	27522	1			T1	51		T2	8		T3	1
valid_sources[0x14]	27292	1			T1	39		T2	4		T7	9
valid_sources[0x15]	27561	1			T1	55		T2	9		T7	9
valid_sources[0x16]	27739	1			T1	44		T2	5		T7	7
valid_sources[0x17]	27778	1			T1	53		T2	1		T3	1
valid_sources[0x18]	28355	1			T1	63		T2	1		T7	11
valid_sources[0x19]	28018	1			T1	53		T2	1		T7	6
valid_sources[0x1a]	28633	1			T1	62		T2	3		T7	10
valid_sources[0x1b]	27944	1			T1	50		T2	5		T7	10
valid_sources[0x1c]	28110	1			T1	50		T2	4		T3	1
valid_sources[0x1d]	27553	1			T1	44		T2	1		T3	2
valid_sources[0x1e]	27607	1			T1	52		T3	2		T7	9
valid_sources[0x1f]	28142	1			T1	65		T2	1		T3	1
valid_sources[0x20]	28780	1			T1	47		T2	3		T7	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25354

1

T1

44

T3

2

T7

10

values[0x0]

all_enables

biggest_size

191145

1

T1

348

T2

23

T3

4

values[0x1]

all_enables

biggest_size

25329

1

T1

54

T2

3

T3

1