Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7936918	0	0
GntImpliesValid_A	2147483647	7936918	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7936918	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	468525276	0	0
ReadyAndValidImplyGrant_A	2147483647	7936918	0	0
ReqAndReadyImplyGrant_A	2147483647	7936918	0	0
ReqImpliesValid_A	2147483647	37812123	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42771	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7936918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3131208	3129384	0	0
T2	58896	57936	0	0
T3	149160	141984	0	0
T7	13765704	13765104	0	0
T8	2608800	2608680	0	0
T9	3947856	3945576	0	0
T10	147096	146256	0	0
T11	13530144	13524648	0	0
T12	5035440	5034024	0	0
T13	4532904	4532880	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7936918	0	0
T1	1696071	9838	0	0
T2	58896	465	0	0
T3	149160	3649	0	0
T7	13765704	1752	0	0
T8	2608800	3768	0	0
T9	3947856	76033	0	0
T10	147096	2466	0	0
T11	13530144	52423	0	0
T12	5035440	367	0	0
T13	4532904	5129	0	0
T14	159082	4234	0	0
T15	0	2004	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7936918	0	0
T1	1696071	9838	0	0
T2	58896	465	0	0
T3	149160	3649	0	0
T7	13765704	1752	0	0
T8	2608800	3768	0	0
T9	3947856	76033	0	0
T10	147096	2466	0	0
T11	13530144	52423	0	0
T12	5035440	367	0	0
T13	4532904	5129	0	0
T14	159082	4234	0	0
T15	0	2004	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3131208	3129384	0	0
T2	58896	57936	0	0
T3	149160	141984	0	0
T7	13765704	13765104	0	0
T8	2608800	2608680	0	0
T9	3947856	3945576	0	0
T10	147096	146256	0	0
T11	13530144	13524648	0	0
T12	5035440	5034024	0	0
T13	4532904	4532880	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3131208	3129384	0	0
T2	58896	57936	0	0
T3	149160	141984	0	0
T7	13765704	13765104	0	0
T8	2608800	2608680	0	0
T9	3947856	3945576	0	0
T10	147096	146256	0	0
T11	13530144	13524648	0	0
T12	5035440	5034024	0	0
T13	4532904	4532880	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7936918	0	0
T1	1696071	9838	0	0
T2	58896	465	0	0
T3	149160	3649	0	0
T7	13765704	1752	0	0
T8	2608800	3768	0	0
T9	3947856	76033	0	0
T10	147096	2466	0	0
T11	13530144	52423	0	0
T12	5035440	367	0	0
T13	4532904	5129	0	0
T14	159082	4234	0	0
T15	0	2004	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	468525276	0	0
T1	3131208	136111	0	0
T2	58896	811	0	0
T3	149160	3160	0	0
T7	13765704	483553	0	0
T8	2608800	923204	0	0
T9	3947856	93713	0	0
T10	147096	2953	0	0
T11	13530144	822963	0	0
T12	5035440	176492	0	0
T13	4532904	173188	0	0
T14	0	3958	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7936918	0	0
T1	1696071	9838	0	0
T2	58896	465	0	0
T3	149160	3649	0	0
T7	13765704	1752	0	0
T8	2608800	3768	0	0
T9	3947856	76033	0	0
T10	147096	2466	0	0
T11	13530144	52423	0	0
T12	5035440	367	0	0
T13	4532904	5129	0	0
T14	159082	4234	0	0
T15	0	2004	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7936918	0	0
T1	1696071	9838	0	0
T2	58896	465	0	0
T3	149160	3649	0	0
T7	13765704	1752	0	0
T8	2608800	3768	0	0
T9	3947856	76033	0	0
T10	147096	2466	0	0
T11	13530144	52423	0	0
T12	5035440	367	0	0
T13	4532904	5129	0	0
T14	159082	4234	0	0
T15	0	2004	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37812123	0	0
T1	1696071	109434	0	0
T2	58896	575	0	0
T3	149160	4295	0	0
T7	13765704	2983	0	0
T8	2608800	6740	0	0
T9	3947856	107040	0	0
T10	147096	2841	0	0
T11	13530144	164362	0	0
T12	5035440	586	0	0
T13	4532904	11865	0	0
T14	159082	5422	0	0
T15	0	41534	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42771	0	21600
T1	130467	22	0	1
T2	2454	0	0	1
T3	12430	7	0	2
T7	1147142	0	0	2
T8	217400	0	0	2
T9	328988	1568	0	2
T10	12258	12	0	2
T11	1127512	26	0	2
T12	419620	0	0	2
T13	377742	0	0	2
T14	14462	27	0	1
T15	348011	1	0	1
T16	0	10	0	0
T17	0	5	0	0
T18	0	28	0	0
T19	0	1	0	0
T20	0	10	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3131208	3129384	0	0
T2	58896	57936	0	0
T3	149160	141984	0	0
T7	13765704	13765104	0	0
T8	2608800	2608680	0	0
T9	3947856	3945576	0	0
T10	147096	146256	0	0
T11	13530144	13524648	0	0
T12	5035440	5034024	0	0
T13	4532904	4532880	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7936918	0	0
T1	1696071	9838	0	0
T2	58896	465	0	0
T3	149160	3649	0	0
T7	13765704	1752	0	0
T8	2608800	3768	0	0
T9	3947856	76033	0	0
T10	147096	2466	0	0
T11	13530144	52423	0	0
T12	5035440	367	0	0
T13	4532904	5129	0	0
T14	159082	4234	0	0
T15	0	2004	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	885307	0	0
GntImpliesValid_A	418504577	885307	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	885307	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	13423795	0	0
ReadyAndValidImplyGrant_A	418504577	885307	0	0
ReqAndReadyImplyGrant_A	418504577	885307	0	0
ReqImpliesValid_A	418504577	2688983	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	885307	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	885307	0	0
T1	130467	681	0	0
T2	2454	41	0	0
T3	6215	428	0	0
T7	573571	219	0	0
T8	108700	437	0	0
T9	164494	10112	0	0
T10	6129	260	0	0
T11	563756	5785	0	0
T12	209810	39	0	0
T13	188871	464	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	885307	0	0
T1	130467	681	0	0
T2	2454	41	0	0
T3	6215	428	0	0
T7	573571	219	0	0
T8	108700	437	0	0
T9	164494	10112	0	0
T10	6129	260	0	0
T11	563756	5785	0	0
T12	209810	39	0	0
T13	188871	464	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	885307	0	0
T1	130467	681	0	0
T2	2454	41	0	0
T3	6215	428	0	0
T7	573571	219	0	0
T8	108700	437	0	0
T9	164494	10112	0	0
T10	6129	260	0	0
T11	563756	5785	0	0
T12	209810	39	0	0
T13	188871	464	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	13423795	0	0
T1	130467	4681	0	0
T2	2454	30	0	0
T3	6215	347	0	0
T7	573571	840	0	0
T8	108700	1761	0	0
T9	164494	6735	0	0
T10	6129	219	0	0
T11	563756	40090	0	0
T12	209810	154	0	0
T13	188871	1886	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	885307	0	0
T1	130467	681	0	0
T2	2454	41	0	0
T3	6215	428	0	0
T7	573571	219	0	0
T8	108700	437	0	0
T9	164494	10112	0	0
T10	6129	260	0	0
T11	563756	5785	0	0
T12	209810	39	0	0
T13	188871	464	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	885307	0	0
T1	130467	681	0	0
T2	2454	41	0	0
T3	6215	428	0	0
T7	573571	219	0	0
T8	108700	437	0	0
T9	164494	10112	0	0
T10	6129	260	0	0
T11	563756	5785	0	0
T12	209810	39	0	0
T13	188871	464	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	2688983	0	0
T1	130467	1127	0	0
T2	2454	53	0	0
T3	6215	515	0	0
T7	573571	299	0	0
T8	108700	574	0	0
T9	164494	13491	0	0
T10	6129	302	0	0
T11	563756	13344	0	0
T12	209810	49	0	0
T13	188871	700	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	885307	0	0
T1	130467	681	0	0
T2	2454	41	0	0
T3	6215	428	0	0
T7	573571	219	0	0
T8	108700	437	0	0
T9	164494	10112	0	0
T10	6129	260	0	0
T11	563756	5785	0	0
T12	209810	39	0	0
T13	188871	464	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	893672	0	0
GntImpliesValid_A	418504577	893672	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	893672	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	13335104	0	0
ReadyAndValidImplyGrant_A	418504577	893672	0	0
ReqAndReadyImplyGrant_A	418504577	893672	0	0
ReqImpliesValid_A	418504577	2727035	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	893672	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	893672	0	0
T1	130467	1383	0	0
T2	2454	46	0	0
T3	6215	398	0	0
T7	573571	175	0	0
T8	108700	443	0	0
T9	164494	7656	0	0
T10	6129	298	0	0
T11	563756	5095	0	0
T12	209810	39	0	0
T13	188871	424	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	893672	0	0
T1	130467	1383	0	0
T2	2454	46	0	0
T3	6215	398	0	0
T7	573571	175	0	0
T8	108700	443	0	0
T9	164494	7656	0	0
T10	6129	298	0	0
T11	563756	5095	0	0
T12	209810	39	0	0
T13	188871	424	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	893672	0	0
T1	130467	1383	0	0
T2	2454	46	0	0
T3	6215	398	0	0
T7	573571	175	0	0
T8	108700	443	0	0
T9	164494	7656	0	0
T10	6129	298	0	0
T11	563756	5095	0	0
T12	209810	39	0	0
T13	188871	424	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	13335104	0	0
T1	130467	5283	0	0
T2	2454	35	0	0
T3	6215	332	0	0
T7	573571	742	0	0
T8	108700	1802	0	0
T9	164494	5888	0	0
T10	6129	242	0	0
T11	563756	35863	0	0
T12	209810	170	0	0
T13	188871	1715	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	893672	0	0
T1	130467	1383	0	0
T2	2454	46	0	0
T3	6215	398	0	0
T7	573571	175	0	0
T8	108700	443	0	0
T9	164494	7656	0	0
T10	6129	298	0	0
T11	563756	5095	0	0
T12	209810	39	0	0
T13	188871	424	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	893672	0	0
T1	130467	1383	0	0
T2	2454	46	0	0
T3	6215	398	0	0
T7	573571	175	0	0
T8	108700	443	0	0
T9	164494	7656	0	0
T10	6129	298	0	0
T11	563756	5095	0	0
T12	209810	39	0	0
T13	188871	424	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	2727035	0	0
T1	130467	8851	0	0
T2	2454	58	0	0
T3	6215	471	0	0
T7	573571	229	0	0
T8	108700	600	0	0
T9	164494	9426	0	0
T10	6129	355	0	0
T11	563756	7566	0	0
T12	209810	48	0	0
T13	188871	563	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	893672	0	0
T1	130467	1383	0	0
T2	2454	46	0	0
T3	6215	398	0	0
T7	573571	175	0	0
T8	108700	443	0	0
T9	164494	7656	0	0
T10	6129	298	0	0
T11	563756	5095	0	0
T12	209810	39	0	0
T13	188871	424	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	226450	0	0
GntImpliesValid_A	418504577	226450	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	226450	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3399239	0	0
ReadyAndValidImplyGrant_A	418504577	226450	0	0
ReqAndReadyImplyGrant_A	418504577	226450	0	0
ReqImpliesValid_A	418504577	644542	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	226450	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226450	0	0
T2	2454	19	0	0
T3	6215	57	0	0
T7	573571	52	0	0
T8	108700	105	0	0
T9	164494	1148	0	0
T10	6129	66	0	0
T11	563756	899	0	0
T12	209810	12	0	0
T13	188871	535	0	0
T14	14462	152	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226450	0	0
T2	2454	19	0	0
T3	6215	57	0	0
T7	573571	52	0	0
T8	108700	105	0	0
T9	164494	1148	0	0
T10	6129	66	0	0
T11	563756	899	0	0
T12	209810	12	0	0
T13	188871	535	0	0
T14	14462	152	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226450	0	0
T2	2454	19	0	0
T3	6215	57	0	0
T7	573571	52	0	0
T8	108700	105	0	0
T9	164494	1148	0	0
T10	6129	66	0	0
T11	563756	899	0	0
T12	209810	12	0	0
T13	188871	535	0	0
T14	14462	152	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3399239	0	0
T1	130467	1	0	0
T2	2454	20	0	0
T3	6215	65	0	0
T7	573571	199	0	0
T8	108700	451	0	0
T9	164494	1121	0	0
T10	6129	63	0	0
T11	563756	6569	0	0
T12	209810	66	0	0
T13	188871	1815	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226450	0	0
T2	2454	19	0	0
T3	6215	57	0	0
T7	573571	52	0	0
T8	108700	105	0	0
T9	164494	1148	0	0
T10	6129	66	0	0
T11	563756	899	0	0
T12	209810	12	0	0
T13	188871	535	0	0
T14	14462	152	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226450	0	0
T2	2454	19	0	0
T3	6215	57	0	0
T7	573571	52	0	0
T8	108700	105	0	0
T9	164494	1148	0	0
T10	6129	66	0	0
T11	563756	899	0	0
T12	209810	12	0	0
T13	188871	535	0	0
T14	14462	152	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	644542	0	0
T2	2454	19	0	0
T3	6215	57	0	0
T7	573571	63	0	0
T8	108700	138	0	0
T9	164494	1177	0	0
T10	6129	70	0	0
T11	563756	1032	0	0
T12	209810	17	0	0
T13	188871	1216	0	0
T14	14462	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226450	0	0
T2	2454	19	0	0
T3	6215	57	0	0
T7	573571	52	0	0
T8	108700	105	0	0
T9	164494	1148	0	0
T10	6129	66	0	0
T11	563756	899	0	0
T12	209810	12	0	0
T13	188871	535	0	0
T14	14462	152	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	224034	0	0
GntImpliesValid_A	418504577	224034	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	224034	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3382296	0	0
ReadyAndValidImplyGrant_A	418504577	224034	0	0
ReqAndReadyImplyGrant_A	418504577	224034	0	0
ReqImpliesValid_A	418504577	643670	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	224034	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	224034	0	0
T2	2454	13	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	100	0	0
T9	164494	2574	0	0
T10	6129	65	0	0
T11	563756	1439	0	0
T12	209810	14	0	0
T13	188871	492	0	0
T14	14462	156	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	224034	0	0
T2	2454	13	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	100	0	0
T9	164494	2574	0	0
T10	6129	65	0	0
T11	563756	1439	0	0
T12	209810	14	0	0
T13	188871	492	0	0
T14	14462	156	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	224034	0	0
T2	2454	13	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	100	0	0
T9	164494	2574	0	0
T10	6129	65	0	0
T11	563756	1439	0	0
T12	209810	14	0	0
T13	188871	492	0	0
T14	14462	156	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3382296	0	0
T1	130467	1	0	0
T2	2454	14	0	0
T3	6215	55	0	0
T7	573571	230	0	0
T8	108700	416	0	0
T9	164494	1977	0	0
T10	6129	64	0	0
T11	563756	10011	0	0
T12	209810	56	0	0
T13	188871	1616	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	224034	0	0
T2	2454	13	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	100	0	0
T9	164494	2574	0	0
T10	6129	65	0	0
T11	563756	1439	0	0
T12	209810	14	0	0
T13	188871	492	0	0
T14	14462	156	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	224034	0	0
T2	2454	13	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	100	0	0
T9	164494	2574	0	0
T10	6129	65	0	0
T11	563756	1439	0	0
T12	209810	14	0	0
T13	188871	492	0	0
T14	14462	156	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	643670	0	0
T2	2454	13	0	0
T3	6215	51	0	0
T7	573571	74	0	0
T8	108700	119	0	0
T9	164494	3173	0	0
T10	6129	67	0	0
T11	563756	3254	0	0
T12	209810	20	0	0
T13	188871	1267	0	0
T14	14462	161	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	224034	0	0
T2	2454	13	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	100	0	0
T9	164494	2574	0	0
T10	6129	65	0	0
T11	563756	1439	0	0
T12	209810	14	0	0
T13	188871	492	0	0
T14	14462	156	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	222615	0	0
GntImpliesValid_A	418504577	222615	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	222615	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	5419358	0	0
ReadyAndValidImplyGrant_A	418504577	222615	0	0
ReqAndReadyImplyGrant_A	418504577	222615	0	0
ReqImpliesValid_A	418504577	1249082	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	222615	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222615	0	0
T1	130467	550	0	0
T2	2454	15	0	0
T3	6215	64	0	0
T7	573571	53	0	0
T8	108700	100	0	0
T9	164494	1153	0	0
T10	6129	86	0	0
T11	563756	926	0	0
T12	209810	14	0	0
T13	188871	0	0	0
T14	0	134	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222615	0	0
T1	130467	550	0	0
T2	2454	15	0	0
T3	6215	64	0	0
T7	573571	53	0	0
T8	108700	100	0	0
T9	164494	1153	0	0
T10	6129	86	0	0
T11	563756	926	0	0
T12	209810	14	0	0
T13	188871	0	0	0
T14	0	134	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222615	0	0
T1	130467	550	0	0
T2	2454	15	0	0
T3	6215	64	0	0
T7	573571	53	0	0
T8	108700	100	0	0
T9	164494	1153	0	0
T10	6129	86	0	0
T11	563756	926	0	0
T12	209810	14	0	0
T13	188871	0	0	0
T14	0	134	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	5419358	0	0
T1	130467	926	0	0
T2	2454	71	0	0
T3	6215	277	0	0
T7	573571	443	0	0
T8	108700	1492	0	0
T9	164494	15490	0	0
T10	6129	485	0	0
T11	563756	13413	0	0
T12	209810	103	0	0
T13	188871	0	0	0
T14	0	673	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222615	0	0
T1	130467	550	0	0
T2	2454	15	0	0
T3	6215	64	0	0
T7	573571	53	0	0
T8	108700	100	0	0
T9	164494	1153	0	0
T10	6129	86	0	0
T11	563756	926	0	0
T12	209810	14	0	0
T13	188871	0	0	0
T14	0	134	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222615	0	0
T1	130467	550	0	0
T2	2454	15	0	0
T3	6215	64	0	0
T7	573571	53	0	0
T8	108700	100	0	0
T9	164494	1153	0	0
T10	6129	86	0	0
T11	563756	926	0	0
T12	209810	14	0	0
T13	188871	0	0	0
T14	0	134	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	1249082	0	0
T1	130467	13619	0	0
T2	2454	20	0	0
T3	6215	64	0	0
T7	573571	99	0	0
T8	108700	277	0	0
T9	164494	2208	0	0
T10	6129	174	0	0
T11	563756	1293	0	0
T12	209810	18	0	0
T13	188871	0	0	0
T14	0	164	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222615	0	0
T1	130467	550	0	0
T2	2454	15	0	0
T3	6215	64	0	0
T7	573571	53	0	0
T8	108700	100	0	0
T9	164494	1153	0	0
T10	6129	86	0	0
T11	563756	926	0	0
T12	209810	14	0	0
T13	188871	0	0	0
T14	0	134	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	220329	0	0
GntImpliesValid_A	418504577	220329	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	220329	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	5832634	0	0
ReadyAndValidImplyGrant_A	418504577	220329	0	0
ReqAndReadyImplyGrant_A	418504577	220329	0	0
ReqImpliesValid_A	418504577	1408569	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	220329	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220329	0	0
T1	130467	490	0	0
T2	2454	16	0	0
T3	6215	47	0	0
T7	573571	49	0	0
T8	108700	102	0	0
T9	164494	2699	0	0
T10	6129	73	0	0
T11	563756	1373	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	0	160	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220329	0	0
T1	130467	490	0	0
T2	2454	16	0	0
T3	6215	47	0	0
T7	573571	49	0	0
T8	108700	102	0	0
T9	164494	2699	0	0
T10	6129	73	0	0
T11	563756	1373	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	0	160	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220329	0	0
T1	130467	490	0	0
T2	2454	16	0	0
T3	6215	47	0	0
T7	573571	49	0	0
T8	108700	102	0	0
T9	164494	2699	0	0
T10	6129	73	0	0
T11	563756	1373	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	0	160	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	5832634	0	0
T1	130467	100	0	0
T2	2454	164	0	0
T3	6215	200	0	0
T7	573571	269	0	0
T8	108700	868	0	0
T9	164494	25141	0	0
T10	6129	277	0	0
T11	563756	32203	0	0
T12	209810	121	0	0
T13	188871	0	0	0
T14	0	776	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220329	0	0
T1	130467	490	0	0
T2	2454	16	0	0
T3	6215	47	0	0
T7	573571	49	0	0
T8	108700	102	0	0
T9	164494	2699	0	0
T10	6129	73	0	0
T11	563756	1373	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	0	160	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220329	0	0
T1	130467	490	0	0
T2	2454	16	0	0
T3	6215	47	0	0
T7	573571	49	0	0
T8	108700	102	0	0
T9	164494	2699	0	0
T10	6129	73	0	0
T11	563756	1373	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	0	160	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	1408569	0	0
T1	130467	9383	0	0
T2	2454	49	0	0
T3	6215	51	0	0
T7	573571	57	0	0
T8	108700	135	0	0
T9	164494	15457	0	0
T10	6129	108	0	0
T11	563756	10234	0	0
T12	209810	38	0	0
T13	188871	0	0	0
T14	0	191	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220329	0	0
T1	130467	490	0	0
T2	2454	16	0	0
T3	6215	47	0	0
T7	573571	49	0	0
T8	108700	102	0	0
T9	164494	2699	0	0
T10	6129	73	0	0
T11	563756	1373	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	0	160	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	213787	0	0
GntImpliesValid_A	418504577	213787	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	213787	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	5698780	0	0
ReadyAndValidImplyGrant_A	418504577	213787	0	0
ReqAndReadyImplyGrant_A	418504577	213787	0	0
ReqImpliesValid_A	418504577	1329701	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	213787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213787	0	0
T1	130467	497	0	0
T2	2454	18	0	0
T3	6215	51	0	0
T7	573571	39	0	0
T8	108700	108	0	0
T9	164494	1190	0	0
T10	6129	67	0	0
T11	563756	945	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213787	0	0
T1	130467	497	0	0
T2	2454	18	0	0
T3	6215	51	0	0
T7	573571	39	0	0
T8	108700	108	0	0
T9	164494	1190	0	0
T10	6129	67	0	0
T11	563756	945	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213787	0	0
T1	130467	497	0	0
T2	2454	18	0	0
T3	6215	51	0	0
T7	573571	39	0	0
T8	108700	108	0	0
T9	164494	1190	0	0
T10	6129	67	0	0
T11	563756	945	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	5698780	0	0
T1	130467	76	0	0
T2	2454	193	0	0
T3	6215	349	0	0
T7	573571	227	0	0
T8	108700	3899	0	0
T9	164494	7481	0	0
T10	6129	385	0	0
T11	563756	20951	0	0
T12	209810	169	0	0
T13	188871	0	0	0
T14	0	1780	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213787	0	0
T1	130467	497	0	0
T2	2454	18	0	0
T3	6215	51	0	0
T7	573571	39	0	0
T8	108700	108	0	0
T9	164494	1190	0	0
T10	6129	67	0	0
T11	563756	945	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213787	0	0
T1	130467	497	0	0
T2	2454	18	0	0
T3	6215	51	0	0
T7	573571	39	0	0
T8	108700	108	0	0
T9	164494	1190	0	0
T10	6129	67	0	0
T11	563756	945	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	1329701	0	0
T1	130467	9788	0	0
T2	2454	46	0	0
T3	6215	58	0	0
T7	573571	43	0	0
T8	108700	535	0	0
T9	164494	1542	0	0
T10	6129	124	0	0
T11	563756	1566	0	0
T12	209810	29	0	0
T13	188871	0	0	0
T14	0	299	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213787	0	0
T1	130467	497	0	0
T2	2454	18	0	0
T3	6215	51	0	0
T7	573571	39	0	0
T8	108700	108	0	0
T9	164494	1190	0	0
T10	6129	67	0	0
T11	563756	945	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	215220	0	0
GntImpliesValid_A	418504577	215220	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	215220	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	6064242	0	0
ReadyAndValidImplyGrant_A	418504577	215220	0	0
ReqAndReadyImplyGrant_A	418504577	215220	0	0
ReqImpliesValid_A	418504577	1359583	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	215220	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	215220	0	0
T1	130467	554	0	0
T2	2454	11	0	0
T3	6215	46	0	0
T7	573571	52	0	0
T8	108700	115	0	0
T9	164494	2161	0	0
T10	6129	77	0	0
T11	563756	935	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	156	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	215220	0	0
T1	130467	554	0	0
T2	2454	11	0	0
T3	6215	46	0	0
T7	573571	52	0	0
T8	108700	115	0	0
T9	164494	2161	0	0
T10	6129	77	0	0
T11	563756	935	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	156	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	215220	0	0
T1	130467	554	0	0
T2	2454	11	0	0
T3	6215	46	0	0
T7	573571	52	0	0
T8	108700	115	0	0
T9	164494	2161	0	0
T10	6129	77	0	0
T11	563756	935	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	156	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	6064242	0	0
T1	130467	125	0	0
T2	2454	85	0	0
T3	6215	182	0	0
T7	573571	362	0	0
T8	108700	1257	0	0
T9	164494	6451	0	0
T10	6129	312	0	0
T11	563756	9923	0	0
T12	209810	111	0	0
T13	188871	0	0	0
T14	0	729	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	215220	0	0
T1	130467	554	0	0
T2	2454	11	0	0
T3	6215	46	0	0
T7	573571	52	0	0
T8	108700	115	0	0
T9	164494	2161	0	0
T10	6129	77	0	0
T11	563756	935	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	156	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	215220	0	0
T1	130467	554	0	0
T2	2454	11	0	0
T3	6215	46	0	0
T7	573571	52	0	0
T8	108700	115	0	0
T9	164494	2161	0	0
T10	6129	77	0	0
T11	563756	935	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	156	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	1359583	0	0
T1	130467	29071	0	0
T2	2454	18	0	0
T3	6215	54	0	0
T7	573571	58	0	0
T8	108700	193	0	0
T9	164494	6723	0	0
T10	6129	125	0	0
T11	563756	1189	0	0
T12	209810	32	0	0
T13	188871	0	0	0
T14	0	202	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	215220	0	0
T1	130467	554	0	0
T2	2454	11	0	0
T3	6215	46	0	0
T7	573571	52	0	0
T8	108700	115	0	0
T9	164494	2161	0	0
T10	6129	77	0	0
T11	563756	935	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	0	156	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	211928	0	0
GntImpliesValid_A	418504577	211928	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	211928	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3326652	0	0
ReadyAndValidImplyGrant_A	418504577	211928	0	0
ReqAndReadyImplyGrant_A	418504577	211928	0	0
ReqImpliesValid_A	418504577	597405	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	211928	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	211928	0	0
T1	130467	486	0	0
T2	2454	16	0	0
T3	6215	158	0	0
T7	573571	32	0	0
T8	108700	97	0	0
T9	164494	1176	0	0
T10	6129	57	0	0
T11	563756	1907	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	0	145	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	211928	0	0
T1	130467	486	0	0
T2	2454	16	0	0
T3	6215	158	0	0
T7	573571	32	0	0
T8	108700	97	0	0
T9	164494	1176	0	0
T10	6129	57	0	0
T11	563756	1907	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	0	145	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	211928	0	0
T1	130467	486	0	0
T2	2454	16	0	0
T3	6215	158	0	0
T7	573571	32	0	0
T8	108700	97	0	0
T9	164494	1176	0	0
T10	6129	57	0	0
T11	563756	1907	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	0	145	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3326652	0	0
T1	130467	1025	0	0
T2	2454	15	0	0
T3	6215	57	0	0
T7	573571	163	0	0
T8	108700	408	0	0
T9	164494	1155	0	0
T10	6129	56	0	0
T11	563756	13517	0	0
T12	209810	41	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	211928	0	0
T1	130467	486	0	0
T2	2454	16	0	0
T3	6215	158	0	0
T7	573571	32	0	0
T8	108700	97	0	0
T9	164494	1176	0	0
T10	6129	57	0	0
T11	563756	1907	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	0	145	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	211928	0	0
T1	130467	486	0	0
T2	2454	16	0	0
T3	6215	158	0	0
T7	573571	32	0	0
T8	108700	97	0	0
T9	164494	1176	0	0
T10	6129	57	0	0
T11	563756	1907	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	0	145	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	597405	0	0
T1	130467	2044	0	0
T2	2454	18	0	0
T3	6215	267	0	0
T7	573571	35	0	0
T8	108700	115	0	0
T9	164494	1199	0	0
T10	6129	59	0	0
T11	563756	4373	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	0	147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	211928	0	0
T1	130467	486	0	0
T2	2454	16	0	0
T3	6215	158	0	0
T7	573571	32	0	0
T8	108700	97	0	0
T9	164494	1176	0	0
T10	6129	57	0	0
T11	563756	1907	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	0	145	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	216031	0	0
GntImpliesValid_A	418504577	216031	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	216031	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3389056	0	0
ReadyAndValidImplyGrant_A	418504577	216031	0	0
ReqAndReadyImplyGrant_A	418504577	216031	0	0
ReqImpliesValid_A	418504577	599421	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	216031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216031	0	0
T2	2454	10	0	0
T3	6215	59	0	0
T7	573571	50	0	0
T8	108700	111	0	0
T9	164494	2158	0	0
T10	6129	71	0	0
T11	563756	1813	0	0
T12	209810	8	0	0
T13	188871	0	0	0
T14	14462	160	0	0
T15	0	257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216031	0	0
T2	2454	10	0	0
T3	6215	59	0	0
T7	573571	50	0	0
T8	108700	111	0	0
T9	164494	2158	0	0
T10	6129	71	0	0
T11	563756	1813	0	0
T12	209810	8	0	0
T13	188871	0	0	0
T14	14462	160	0	0
T15	0	257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216031	0	0
T2	2454	10	0	0
T3	6215	59	0	0
T7	573571	50	0	0
T8	108700	111	0	0
T9	164494	2158	0	0
T10	6129	71	0	0
T11	563756	1813	0	0
T12	209810	8	0	0
T13	188871	0	0	0
T14	14462	160	0	0
T15	0	257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3389056	0	0
T1	130467	1	0	0
T2	2454	10	0	0
T3	6215	67	0	0
T7	573571	197	0	0
T8	108700	502	0	0
T9	164494	1799	0	0
T10	6129	66	0	0
T11	563756	11777	0	0
T12	209810	29	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216031	0	0
T2	2454	10	0	0
T3	6215	59	0	0
T7	573571	50	0	0
T8	108700	111	0	0
T9	164494	2158	0	0
T10	6129	71	0	0
T11	563756	1813	0	0
T12	209810	8	0	0
T13	188871	0	0	0
T14	14462	160	0	0
T15	0	257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216031	0	0
T2	2454	10	0	0
T3	6215	59	0	0
T7	573571	50	0	0
T8	108700	111	0	0
T9	164494	2158	0	0
T10	6129	71	0	0
T11	563756	1813	0	0
T12	209810	8	0	0
T13	188871	0	0	0
T14	14462	160	0	0
T15	0	257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	599421	0	0
T2	2454	11	0	0
T3	6215	59	0	0
T7	573571	59	0	0
T8	108700	130	0	0
T9	164494	2519	0	0
T10	6129	77	0	0
T11	563756	5105	0	0
T12	209810	8	0	0
T13	188871	0	0	0
T14	14462	160	0	0
T15	0	6629	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216031	0	0
T2	2454	10	0	0
T3	6215	59	0	0
T7	573571	50	0	0
T8	108700	111	0	0
T9	164494	2158	0	0
T10	6129	71	0	0
T11	563756	1813	0	0
T12	209810	8	0	0
T13	188871	0	0	0
T14	14462	160	0	0
T15	0	257	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	210352	0	0
GntImpliesValid_A	418504577	210352	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	210352	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3307995	0	0
ReadyAndValidImplyGrant_A	418504577	210352	0	0
ReqAndReadyImplyGrant_A	418504577	210352	0	0
ReqImpliesValid_A	418504577	602454	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	210352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	210352	0	0
T2	2454	13	0	0
T3	6215	65	0	0
T7	573571	43	0	0
T8	108700	81	0	0
T9	164494	2185	0	0
T10	6129	61	0	0
T11	563756	1505	0	0
T12	209810	15	0	0
T13	188871	435	0	0
T14	14462	172	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	210352	0	0
T2	2454	13	0	0
T3	6215	65	0	0
T7	573571	43	0	0
T8	108700	81	0	0
T9	164494	2185	0	0
T10	6129	61	0	0
T11	563756	1505	0	0
T12	209810	15	0	0
T13	188871	435	0	0
T14	14462	172	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	210352	0	0
T2	2454	13	0	0
T3	6215	65	0	0
T7	573571	43	0	0
T8	108700	81	0	0
T9	164494	2185	0	0
T10	6129	61	0	0
T11	563756	1505	0	0
T12	209810	15	0	0
T13	188871	435	0	0
T14	14462	172	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3307995	0	0
T1	130467	1	0	0
T2	2454	13	0	0
T3	6215	72	0	0
T7	573571	193	0	0
T8	108700	337	0	0
T9	164494	1874	0	0
T10	6129	60	0	0
T11	563756	10294	0	0
T12	209810	67	0	0
T13	188871	1336	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	210352	0	0
T2	2454	13	0	0
T3	6215	65	0	0
T7	573571	43	0	0
T8	108700	81	0	0
T9	164494	2185	0	0
T10	6129	61	0	0
T11	563756	1505	0	0
T12	209810	15	0	0
T13	188871	435	0	0
T14	14462	172	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	210352	0	0
T2	2454	13	0	0
T3	6215	65	0	0
T7	573571	43	0	0
T8	108700	81	0	0
T9	164494	2185	0	0
T10	6129	61	0	0
T11	563756	1505	0	0
T12	209810	15	0	0
T13	188871	435	0	0
T14	14462	172	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	602454	0	0
T2	2454	14	0	0
T3	6215	66	0	0
T7	573571	50	0	0
T8	108700	96	0	0
T9	164494	2498	0	0
T10	6129	63	0	0
T11	563756	2125	0	0
T12	209810	25	0	0
T13	188871	1104	0	0
T14	14462	178	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	210352	0	0
T2	2454	13	0	0
T3	6215	65	0	0
T7	573571	43	0	0
T8	108700	81	0	0
T9	164494	2185	0	0
T10	6129	61	0	0
T11	563756	1505	0	0
T12	209810	15	0	0
T13	188871	435	0	0
T14	14462	172	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	213788	0	0
GntImpliesValid_A	418504577	213788	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	213788	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3338820	0	0
ReadyAndValidImplyGrant_A	418504577	213788	0	0
ReqAndReadyImplyGrant_A	418504577	213788	0	0
ReqImpliesValid_A	418504577	615521	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	213788	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213788	0	0
T2	2454	17	0	0
T3	6215	68	0	0
T7	573571	53	0	0
T8	108700	90	0	0
T9	164494	1208	0	0
T10	6129	68	0	0
T11	563756	914	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	172	0	0
T15	0	259	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213788	0	0
T2	2454	17	0	0
T3	6215	68	0	0
T7	573571	53	0	0
T8	108700	90	0	0
T9	164494	1208	0	0
T10	6129	68	0	0
T11	563756	914	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	172	0	0
T15	0	259	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213788	0	0
T2	2454	17	0	0
T3	6215	68	0	0
T7	573571	53	0	0
T8	108700	90	0	0
T9	164494	1208	0	0
T10	6129	68	0	0
T11	563756	914	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	172	0	0
T15	0	259	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3338820	0	0
T1	130467	1	0	0
T2	2454	17	0	0
T3	6215	75	0	0
T7	573571	216	0	0
T8	108700	400	0	0
T9	164494	1190	0	0
T10	6129	65	0	0
T11	563756	6904	0	0
T12	209810	39	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213788	0	0
T2	2454	17	0	0
T3	6215	68	0	0
T7	573571	53	0	0
T8	108700	90	0	0
T9	164494	1208	0	0
T10	6129	68	0	0
T11	563756	914	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	172	0	0
T15	0	259	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213788	0	0
T2	2454	17	0	0
T3	6215	68	0	0
T7	573571	53	0	0
T8	108700	90	0	0
T9	164494	1208	0	0
T10	6129	68	0	0
T11	563756	914	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	172	0	0
T15	0	259	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	615521	0	0
T2	2454	18	0	0
T3	6215	69	0	0
T7	573571	78	0	0
T8	108700	109	0	0
T9	164494	1228	0	0
T10	6129	72	0	0
T11	563756	1026	0	0
T12	209810	19	0	0
T13	188871	0	0	0
T14	14462	174	0	0
T15	0	7606	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	213788	0	0
T2	2454	17	0	0
T3	6215	68	0	0
T7	573571	53	0	0
T8	108700	90	0	0
T9	164494	1208	0	0
T10	6129	68	0	0
T11	563756	914	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	172	0	0
T15	0	259	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	218301	0	0
GntImpliesValid_A	418504577	218301	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	218301	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3295507	0	0
ReadyAndValidImplyGrant_A	418504577	218301	0	0
ReqAndReadyImplyGrant_A	418504577	218301	0	0
ReqImpliesValid_A	418504577	625787	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	218301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218301	0	0
T2	2454	18	0	0
T3	6215	547	0	0
T7	573571	44	0	0
T8	108700	84	0	0
T9	164494	2740	0	0
T10	6129	61	0	0
T11	563756	1922	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	14462	143	0	0
T15	0	278	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218301	0	0
T2	2454	18	0	0
T3	6215	547	0	0
T7	573571	44	0	0
T8	108700	84	0	0
T9	164494	2740	0	0
T10	6129	61	0	0
T11	563756	1922	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	14462	143	0	0
T15	0	278	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218301	0	0
T2	2454	18	0	0
T3	6215	547	0	0
T7	573571	44	0	0
T8	108700	84	0	0
T9	164494	2740	0	0
T10	6129	61	0	0
T11	563756	1922	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	14462	143	0	0
T15	0	278	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3295507	0	0
T1	130467	1	0	0
T2	2454	16	0	0
T3	6215	342	0	0
T7	573571	174	0	0
T8	108700	361	0	0
T9	164494	1812	0	0
T10	6129	61	0	0
T11	563756	12106	0	0
T12	209810	72	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218301	0	0
T2	2454	18	0	0
T3	6215	547	0	0
T7	573571	44	0	0
T8	108700	84	0	0
T9	164494	2740	0	0
T10	6129	61	0	0
T11	563756	1922	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	14462	143	0	0
T15	0	278	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218301	0	0
T2	2454	18	0	0
T3	6215	547	0	0
T7	573571	44	0	0
T8	108700	84	0	0
T9	164494	2740	0	0
T10	6129	61	0	0
T11	563756	1922	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	14462	143	0	0
T15	0	278	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	625787	0	0
T2	2454	21	0	0
T3	6215	760	0	0
T7	573571	57	0	0
T8	108700	102	0	0
T9	164494	3670	0	0
T10	6129	62	0	0
T11	563756	6134	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	14462	145	0	0
T15	0	6198	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218301	0	0
T2	2454	18	0	0
T3	6215	547	0	0
T7	573571	44	0	0
T8	108700	84	0	0
T9	164494	2740	0	0
T10	6129	61	0	0
T11	563756	1922	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	14462	143	0	0
T15	0	278	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	221230	0	0
GntImpliesValid_A	418504577	221230	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	221230	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3359646	0	0
ReadyAndValidImplyGrant_A	418504577	221230	0	0
ReqAndReadyImplyGrant_A	418504577	221230	0	0
ReqImpliesValid_A	418504577	668011	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	221230	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221230	0	0
T2	2454	11	0	0
T3	6215	53	0	0
T7	573571	51	0	0
T8	108700	100	0	0
T9	164494	1183	0	0
T10	6129	80	0	0
T11	563756	2799	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	683	0	0
T15	0	206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221230	0	0
T2	2454	11	0	0
T3	6215	53	0	0
T7	573571	51	0	0
T8	108700	100	0	0
T9	164494	1183	0	0
T10	6129	80	0	0
T11	563756	2799	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	683	0	0
T15	0	206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221230	0	0
T2	2454	11	0	0
T3	6215	53	0	0
T7	573571	51	0	0
T8	108700	100	0	0
T9	164494	1183	0	0
T10	6129	80	0	0
T11	563756	2799	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	683	0	0
T15	0	206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3359646	0	0
T1	130467	1	0	0
T2	2454	12	0	0
T3	6215	60	0	0
T7	573571	182	0	0
T8	108700	414	0	0
T9	164494	1166	0	0
T10	6129	76	0	0
T11	563756	14058	0	0
T12	209810	45	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221230	0	0
T2	2454	11	0	0
T3	6215	53	0	0
T7	573571	51	0	0
T8	108700	100	0	0
T9	164494	1183	0	0
T10	6129	80	0	0
T11	563756	2799	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	683	0	0
T15	0	206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221230	0	0
T2	2454	11	0	0
T3	6215	53	0	0
T7	573571	51	0	0
T8	108700	100	0	0
T9	164494	1183	0	0
T10	6129	80	0	0
T11	563756	2799	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	683	0	0
T15	0	206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	668011	0	0
T2	2454	11	0	0
T3	6215	54	0	0
T7	573571	52	0	0
T8	108700	108	0	0
T9	164494	1202	0	0
T10	6129	85	0	0
T11	563756	14080	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	1135	0	0
T15	0	2290	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221230	0	0
T2	2454	11	0	0
T3	6215	53	0	0
T7	573571	51	0	0
T8	108700	100	0	0
T9	164494	1183	0	0
T10	6129	80	0	0
T11	563756	2799	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	683	0	0
T15	0	206	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	216675	0	0
GntImpliesValid_A	418504577	216675	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	216675	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3336211	0	0
ReadyAndValidImplyGrant_A	418504577	216675	0	0
ReqAndReadyImplyGrant_A	418504577	216675	0	0
ReqImpliesValid_A	418504577	623291	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	216675	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216675	0	0
T2	2454	11	0	0
T3	6215	48	0	0
T7	573571	41	0	0
T8	108700	92	0	0
T9	164494	3379	0	0
T10	6129	64	0	0
T11	563756	1881	0	0
T12	209810	7	0	0
T13	188871	0	0	0
T14	14462	174	0	0
T15	0	267	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216675	0	0
T2	2454	11	0	0
T3	6215	48	0	0
T7	573571	41	0	0
T8	108700	92	0	0
T9	164494	3379	0	0
T10	6129	64	0	0
T11	563756	1881	0	0
T12	209810	7	0	0
T13	188871	0	0	0
T14	14462	174	0	0
T15	0	267	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216675	0	0
T2	2454	11	0	0
T3	6215	48	0	0
T7	573571	41	0	0
T8	108700	92	0	0
T9	164494	3379	0	0
T10	6129	64	0	0
T11	563756	1881	0	0
T12	209810	7	0	0
T13	188871	0	0	0
T14	14462	174	0	0
T15	0	267	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3336211	0	0
T1	130467	1	0	0
T2	2454	11	0	0
T3	6215	56	0	0
T7	573571	175	0	0
T8	108700	393	0	0
T9	164494	2483	0	0
T10	6129	64	0	0
T11	563756	12217	0	0
T12	209810	33	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216675	0	0
T2	2454	11	0	0
T3	6215	48	0	0
T7	573571	41	0	0
T8	108700	92	0	0
T9	164494	3379	0	0
T10	6129	64	0	0
T11	563756	1881	0	0
T12	209810	7	0	0
T13	188871	0	0	0
T14	14462	174	0	0
T15	0	267	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216675	0	0
T2	2454	11	0	0
T3	6215	48	0	0
T7	573571	41	0	0
T8	108700	92	0	0
T9	164494	3379	0	0
T10	6129	64	0	0
T11	563756	1881	0	0
T12	209810	7	0	0
T13	188871	0	0	0
T14	14462	174	0	0
T15	0	267	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	623291	0	0
T2	2454	12	0	0
T3	6215	48	0	0
T7	573571	51	0	0
T8	108700	121	0	0
T9	164494	4277	0	0
T10	6129	65	0	0
T11	563756	5349	0	0
T12	209810	7	0	0
T13	188871	0	0	0
T14	14462	176	0	0
T15	0	6569	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	216675	0	0
T2	2454	11	0	0
T3	6215	48	0	0
T7	573571	41	0	0
T8	108700	92	0	0
T9	164494	3379	0	0
T10	6129	64	0	0
T11	563756	1881	0	0
T12	209810	7	0	0
T13	188871	0	0	0
T14	14462	174	0	0
T15	0	267	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	221170	0	0
GntImpliesValid_A	418504577	221170	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	221170	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3312279	0	0
ReadyAndValidImplyGrant_A	418504577	221170	0	0
ReqAndReadyImplyGrant_A	418504577	221170	0	0
ReqImpliesValid_A	418504577	649320	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	221170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221170	0	0
T1	130467	1036	0	0
T2	2454	22	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	101	0	0
T9	164494	2659	0	0
T10	6129	67	0	0
T11	563756	930	0	0
T12	209810	4	0	0
T13	188871	0	0	0
T14	0	1040	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221170	0	0
T1	130467	1036	0	0
T2	2454	22	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	101	0	0
T9	164494	2659	0	0
T10	6129	67	0	0
T11	563756	930	0	0
T12	209810	4	0	0
T13	188871	0	0	0
T14	0	1040	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221170	0	0
T1	130467	1036	0	0
T2	2454	22	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	101	0	0
T9	164494	2659	0	0
T10	6129	67	0	0
T11	563756	930	0	0
T12	209810	4	0	0
T13	188871	0	0	0
T14	0	1040	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3312279	0	0
T1	130467	1734	0	0
T2	2454	23	0	0
T3	6215	55	0	0
T7	573571	221	0	0
T8	108700	413	0	0
T9	164494	1997	0	0
T10	6129	65	0	0
T11	563756	7110	0	0
T12	209810	21	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221170	0	0
T1	130467	1036	0	0
T2	2454	22	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	101	0	0
T9	164494	2659	0	0
T10	6129	67	0	0
T11	563756	930	0	0
T12	209810	4	0	0
T13	188871	0	0	0
T14	0	1040	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221170	0	0
T1	130467	1036	0	0
T2	2454	22	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	101	0	0
T9	164494	2659	0	0
T10	6129	67	0	0
T11	563756	930	0	0
T12	209810	4	0	0
T13	188871	0	0	0
T14	0	1040	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	649320	0	0
T1	130467	9824	0	0
T2	2454	22	0	0
T3	6215	51	0	0
T7	573571	68	0	0
T8	108700	136	0	0
T9	164494	3323	0	0
T10	6129	70	0	0
T11	563756	1042	0	0
T12	209810	4	0	0
T13	188871	0	0	0
T14	0	1494	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	221170	0	0
T1	130467	1036	0	0
T2	2454	22	0	0
T3	6215	49	0	0
T7	573571	54	0	0
T8	108700	101	0	0
T9	164494	2659	0	0
T10	6129	67	0	0
T11	563756	930	0	0
T12	209810	4	0	0
T13	188871	0	0	0
T14	0	1040	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	238217	0	0
GntImpliesValid_A	418504577	238217	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	238217	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3401499	0	0
ReadyAndValidImplyGrant_A	418504577	238217	0	0
ReqAndReadyImplyGrant_A	418504577	238217	0	0
ReqImpliesValid_A	418504577	612343	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	238217	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	238217	0	0
T1	130467	473	0	0
T2	2454	13	0	0
T3	6215	73	0	0
T7	573571	36	0	0
T8	108700	118	0	0
T9	164494	3259	0	0
T10	6129	101	0	0
T11	563756	1608	0	0
T12	209810	13	0	0
T13	188871	1511	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	238217	0	0
T1	130467	473	0	0
T2	2454	13	0	0
T3	6215	73	0	0
T7	573571	36	0	0
T8	108700	118	0	0
T9	164494	3259	0	0
T10	6129	101	0	0
T11	563756	1608	0	0
T12	209810	13	0	0
T13	188871	1511	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	238217	0	0
T1	130467	473	0	0
T2	2454	13	0	0
T3	6215	73	0	0
T7	573571	36	0	0
T8	108700	118	0	0
T9	164494	3259	0	0
T10	6129	101	0	0
T11	563756	1608	0	0
T12	209810	13	0	0
T13	188871	1511	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3401499	0	0
T1	130467	929	0	0
T2	2454	14	0	0
T3	6215	80	0	0
T7	573571	166	0	0
T8	108700	539	0	0
T9	164494	2306	0	0
T10	6129	98	0	0
T11	563756	10948	0	0
T12	209810	49	0	0
T13	188871	4843	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	238217	0	0
T1	130467	473	0	0
T2	2454	13	0	0
T3	6215	73	0	0
T7	573571	36	0	0
T8	108700	118	0	0
T9	164494	3259	0	0
T10	6129	101	0	0
T11	563756	1608	0	0
T12	209810	13	0	0
T13	188871	1511	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	238217	0	0
T1	130467	473	0	0
T2	2454	13	0	0
T3	6215	73	0	0
T7	573571	36	0	0
T8	108700	118	0	0
T9	164494	3259	0	0
T10	6129	101	0	0
T11	563756	1608	0	0
T12	209810	13	0	0
T13	188871	1511	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	612343	0	0
T1	130467	1877	0	0
T2	2454	13	0	0
T3	6215	74	0	0
T7	573571	36	0	0
T8	108700	153	0	0
T9	164494	4214	0	0
T10	6129	105	0	0
T11	563756	4110	0	0
T12	209810	13	0	0
T13	188871	3608	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	238217	0	0
T1	130467	473	0	0
T2	2454	13	0	0
T3	6215	73	0	0
T7	573571	36	0	0
T8	108700	118	0	0
T9	164494	3259	0	0
T10	6129	101	0	0
T11	563756	1608	0	0
T12	209810	13	0	0
T13	188871	1511	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	222587	0	0
GntImpliesValid_A	418504577	222587	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	222587	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3355997	0	0
ReadyAndValidImplyGrant_A	418504577	222587	0	0
ReqAndReadyImplyGrant_A	418504577	222587	0	0
ReqImpliesValid_A	418504577	601363	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	222587	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222587	0	0
T2	2454	16	0	0
T3	6215	49	0	0
T7	573571	36	0	0
T8	108700	98	0	0
T9	164494	1748	0	0
T10	6129	72	0	0
T11	563756	939	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	14462	151	0	0
T15	0	266	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222587	0	0
T2	2454	16	0	0
T3	6215	49	0	0
T7	573571	36	0	0
T8	108700	98	0	0
T9	164494	1748	0	0
T10	6129	72	0	0
T11	563756	939	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	14462	151	0	0
T15	0	266	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222587	0	0
T2	2454	16	0	0
T3	6215	49	0	0
T7	573571	36	0	0
T8	108700	98	0	0
T9	164494	1748	0	0
T10	6129	72	0	0
T11	563756	939	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	14462	151	0	0
T15	0	266	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3355997	0	0
T1	130467	1	0	0
T2	2454	16	0	0
T3	6215	55	0	0
T7	573571	176	0	0
T8	108700	440	0	0
T9	164494	1679	0	0
T10	6129	68	0	0
T11	563756	7473	0	0
T12	209810	28	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222587	0	0
T2	2454	16	0	0
T3	6215	49	0	0
T7	573571	36	0	0
T8	108700	98	0	0
T9	164494	1748	0	0
T10	6129	72	0	0
T11	563756	939	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	14462	151	0	0
T15	0	266	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222587	0	0
T2	2454	16	0	0
T3	6215	49	0	0
T7	573571	36	0	0
T8	108700	98	0	0
T9	164494	1748	0	0
T10	6129	72	0	0
T11	563756	939	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	14462	151	0	0
T15	0	266	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	601363	0	0
T2	2454	17	0	0
T3	6215	51	0	0
T7	573571	39	0	0
T8	108700	102	0	0
T9	164494	1819	0	0
T10	6129	77	0	0
T11	563756	1059	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	14462	153	0	0
T15	0	4203	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	222587	0	0
T2	2454	16	0	0
T3	6215	49	0	0
T7	573571	36	0	0
T8	108700	98	0	0
T9	164494	1748	0	0
T10	6129	72	0	0
T11	563756	939	0	0
T12	209810	6	0	0
T13	188871	0	0	0
T14	14462	151	0	0
T15	0	266	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	208770	0	0
GntImpliesValid_A	418504577	208770	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	208770	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3301728	0	0
ReadyAndValidImplyGrant_A	418504577	208770	0	0
ReqAndReadyImplyGrant_A	418504577	208770	0	0
ReqImpliesValid_A	418504577	563597	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	208770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	208770	0	0
T2	2454	11	0	0
T3	6215	147	0	0
T7	573571	47	0	0
T8	108700	108	0	0
T9	164494	1553	0	0
T10	6129	61	0	0
T11	563756	1477	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	148	0	0
T15	0	237	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	208770	0	0
T2	2454	11	0	0
T3	6215	147	0	0
T7	573571	47	0	0
T8	108700	108	0	0
T9	164494	1553	0	0
T10	6129	61	0	0
T11	563756	1477	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	148	0	0
T15	0	237	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	208770	0	0
T2	2454	11	0	0
T3	6215	147	0	0
T7	573571	47	0	0
T8	108700	108	0	0
T9	164494	1553	0	0
T10	6129	61	0	0
T11	563756	1477	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	148	0	0
T15	0	237	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3301728	0	0
T1	130467	1	0	0
T2	2454	11	0	0
T3	6215	64	0	0
T7	573571	177	0	0
T8	108700	443	0	0
T9	164494	1048	0	0
T10	6129	60	0	0
T11	563756	10331	0	0
T12	209810	40	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	208770	0	0
T2	2454	11	0	0
T3	6215	147	0	0
T7	573571	47	0	0
T8	108700	108	0	0
T9	164494	1553	0	0
T10	6129	61	0	0
T11	563756	1477	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	148	0	0
T15	0	237	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	208770	0	0
T2	2454	11	0	0
T3	6215	147	0	0
T7	573571	47	0	0
T8	108700	108	0	0
T9	164494	1553	0	0
T10	6129	61	0	0
T11	563756	1477	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	148	0	0
T15	0	237	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	563597	0	0
T2	2454	12	0	0
T3	6215	238	0	0
T7	573571	54	0	0
T8	108700	143	0	0
T9	164494	2060	0	0
T10	6129	63	0	0
T11	563756	2163	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	14462	148	0	0
T15	0	2961	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	208770	0	0
T2	2454	11	0	0
T3	6215	147	0	0
T7	573571	47	0	0
T8	108700	108	0	0
T9	164494	1553	0	0
T10	6129	61	0	0
T11	563756	1477	0	0
T12	209810	11	0	0
T13	188871	0	0	0
T14	14462	148	0	0
T15	0	237	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	226518	0	0
GntImpliesValid_A	418504577	226518	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	226518	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3296298	0	0
ReadyAndValidImplyGrant_A	418504577	226518	0	0
ReqAndReadyImplyGrant_A	418504577	226518	0	0
ReqImpliesValid_A	418504577	680563	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	226518	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226518	0	0
T1	130467	419	0	0
T2	2454	17	0	0
T3	6215	159	0	0
T7	573571	38	0	0
T8	108700	98	0	0
T9	164494	2702	0	0
T10	6129	62	0	0
T11	563756	1432	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	0	152	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226518	0	0
T1	130467	419	0	0
T2	2454	17	0	0
T3	6215	159	0	0
T7	573571	38	0	0
T8	108700	98	0	0
T9	164494	2702	0	0
T10	6129	62	0	0
T11	563756	1432	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	0	152	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226518	0	0
T1	130467	419	0	0
T2	2454	17	0	0
T3	6215	159	0	0
T7	573571	38	0	0
T8	108700	98	0	0
T9	164494	2702	0	0
T10	6129	62	0	0
T11	563756	1432	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	0	152	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3296298	0	0
T1	130467	596	0	0
T2	2454	17	0	0
T3	6215	151	0	0
T7	573571	159	0	0
T8	108700	408	0	0
T9	164494	2301	0	0
T10	6129	60	0	0
T11	563756	10952	0	0
T12	209810	52	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226518	0	0
T1	130467	419	0	0
T2	2454	17	0	0
T3	6215	159	0	0
T7	573571	38	0	0
T8	108700	98	0	0
T9	164494	2702	0	0
T10	6129	62	0	0
T11	563756	1432	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	0	152	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226518	0	0
T1	130467	419	0	0
T2	2454	17	0	0
T3	6215	159	0	0
T7	573571	38	0	0
T8	108700	98	0	0
T9	164494	2702	0	0
T10	6129	62	0	0
T11	563756	1432	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	0	152	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	680563	0	0
T1	130467	4287	0	0
T2	2454	18	0	0
T3	6215	175	0	0
T7	573571	43	0	0
T8	108700	113	0	0
T9	164494	3105	0	0
T10	6129	65	0	0
T11	563756	2223	0	0
T12	209810	16	0	0
T13	188871	0	0	0
T14	0	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	226518	0	0
T1	130467	419	0	0
T2	2454	17	0	0
T3	6215	159	0	0
T7	573571	38	0	0
T8	108700	98	0	0
T9	164494	2702	0	0
T10	6129	62	0	0
T11	563756	1432	0	0
T12	209810	13	0	0
T13	188871	0	0	0
T14	0	152	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	218844	0	0
GntImpliesValid_A	418504577	218844	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	218844	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3330300	0	0
ReadyAndValidImplyGrant_A	418504577	218844	0	0
ReqAndReadyImplyGrant_A	418504577	218844	0	0
ReqImpliesValid_A	418504577	609406	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	218844	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218844	0	0
T2	2454	9	0	0
T3	6215	44	0	0
T7	573571	39	0	0
T8	108700	106	0	0
T9	164494	2282	0	0
T10	6129	58	0	0
T11	563756	1402	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	182	0	0
T15	0	234	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218844	0	0
T2	2454	9	0	0
T3	6215	44	0	0
T7	573571	39	0	0
T8	108700	106	0	0
T9	164494	2282	0	0
T10	6129	58	0	0
T11	563756	1402	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	182	0	0
T15	0	234	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218844	0	0
T2	2454	9	0	0
T3	6215	44	0	0
T7	573571	39	0	0
T8	108700	106	0	0
T9	164494	2282	0	0
T10	6129	58	0	0
T11	563756	1402	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	182	0	0
T15	0	234	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3330300	0	0
T1	130467	1	0	0
T2	2454	10	0	0
T3	6215	52	0	0
T7	573571	153	0	0
T8	108700	476	0	0
T9	164494	1507	0	0
T10	6129	56	0	0
T11	563756	10630	0	0
T12	209810	24	0	0
T13	188871	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218844	0	0
T2	2454	9	0	0
T3	6215	44	0	0
T7	573571	39	0	0
T8	108700	106	0	0
T9	164494	2282	0	0
T10	6129	58	0	0
T11	563756	1402	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	182	0	0
T15	0	234	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218844	0	0
T2	2454	9	0	0
T3	6215	44	0	0
T7	573571	39	0	0
T8	108700	106	0	0
T9	164494	2282	0	0
T10	6129	58	0	0
T11	563756	1402	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	182	0	0
T15	0	234	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	609406	0	0
T2	2454	9	0	0
T3	6215	44	0	0
T7	573571	45	0	0
T8	108700	130	0	0
T9	164494	3059	0	0
T10	6129	61	0	0
T11	563756	2435	0	0
T12	209810	12	0	0
T13	188871	0	0	0
T14	14462	185	0	0
T15	0	5078	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	218844	0	0
T2	2454	9	0	0
T3	6215	44	0	0
T7	573571	39	0	0
T8	108700	106	0	0
T9	164494	2282	0	0
T10	6129	58	0	0
T11	563756	1402	0	0
T12	209810	10	0	0
T13	188871	0	0	0
T14	14462	182	0	0
T15	0	234	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	220673	0	0
GntImpliesValid_A	418504577	220673	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	220673	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	3336063	0	0
ReadyAndValidImplyGrant_A	418504577	220673	0	0
ReqAndReadyImplyGrant_A	418504577	220673	0	0
ReqImpliesValid_A	418504577	591845	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	0	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	220673	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220673	0	0
T1	130467	1053	0	0
T2	2454	12	0	0
T3	6215	178	0	0
T7	573571	54	0	0
T8	108700	106	0	0
T9	164494	1669	0	0
T10	6129	49	0	0
T11	563756	2404	0	0
T12	209810	11	0	0
T13	188871	470	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220673	0	0
T1	130467	1053	0	0
T2	2454	12	0	0
T3	6215	178	0	0
T7	573571	54	0	0
T8	108700	106	0	0
T9	164494	1669	0	0
T10	6129	49	0	0
T11	563756	2404	0	0
T12	209810	11	0	0
T13	188871	470	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220673	0	0
T1	130467	1053	0	0
T2	2454	12	0	0
T3	6215	178	0	0
T7	573571	54	0	0
T8	108700	106	0	0
T9	164494	1669	0	0
T10	6129	49	0	0
T11	563756	2404	0	0
T12	209810	11	0	0
T13	188871	470	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	3336063	0	0
T1	130467	2208	0	0
T2	2454	12	0	0
T3	6215	158	0	0
T7	573571	248	0	0
T8	108700	443	0	0
T9	164494	1109	0	0
T10	6129	49	0	0
T11	563756	13961	0	0
T12	209810	47	0	0
T13	188871	1439	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220673	0	0
T1	130467	1053	0	0
T2	2454	12	0	0
T3	6215	178	0	0
T7	573571	54	0	0
T8	108700	106	0	0
T9	164494	1669	0	0
T10	6129	49	0	0
T11	563756	2404	0	0
T12	209810	11	0	0
T13	188871	470	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220673	0	0
T1	130467	1053	0	0
T2	2454	12	0	0
T3	6215	178	0	0
T7	573571	54	0	0
T8	108700	106	0	0
T9	164494	1669	0	0
T10	6129	49	0	0
T11	563756	2404	0	0
T12	209810	11	0	0
T13	188871	470	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	591845	0	0
T1	130467	4360	0	0
T2	2454	13	0	0
T3	6215	206	0	0
T7	573571	68	0	0
T8	108700	140	0	0
T9	164494	2231	0	0
T10	6129	50	0	0
T11	563756	9631	0	0
T12	209810	11	0	0
T13	188871	1191	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	220673	0	0
T1	130467	1053	0	0
T2	2454	12	0	0
T3	6215	178	0	0
T7	573571	54	0	0
T8	108700	106	0	0
T9	164494	1669	0	0
T10	6129	49	0	0
T11	563756	2404	0	0
T12	209810	11	0	0
T13	188871	470	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	900894	0	0
GntImpliesValid_A	418504577	900894	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	900894	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	12675979	0	0
ReadyAndValidImplyGrant_A	418504577	900894	0	0
ReqAndReadyImplyGrant_A	418504577	900894	0	0
ReqImpliesValid_A	418504577	2579035	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	19429	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	900894	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	900894	0	0
T1	130467	1488	0	0
T2	2454	51	0	0
T3	6215	419	0	0
T7	573571	205	0	0
T8	108700	443	0	0
T9	164494	7432	0	0
T10	6129	274	0	0
T11	563756	5749	0	0
T12	209810	43	0	0
T13	188871	407	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	900894	0	0
T1	130467	1488	0	0
T2	2454	51	0	0
T3	6215	419	0	0
T7	573571	205	0	0
T8	108700	443	0	0
T9	164494	7432	0	0
T10	6129	274	0	0
T11	563756	5749	0	0
T12	209810	43	0	0
T13	188871	407	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	900894	0	0
T1	130467	1488	0	0
T2	2454	51	0	0
T3	6215	419	0	0
T7	573571	205	0	0
T8	108700	443	0	0
T9	164494	7432	0	0
T10	6129	274	0	0
T11	563756	5749	0	0
T12	209810	43	0	0
T13	188871	407	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	12675979	0	0
T1	130467	4819	0	0
T2	2454	1	0	0
T3	6215	8	0	0
T7	573571	638	0	0
T8	108700	1480	0	0
T9	164494	2	0	0
T10	6129	1	0	0
T11	563756	34947	0	0
T12	209810	145	0	0
T13	188871	1288	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	900894	0	0
T1	130467	1488	0	0
T2	2454	51	0	0
T3	6215	419	0	0
T7	573571	205	0	0
T8	108700	443	0	0
T9	164494	7432	0	0
T10	6129	274	0	0
T11	563756	5749	0	0
T12	209810	43	0	0
T13	188871	407	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	900894	0	0
T1	130467	1488	0	0
T2	2454	51	0	0
T3	6215	419	0	0
T7	573571	205	0	0
T8	108700	443	0	0
T9	164494	7432	0	0
T10	6129	274	0	0
T11	563756	5749	0	0
T12	209810	43	0	0
T13	188871	407	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	2579035	0	0
T1	130467	9563	0	0
T2	2454	51	0	0
T3	6215	419	0	0
T7	573571	277	0	0
T8	108700	573	0	0
T9	164494	7432	0	0
T10	6129	274	0	0
T11	563756	12174	0	0
T12	209810	46	0	0
T13	188871	528	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	19429	0	900
T1	130467	22	0	1
T2	2454	0	0	1
T3	6215	4	0	1
T7	573571	0	0	1
T8	108700	0	0	1
T9	164494	125	0	1
T10	6129	7	0	1
T11	563756	7	0	1
T12	209810	0	0	1
T13	188871	0	0	1
T14	0	18	0	0
T16	0	10	0	0
T17	0	4	0	0
T18	0	27	0	0
T20	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	900894	0	0
T1	130467	1488	0	0
T2	2454	51	0	0
T3	6215	419	0	0
T7	573571	205	0	0
T8	108700	443	0	0
T9	164494	7432	0	0
T10	6129	274	0	0
T11	563756	5749	0	0
T12	209810	43	0	0
T13	188871	407	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	418504577	418377092	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	418504577	869526	0	0
GntImpliesValid_A	418504577	869526	0	0
GrantKnown_A	418504577	418377092	0	0
IdxKnown_A	418504577	418377092	0	0
IndexIsCorrect_A	418504577	869526	0	0
LockArbDecision_A	418504577	0	0	0
NoReadyValidNoGrant_A	418504577	352605798	0	0
ReadyAndValidImplyGrant_A	418504577	869526	0	0
ReqAndReadyImplyGrant_A	418504577	869526	0	0
ReqImpliesValid_A	418504577	14541596	0	0
ReqStaysHighUntilGranted0_M	418504577	0	0	0
RoundRobin_A	418504577	23342	0	900
ValidKnown_A	418504577	418377092	0	0
gen_data_port_assertion.DataFlow_A	418504577	869526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	869526	0	0
T1	130467	728	0	0
T2	2454	39	0	0
T3	6215	393	0	0
T7	573571	236	0	0
T8	108700	425	0	0
T9	164494	10007	0	0
T10	6129	268	0	0
T11	563756	6344	0	0
T12	209810	33	0	0
T13	188871	391	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	869526	0	0
T1	130467	728	0	0
T2	2454	39	0	0
T3	6215	393	0	0
T7	573571	236	0	0
T8	108700	425	0	0
T9	164494	10007	0	0
T10	6129	268	0	0
T11	563756	6344	0	0
T12	209810	33	0	0
T13	188871	391	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	869526	0	0
T1	130467	728	0	0
T2	2454	39	0	0
T3	6215	393	0	0
T7	573571	236	0	0
T8	108700	425	0	0
T9	164494	10007	0	0
T10	6129	268	0	0
T11	563756	6344	0	0
T12	209810	33	0	0
T13	188871	391	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	352605798	0	0
T1	130467	113598	0	0
T2	2454	1	0	0
T3	6215	1	0	0
T7	573571	477003	0	0
T8	108700	903801	0	0
T9	164494	1	0	0
T10	6129	1	0	0
T11	563756	466715	0	0
T12	209810	174810	0	0
T13	188871	157239	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	869526	0	0
T1	130467	728	0	0
T2	2454	39	0	0
T3	6215	393	0	0
T7	573571	236	0	0
T8	108700	425	0	0
T9	164494	10007	0	0
T10	6129	268	0	0
T11	563756	6344	0	0
T12	209810	33	0	0
T13	188871	391	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	869526	0	0
T1	130467	728	0	0
T2	2454	39	0	0
T3	6215	393	0	0
T7	573571	236	0	0
T8	108700	425	0	0
T9	164494	10007	0	0
T10	6129	268	0	0
T11	563756	6344	0	0
T12	209810	33	0	0
T13	188871	391	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	14541596	0	0
T1	130467	5640	0	0
T2	2454	39	0	0
T3	6215	393	0	0
T7	573571	1049	0	0
T8	108700	1898	0	0
T9	164494	10007	0	0
T10	6129	268	0	0
T11	563756	51855	0	0
T12	209810	126	0	0
T13	188871	1688	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	23342	0	900
T3	6215	3	0	1
T7	573571	0	0	1
T8	108700	0	0	1
T9	164494	1443	0	1
T10	6129	5	0	1
T11	563756	19	0	1
T12	209810	0	0	1
T13	188871	0	0	1
T14	14462	9	0	1
T15	348011	1	0	1
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	418377092	0	0
T1	130467	130391	0	0
T2	2454	2414	0	0
T3	6215	5916	0	0
T7	573571	573546	0	0
T8	108700	108695	0	0
T9	164494	164399	0	0
T10	6129	6094	0	0
T11	563756	563527	0	0
T12	209810	209751	0	0
T13	188871	188870	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418504577	869526	0	0
T1	130467	728	0	0
T2	2454	39	0	0
T3	6215	393	0	0
T7	573571	236	0	0
T8	108700	425	0	0
T9	164494	10007	0	0
T10	6129	268	0	0
T11	563756	6344	0	0
T12	209810	33	0	0
T13	188871	391	0	0