Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1580456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251974

1

T1

48

T2

18

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	621979	1			T1	184		T2	51		T3	25
values[0x0]	589862	1			T1	30		T2	50		T3	6
values[0x1]	620589	1			T1	214		T2	53		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1222423	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

610007

1

T1

158

T2

47

T3

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28155	1			T1	6		T3	1		T7	29
valid_sources[0x01]	28056	1			T1	6		T3	2		T7	45
valid_sources[0x02]	27989	1			T1	6		T3	1		T7	21
valid_sources[0x03]	28059	1			T1	4		T3	1		T7	35
valid_sources[0x04]	28458	1			T1	6		T3	1		T7	42
valid_sources[0x05]	28925	1			T1	7		T3	1		T7	15
valid_sources[0x06]	28961	1			T1	6		T3	1		T7	21
valid_sources[0x07]	28609	1			T1	4		T2	11		T3	1
valid_sources[0x08]	29121	1			T1	2		T3	1		T7	20
valid_sources[0x09]	27784	1			T1	5		T3	2		T7	30
valid_sources[0x0a]	28310	1			T1	7		T3	1		T7	17
valid_sources[0x0b]	27815	1			T1	13		T7	27		T8	1
valid_sources[0x0c]	28154	1			T1	7		T2	5		T3	4
valid_sources[0x0d]	29355	1			T1	8		T3	1		T7	24
valid_sources[0x0e]	28080	1			T1	8		T3	2		T7	19
valid_sources[0x0f]	28464	1			T1	5		T3	1		T7	38
valid_sources[0x10]	28770	1			T1	6		T3	1		T7	37
valid_sources[0x11]	29956	1			T1	3		T2	18		T7	29
valid_sources[0x12]	28524	1			T1	12		T2	6		T7	29
valid_sources[0x13]	29399	1			T1	3		T3	2		T7	44
valid_sources[0x14]	28510	1			T1	5		T3	3		T7	20
valid_sources[0x15]	28793	1			T1	6		T7	21		T9	25
valid_sources[0x16]	30034	1			T1	7		T7	21		T8	2
valid_sources[0x17]	29077	1			T1	8		T7	24		T8	1
valid_sources[0x18]	27893	1			T1	10		T3	1		T7	22
valid_sources[0x19]	27506	1			T1	10		T2	9		T3	1
valid_sources[0x1a]	28516	1			T2	1		T7	28		T9	2
valid_sources[0x1b]	29144	1			T1	7		T7	21		T8	2
valid_sources[0x1c]	29085	1			T1	4		T3	2		T7	18
valid_sources[0x1d]	28844	1			T1	9		T3	2		T7	31
valid_sources[0x1e]	29403	1			T1	9		T2	10		T3	2
valid_sources[0x1f]	28251	1			T1	7		T3	1		T7	34
valid_sources[0x20]	29595	1			T1	14		T3	1		T7	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26446

1

T1

10

T3

2

T7

27

values[0x0]

all_enables

biggest_size

199131

1

T1

18

T2

16

T3

2

values[0x1]

all_enables

biggest_size

26397

1

T1

20

T2

2

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1591865	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259197

1

T1

52

T2

19

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	632256	1			T1	205		T2	58		T3	42
values[0x0]	585164	1			T1	34		T2	50		T3	11
values[0x1]	633642	1			T1	186		T2	47		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1221773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

629289

1

T1

171

T2

53

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28162	1			T1	6		T3	1		T7	40
valid_sources[0x01]	29316	1			T1	7		T2	5		T3	3
valid_sources[0x02]	29345	1			T1	5		T2	8		T3	3
valid_sources[0x03]	29027	1			T1	11		T2	6		T3	2
valid_sources[0x04]	29135	1			T1	8		T3	2		T7	31
valid_sources[0x05]	28464	1			T1	3		T3	1		T7	39
valid_sources[0x06]	28993	1			T1	4		T2	2		T3	2
valid_sources[0x07]	29158	1			T1	6		T3	1		T7	42
valid_sources[0x08]	29126	1			T1	8		T2	8		T7	11
valid_sources[0x09]	29100	1			T1	5		T3	2		T7	26
valid_sources[0x0a]	28558	1			T1	6		T2	1		T3	1
valid_sources[0x0b]	28660	1			T1	10		T3	1		T7	2
valid_sources[0x0c]	29159	1			T1	5		T3	3		T7	10
valid_sources[0x0d]	29738	1			T1	14		T2	14		T7	19
valid_sources[0x0e]	29083	1			T1	4		T3	1		T7	41
valid_sources[0x0f]	28661	1			T1	6		T3	1		T7	45
valid_sources[0x10]	28979	1			T1	4		T2	2		T7	25
valid_sources[0x11]	28970	1			T1	4		T7	37		T8	4
valid_sources[0x12]	28584	1			T1	4		T2	1		T3	1
valid_sources[0x13]	28877	1			T1	6		T2	1		T7	33
valid_sources[0x14]	28794	1			T1	5		T2	4		T7	29
valid_sources[0x15]	28777	1			T1	3		T7	17		T8	1
valid_sources[0x16]	29226	1			T1	9		T2	11		T3	3
valid_sources[0x17]	28527	1			T1	10		T2	1		T3	2
valid_sources[0x18]	28577	1			T1	5		T2	2		T3	1
valid_sources[0x19]	28732	1			T1	13		T2	2		T7	46
valid_sources[0x1a]	28639	1			T1	3		T7	32		T8	1
valid_sources[0x1b]	29334	1			T1	4		T2	5		T3	1
valid_sources[0x1c]	29427	1			T1	5		T2	1		T3	4
valid_sources[0x1d]	28744	1			T1	6		T2	2		T7	17
valid_sources[0x1e]	29593	1			T1	9		T3	1		T7	34
valid_sources[0x1f]	28622	1			T1	7		T3	1		T7	23
valid_sources[0x20]	29071	1			T1	11		T2	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27141

1

T1

18

T3

3

T7

23

values[0x0]

all_enables

biggest_size

205087

1

T1

17

T2

17

T3

4

values[0x1]

all_enables

biggest_size

26969

1

T1

17

T2

2

T3

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1590441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253443

1

T1

44

T2

20

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	625250	1			T1	188		T2	48		T3	37
values[0x0]	593756	1			T1	36		T2	40		T3	9
values[0x1]	624878	1			T1	198		T2	47		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1228883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615001

1

T1

157

T2

48

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29464	1			T1	7		T2	5		T3	1
valid_sources[0x01]	29104	1			T1	5		T2	1		T3	2
valid_sources[0x02]	28782	1			T1	11		T2	1		T3	2
valid_sources[0x03]	28537	1			T1	12		T3	2		T7	23
valid_sources[0x04]	28309	1			T1	5		T2	1		T3	1
valid_sources[0x05]	28949	1			T1	5		T2	1		T3	1
valid_sources[0x06]	28941	1			T1	4		T2	5		T3	3
valid_sources[0x07]	29272	1			T1	6		T2	3		T3	2
valid_sources[0x08]	29179	1			T1	10		T2	1		T3	2
valid_sources[0x09]	27902	1			T1	8		T2	1		T3	1
valid_sources[0x0a]	29764	1			T1	6		T2	1		T7	33
valid_sources[0x0b]	28794	1			T1	9		T2	2		T7	21
valid_sources[0x0c]	28644	1			T1	5		T2	6		T3	3
valid_sources[0x0d]	29828	1			T1	5		T2	2		T7	36
valid_sources[0x0e]	28850	1			T1	9		T2	4		T3	3
valid_sources[0x0f]	28024	1			T1	6		T2	3		T3	2
valid_sources[0x10]	29309	1			T1	10		T2	1		T3	1
valid_sources[0x11]	28683	1			T1	12		T3	3		T7	34
valid_sources[0x12]	28870	1			T1	7		T2	5		T7	28
valid_sources[0x13]	28263	1			T1	4		T3	2		T7	21
valid_sources[0x14]	29152	1			T1	10		T2	1		T3	2
valid_sources[0x15]	28653	1			T1	4		T2	4		T3	1
valid_sources[0x16]	28440	1			T1	6		T2	2		T7	40
valid_sources[0x17]	28782	1			T1	6		T2	3		T3	1
valid_sources[0x18]	28504	1			T1	7		T2	3		T7	23
valid_sources[0x19]	29043	1			T1	5		T2	3		T3	2
valid_sources[0x1a]	28987	1			T1	7		T2	3		T3	2
valid_sources[0x1b]	28413	1			T1	5		T2	2		T7	27
valid_sources[0x1c]	28409	1			T1	4		T2	1		T3	2
valid_sources[0x1d]	28506	1			T1	3		T2	1		T3	4
valid_sources[0x1e]	29162	1			T1	1		T2	1		T7	21
valid_sources[0x1f]	28721	1			T1	7		T2	3		T3	3
valid_sources[0x20]	28759	1			T1	6		T2	2		T7	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26535

1

T1

13

T2

3

T3

3

values[0x0]

all_enables

biggest_size

200377

1

T1

15

T2

15

T3

3

values[0x1]

all_enables

biggest_size

26531

1

T1

16

T2

2

T3

3