Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_27.fifo_h.reqfifo

Module Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	97.50	84.09			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	183939855	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	183939855	0	0
T1	47470	23871	0	0
T2	333429	125974	0	0
T3	40808	11530	0	0
T7	43417	18336	0	0
T8	49544	14012	0	0
T9	13889	5998	0	0
T10	84485	4027	0	0
T11	10395	6176	0	0
T12	2328	394	0	0
T13	31440	11683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	68844205	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	68844205	0	0
T1	47470	9073	0	0
T2	333429	58976	0	0
T3	40808	3393	0	0
T7	43417	5240	0	0
T8	49544	4662	0	0
T9	13889	1544	0	0
T10	84485	10831	0	0
T11	10395	2485	0	0
T12	2328	139	0	0
T13	31440	11444	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	1683343	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1683343	0	0
T1	47470	1806	0	0
T2	333429	49	0	0
T3	40808	383	0	0
T7	43417	5379	0	0
T8	49544	454	0	0
T9	13889	170	0	0
T10	84485	425	0	0
T11	10395	309	0	0
T12	2328	37	0	0
T13	31440	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	17400248	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	17400248	0	0
T1	47470	1794	0	0
T2	333429	13576	0	0
T3	40808	590	0	0
T7	43417	1845	0	0
T8	49544	912	0	0
T9	13889	311	0	0
T10	84485	2656	0	0
T11	10395	308	0	0
T12	2328	37	0	0
T13	31440	1349	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	1856201	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1856201	0	0
T1	47470	3536	0	0
T2	333429	45	0	0
T3	40808	326	0	0
T7	43417	660	0	0
T8	49544	385	0	0
T9	13889	237	0	0
T10	84485	360	0	0
T11	10395	366	0	0
T12	2328	51	0	0
T13	31440	206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	16888281	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	16888281	0	0
T1	47470	2052	0	0
T2	333429	13234	0	0
T3	40808	588	0	0
T7	43417	1167	0	0
T8	49544	719	0	0
T9	13889	329	0	0
T10	84485	2634	0	0
T11	10395	310	0	0
T12	2328	38	0	0
T13	31440	1213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	10172362	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	10172362	0	0
T1	47470	2925	0	0
T2	333429	135	0	0
T3	40808	1730	0	0
T7	43417	2851	0	0
T8	49544	2372	0	0
T9	13889	1036	0	0
T10	84485	2876	0	0
T11	10395	320	0	0
T12	2328	28	0	0
T13	31440	1186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	16976739	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	16976739	0	0
T1	47470	2324	0	0
T2	333429	11695	0	0
T3	40808	748	0	0
T7	43417	1198	0	0
T8	49544	938	0	0
T9	13889	427	0	0
T10	84485	2884	0	0
T11	10395	319	0	0
T12	2328	28	0	0
T13	31440	1218	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	1793871	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1793871	0	0
T1	47470	2686	0	0
T2	333429	43	0	0
T3	40808	360	0	0
T7	43417	501	0	0
T8	49544	458	0	0
T9	13889	258	0	0
T10	84485	358	0	0
T11	10395	351	0	0
T12	2328	47	0	0
T13	31440	261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	16776938	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	16776938	0	0
T1	47470	2032	0	0
T2	333429	20471	0	0
T3	40808	595	0	0
T7	43417	1029	0	0
T8	49544	909	0	0
T9	13889	367	0	0
T10	84485	2597	0	0
T11	10395	295	0	0
T12	2328	36	0	0
T13	31440	1392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	2	2	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Excluded	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	13623829	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	427134500	13623829	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	13623829	0	0
T1	47470	2040	0	0
T2	333429	219	0	0
T3	40808	2614	0	0
T7	43417	11834	0	0
T8	49544	3198	0	0
T9	13889	1287	0	0
T10	84485	3660	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	1756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	13623829	0	0
T1	47470	2040	0	0
T2	333429	219	0	0
T3	40808	2614	0	0
T7	43417	11834	0	0
T8	49544	3198	0	0
T9	13889	1287	0	0
T10	84485	3660	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	1756	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	21810689	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	427134500	21810689	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	21810689	0	0
T1	47470	2040	0	0
T2	333429	16056	0	0
T3	40808	941	0	0
T7	43417	3711	0	0
T8	49544	1151	0	0
T9	13889	357	0	0
T10	84485	3203	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	1450	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	21810689	0	0
T1	47470	2040	0	0
T2	333429	16056	0	0
T3	40808	941	0	0
T7	43417	3711	0	0
T8	49544	1151	0	0
T9	13889	357	0	0
T10	84485	3203	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	1450	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	1683343	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1683343	0	0
T1	47470	1806	0	0
T2	333429	49	0	0
T3	40808	383	0	0
T7	43417	5379	0	0
T8	49544	454	0	0
T9	13889	170	0	0
T10	84485	425	0	0
T11	10395	309	0	0
T12	2328	37	0	0
T13	31440	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	17400248	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	17400248	0	0
T1	47470	1794	0	0
T2	333429	13576	0	0
T3	40808	590	0	0
T7	43417	1845	0	0
T8	49544	912	0	0
T9	13889	311	0	0
T10	84485	2656	0	0
T11	10395	308	0	0
T12	2328	37	0	0
T13	31440	1349	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0