SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.31 | 100.00 | 81.25 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.57 | 97.50 | 80.56 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.75 | 100.00 | 75.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.88 | 97.50 | 77.78 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 422764 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 422764 | 0 | 0 |
T1 | 47470 | 125 | 0 | 0 |
T2 | 333429 | 10 | 0 | 0 |
T3 | 40808 | 59 | 0 | 0 |
T7 | 43417 | 4759 | 0 | 0 |
T8 | 49544 | 48 | 0 | 0 |
T9 | 13889 | 3 | 0 | 0 |
T10 | 84485 | 69 | 0 | 0 |
T11 | 10395 | 48 | 0 | 0 |
T12 | 2328 | 6 | 0 | 0 |
T13 | 31440 | 29 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 3850098 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 3850098 | 0 | 0 |
T1 | 47470 | 123 | 0 | 0 |
T2 | 333429 | 2476 | 0 | 0 |
T3 | 40808 | 236 | 0 | 0 |
T7 | 43417 | 1075 | 0 | 0 |
T8 | 49544 | 113 | 0 | 0 |
T9 | 13889 | 26 | 0 | 0 |
T10 | 84485 | 494 | 0 | 0 |
T11 | 10395 | 48 | 0 | 0 |
T12 | 2328 | 6 | 0 | 0 |
T13 | 31440 | 75 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 543663 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 543663 | 0 | 0 |
T1 | 47470 | 123 | 0 | 0 |
T2 | 333429 | 4 | 0 | 0 |
T3 | 40808 | 83 | 0 | 0 |
T7 | 43417 | 5630 | 0 | 0 |
T8 | 49544 | 93 | 0 | 0 |
T9 | 13889 | 21 | 0 | 0 |
T10 | 84485 | 53 | 0 | 0 |
T11 | 10395 | 51 | 0 | 0 |
T12 | 2328 | 7 | 0 | 0 |
T13 | 31440 | 32 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 560343 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 560343 | 0 | 0 |
T1 | 47470 | 123 | 0 | 0 |
T2 | 333429 | 4 | 0 | 0 |
T3 | 40808 | 115 | 0 | 0 |
T7 | 43417 | 791 | 0 | 0 |
T8 | 49544 | 126 | 0 | 0 |
T9 | 13889 | 20 | 0 | 0 |
T10 | 84485 | 53 | 0 | 0 |
T11 | 10395 | 51 | 0 | 0 |
T12 | 2328 | 7 | 0 | 0 |
T13 | 31440 | 26 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 13566176 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 427134500 | 13566176 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 13566176 | 0 | 0 |
T1 | 47470 | 2753 | 0 | 0 |
T2 | 333429 | 191 | 0 | 0 |
T3 | 40808 | 2431 | 0 | 0 |
T7 | 43417 | 3102 | 0 | 0 |
T8 | 49544 | 2963 | 0 | 0 |
T9 | 13889 | 1168 | 0 | 0 |
T10 | 84485 | 3381 | 0 | 0 |
T11 | 10395 | 391 | 0 | 0 |
T12 | 2328 | 57 | 0 | 0 |
T13 | 31440 | 1592 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 13566176 | 0 | 0 |
T1 | 47470 | 2753 | 0 | 0 |
T2 | 333429 | 191 | 0 | 0 |
T3 | 40808 | 2431 | 0 | 0 |
T7 | 43417 | 3102 | 0 | 0 |
T8 | 49544 | 2963 | 0 | 0 |
T9 | 13889 | 1168 | 0 | 0 |
T10 | 84485 | 3381 | 0 | 0 |
T11 | 10395 | 391 | 0 | 0 |
T12 | 2328 | 57 | 0 | 0 |
T13 | 31440 | 1592 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 20994245 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 427134500 | 20994245 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 20994245 | 0 | 0 |
T1 | 47470 | 2753 | 0 | 0 |
T2 | 333429 | 14700 | 0 | 0 |
T3 | 40808 | 998 | 0 | 0 |
T7 | 43417 | 1167 | 0 | 0 |
T8 | 49544 | 921 | 0 | 0 |
T9 | 13889 | 392 | 0 | 0 |
T10 | 84485 | 3155 | 0 | 0 |
T11 | 10395 | 391 | 0 | 0 |
T12 | 2328 | 57 | 0 | 0 |
T13 | 31440 | 1323 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 20994245 | 0 | 0 |
T1 | 47470 | 2753 | 0 | 0 |
T2 | 333429 | 14700 | 0 | 0 |
T3 | 40808 | 998 | 0 | 0 |
T7 | 43417 | 1167 | 0 | 0 |
T8 | 49544 | 921 | 0 | 0 |
T9 | 13889 | 392 | 0 | 0 |
T10 | 84485 | 3155 | 0 | 0 |
T11 | 10395 | 391 | 0 | 0 |
T12 | 2328 | 57 | 0 | 0 |
T13 | 31440 | 1323 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 1856201 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 1856201 | 0 | 0 |
T1 | 47470 | 3536 | 0 | 0 |
T2 | 333429 | 45 | 0 | 0 |
T3 | 40808 | 326 | 0 | 0 |
T7 | 43417 | 660 | 0 | 0 |
T8 | 49544 | 385 | 0 | 0 |
T9 | 13889 | 237 | 0 | 0 |
T10 | 84485 | 360 | 0 | 0 |
T11 | 10395 | 366 | 0 | 0 |
T12 | 2328 | 51 | 0 | 0 |
T13 | 31440 | 206 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 16888281 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 16888281 | 0 | 0 |
T1 | 47470 | 2052 | 0 | 0 |
T2 | 333429 | 13234 | 0 | 0 |
T3 | 40808 | 588 | 0 | 0 |
T7 | 43417 | 1167 | 0 | 0 |
T8 | 49544 | 719 | 0 | 0 |
T9 | 13889 | 329 | 0 | 0 |
T10 | 84485 | 2634 | 0 | 0 |
T11 | 10395 | 310 | 0 | 0 |
T12 | 2328 | 38 | 0 | 0 |
T13 | 31440 | 1213 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 481370 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 481370 | 0 | 0 |
T1 | 47470 | 1512 | 0 | 0 |
T2 | 333429 | 4 | 0 | 0 |
T3 | 40808 | 64 | 0 | 0 |
T7 | 43417 | 0 | 0 | 0 |
T8 | 49544 | 54 | 0 | 0 |
T9 | 13889 | 27 | 0 | 0 |
T10 | 84485 | 67 | 0 | 0 |
T11 | 10395 | 46 | 0 | 0 |
T12 | 2328 | 8 | 0 | 0 |
T13 | 31440 | 33 | 0 | 0 |
T14 | 0 | 58 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 3555612 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 3555612 | 0 | 0 |
T1 | 47470 | 380 | 0 | 0 |
T2 | 333429 | 1454 | 0 | 0 |
T3 | 40808 | 340 | 0 | 0 |
T7 | 43417 | 0 | 0 | 0 |
T8 | 49544 | 114 | 0 | 0 |
T9 | 13889 | 50 | 0 | 0 |
T10 | 84485 | 466 | 0 | 0 |
T11 | 10395 | 40 | 0 | 0 |
T12 | 2328 | 8 | 0 | 0 |
T13 | 31440 | 42 | 0 | 0 |
T14 | 0 | 50 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 604247 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 604247 | 0 | 0 |
T1 | 47470 | 1159 | 0 | 0 |
T2 | 333429 | 3 | 0 | 0 |
T3 | 40808 | 47 | 0 | 0 |
T7 | 43417 | 0 | 0 | 0 |
T8 | 49544 | 65 | 0 | 0 |
T9 | 13889 | 18 | 0 | 0 |
T10 | 84485 | 61 | 0 | 0 |
T11 | 10395 | 45 | 0 | 0 |
T12 | 2328 | 11 | 0 | 0 |
T13 | 31440 | 31 | 0 | 0 |
T14 | 0 | 73 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 550352 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 550352 | 0 | 0 |
T1 | 47470 | 321 | 0 | 0 |
T2 | 333429 | 12 | 0 | 0 |
T3 | 40808 | 70 | 0 | 0 |
T7 | 43417 | 0 | 0 | 0 |
T8 | 49544 | 88 | 0 | 0 |
T9 | 13889 | 13 | 0 | 0 |
T10 | 84485 | 55 | 0 | 0 |
T11 | 10395 | 41 | 0 | 0 |
T12 | 2328 | 11 | 0 | 0 |
T13 | 31440 | 68 | 0 | 0 |
T14 | 0 | 70 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 13252049 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 13252049 | 0 | 0 |
T1 | 47470 | 3530 | 0 | 0 |
T2 | 333429 | 216 | 0 | 0 |
T3 | 40808 | 2285 | 0 | 0 |
T7 | 43417 | 2851 | 0 | 0 |
T8 | 49544 | 3188 | 0 | 0 |
T9 | 13889 | 1154 | 0 | 0 |
T10 | 84485 | 3622 | 0 | 0 |
T11 | 10395 | 420 | 0 | 0 |
T12 | 2328 | 36 | 0 | 0 |
T13 | 31440 | 1538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 427134500 | 21086037 | 0 | 0 |
DepthKnown_A | 427134500 | 427009449 | 0 | 0 |
RvalidKnown_A | 427134500 | 427009449 | 0 | 0 |
WreadyKnown_A | 427134500 | 427009449 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 21086037 | 0 | 0 |
T1 | 47470 | 3530 | 0 | 0 |
T2 | 333429 | 16215 | 0 | 0 |
T3 | 40808 | 1110 | 0 | 0 |
T7 | 43417 | 1198 | 0 | 0 |
T8 | 49544 | 1300 | 0 | 0 |
T9 | 13889 | 487 | 0 | 0 |
T10 | 84485 | 3376 | 0 | 0 |
T11 | 10395 | 420 | 0 | 0 |
T12 | 2328 | 36 | 0 | 0 |
T13 | 31440 | 1384 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 427134500 | 427009449 | 0 | 0 |
T1 | 47470 | 47331 | 0 | 0 |
T2 | 333429 | 333388 | 0 | 0 |
T3 | 40808 | 40778 | 0 | 0 |
T7 | 43417 | 43409 | 0 | 0 |
T8 | 49544 | 49504 | 0 | 0 |
T9 | 13889 | 13375 | 0 | 0 |
T10 | 84485 | 84406 | 0 | 0 |
T11 | 10395 | 10328 | 0 | 0 |
T12 | 2328 | 2289 | 0 | 0 |
T13 | 31440 | 31389 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |