Unified Coverage Report :: Module Instance :: tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo

Module Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	269961	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	269961	0	0
T1	47470	113	0	0
T2	333429	5	0	0
T3	40808	39	0	0
T7	43417	0	0	0
T8	49544	68	0	0
T9	13889	30	0	0
T10	84485	57	0	0
T11	10395	55	0	0
T12	2328	8	0	0
T13	31440	33	0	0
T14	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	2683075	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2683075	0	0
T1	47470	112	0	0
T2	333429	1769	0	0
T3	40808	305	0	0
T7	43417	0	0	0
T8	49544	152	0	0
T9	13889	150	0	0
T10	84485	386	0	0
T11	10395	50	0	0
T12	2328	8	0	0
T13	31440	73	0	0
T14	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	359234	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	359234	0	0
T1	47470	121	0	0
T2	333429	9	0	0
T3	40808	63	0	0
T7	43417	0	0	0
T8	49544	63	0	0
T9	13889	45	0	0
T10	84485	64	0	0
T11	10395	61	0	0
T12	2328	9	0	0
T13	31440	29	0	0
T14	0	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	580161	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	580161	0	0
T1	47470	120	0	0
T2	333429	103	0	0
T3	40808	101	0	0
T7	43417	0	0	0
T8	49544	89	0	0
T9	13889	32	0	0
T10	84485	64	0	0
T11	10395	59	0	0
T12	2328	9	0	0
T13	31440	38	0	0
T14	0	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3293889	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	427134500	3293889	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3293889	0	0
T1	47470	755	0	0
T2	333429	15	0	0
T3	40808	564	0	0
T7	43417	0	0	0
T8	49544	791	0	0
T9	13889	155	0	0
T10	84485	906	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	429	0	0
T14	0	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3293889	0	0
T1	47470	755	0	0
T2	333429	15	0	0
T3	40808	564	0	0
T7	43417	0	0	0
T8	49544	791	0	0
T9	13889	155	0	0
T10	84485	906	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	429	0	0
T14	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	4028448	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	427134500	4028448	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4028448	0	0
T1	47470	755	0	0
T2	333429	1287	0	0
T3	40808	349	0	0
T7	43417	0	0	0
T8	49544	199	0	0
T9	13889	28	0	0
T10	84485	465	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	151	0	0
T14	0	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4028448	0	0
T1	47470	755	0	0
T2	333429	1287	0	0
T3	40808	349	0	0
T7	43417	0	0	0
T8	49544	199	0	0
T9	13889	28	0	0
T10	84485	465	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	151	0	0
T14	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	273988	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	273988	0	0
T1	47470	622	0	0
T2	333429	2	0	0
T3	40808	35	0	0
T7	43417	0	0	0
T8	49544	56	0	0
T9	13889	3	0	0
T10	84485	56	0	0
T11	10395	52	0	0
T12	2328	10	0	0
T13	31440	28	0	0
T14	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3370023	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3370023	0	0
T1	47470	430	0	0
T2	333429	558	0	0
T3	40808	282	0	0
T7	43417	0	0	0
T8	49544	124	0	0
T9	13889	15	0	0
T10	84485	402	0	0
T11	10395	52	0	0
T12	2328	9	0	0
T13	31440	84	0	0
T14	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	361485	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	361485	0	0
T1	47470	415	0	0
T2	333429	4	0	0
T3	40808	48	0	0
T7	43417	0	0	0
T8	49544	60	0	0
T9	13889	29	0	0
T10	84485	90	0	0
T11	10395	54	0	0
T12	2328	8	0	0
T13	31440	44	0	0
T14	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	658425	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	658425	0	0
T1	47470	325	0	0
T2	333429	729	0	0
T3	40808	67	0	0
T7	43417	0	0	0
T8	49544	75	0	0
T9	13889	13	0	0
T10	84485	63	0	0
T11	10395	54	0	0
T12	2328	8	0	0
T13	31440	67	0	0
T14	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3332881	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	427134500	3332881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3332881	0	0
T1	47470	746	0	0
T2	333429	32	0	0
T3	40808	707	0	0
T7	43417	0	0	0
T8	49544	885	0	0
T9	13889	243	0	0
T10	84485	1044	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	396	0	0
T14	0	122	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3332881	0	0
T1	47470	746	0	0
T2	333429	32	0	0
T3	40808	707	0	0
T7	43417	0	0	0
T8	49544	885	0	0
T9	13889	243	0	0
T10	84485	1044	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	396	0	0
T14	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	4434841	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	427134500	4434841	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4434841	0	0
T1	47470	746	0	0
T2	333429	2706	0	0
T3	40808	315	0	0
T7	43417	0	0	0
T8	49544	195	0	0
T9	13889	103	0	0
T10	84485	632	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	108	0	0
T14	0	122	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4434841	0	0
T1	47470	746	0	0
T2	333429	2706	0	0
T3	40808	315	0	0
T7	43417	0	0	0
T8	49544	195	0	0
T9	13889	103	0	0
T10	84485	632	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	108	0	0
T14	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	297549	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	297549	0	0
T1	47470	643	0	0
T2	333429	5	0	0
T3	40808	54	0	0
T7	43417	0	0	0
T8	49544	43	0	0
T9	13889	12	0	0
T10	84485	70	0	0
T11	10395	75	0	0
T12	2328	7	0	0
T13	31440	36	0	0
T14	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3693891	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3693891	0	0
T1	47470	381	0	0
T2	333429	2700	0	0
T3	40808	258	0	0
T7	43417	0	0	0
T8	49544	88	0	0
T9	13889	82	0	0
T10	84485	573	0	0
T11	10395	70	0	0
T12	2328	7	0	0
T13	31440	64	0	0
T14	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0