Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3329137 |
0 |
0 |
T1 |
47470 |
272 |
0 |
0 |
T2 |
333429 |
35 |
0 |
0 |
T3 |
40808 |
595 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
751 |
0 |
0 |
T9 |
13889 |
78 |
0 |
0 |
T10 |
84485 |
965 |
0 |
0 |
T11 |
10395 |
95 |
0 |
0 |
T12 |
2328 |
16 |
0 |
0 |
T13 |
31440 |
416 |
0 |
0 |
T14 |
0 |
109 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3329137 |
0 |
0 |
T1 |
47470 |
272 |
0 |
0 |
T2 |
333429 |
35 |
0 |
0 |
T3 |
40808 |
595 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
751 |
0 |
0 |
T9 |
13889 |
78 |
0 |
0 |
T10 |
84485 |
965 |
0 |
0 |
T11 |
10395 |
95 |
0 |
0 |
T12 |
2328 |
16 |
0 |
0 |
T13 |
31440 |
416 |
0 |
0 |
T14 |
0 |
109 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
4106182 |
0 |
0 |
T1 |
47470 |
272 |
0 |
0 |
T2 |
333429 |
1530 |
0 |
0 |
T3 |
40808 |
292 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
194 |
0 |
0 |
T9 |
13889 |
37 |
0 |
0 |
T10 |
84485 |
457 |
0 |
0 |
T11 |
10395 |
95 |
0 |
0 |
T12 |
2328 |
16 |
0 |
0 |
T13 |
31440 |
96 |
0 |
0 |
T14 |
0 |
109 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
4106182 |
0 |
0 |
T1 |
47470 |
272 |
0 |
0 |
T2 |
333429 |
1530 |
0 |
0 |
T3 |
40808 |
292 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
194 |
0 |
0 |
T9 |
13889 |
37 |
0 |
0 |
T10 |
84485 |
457 |
0 |
0 |
T11 |
10395 |
95 |
0 |
0 |
T12 |
2328 |
16 |
0 |
0 |
T13 |
31440 |
96 |
0 |
0 |
T14 |
0 |
109 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
306257 |
0 |
0 |
T1 |
47470 |
136 |
0 |
0 |
T2 |
333429 |
7 |
0 |
0 |
T3 |
40808 |
47 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
50 |
0 |
0 |
T9 |
13889 |
6 |
0 |
0 |
T10 |
84485 |
66 |
0 |
0 |
T11 |
10395 |
49 |
0 |
0 |
T12 |
2328 |
5 |
0 |
0 |
T13 |
31440 |
28 |
0 |
0 |
T14 |
0 |
59 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3399796 |
0 |
0 |
T1 |
47470 |
133 |
0 |
0 |
T2 |
333429 |
1527 |
0 |
0 |
T3 |
40808 |
226 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
120 |
0 |
0 |
T9 |
13889 |
32 |
0 |
0 |
T10 |
84485 |
396 |
0 |
0 |
T11 |
10395 |
46 |
0 |
0 |
T12 |
2328 |
5 |
0 |
0 |
T13 |
31440 |
59 |
0 |
0 |
T14 |
0 |
56 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
397564 |
0 |
0 |
T1 |
47470 |
139 |
0 |
0 |
T2 |
333429 |
3 |
0 |
0 |
T3 |
40808 |
67 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
58 |
0 |
0 |
T9 |
13889 |
5 |
0 |
0 |
T10 |
84485 |
61 |
0 |
0 |
T11 |
10395 |
50 |
0 |
0 |
T12 |
2328 |
11 |
0 |
0 |
T13 |
31440 |
33 |
0 |
0 |
T14 |
0 |
53 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
706386 |
0 |
0 |
T1 |
47470 |
139 |
0 |
0 |
T2 |
333429 |
3 |
0 |
0 |
T3 |
40808 |
66 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
74 |
0 |
0 |
T9 |
13889 |
5 |
0 |
0 |
T10 |
84485 |
61 |
0 |
0 |
T11 |
10395 |
49 |
0 |
0 |
T12 |
2328 |
11 |
0 |
0 |
T13 |
31440 |
37 |
0 |
0 |
T14 |
0 |
53 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3365664 |
0 |
0 |
T1 |
47470 |
747 |
0 |
0 |
T2 |
333429 |
43 |
0 |
0 |
T3 |
40808 |
803 |
0 |
0 |
T7 |
43417 |
5261 |
0 |
0 |
T8 |
49544 |
549 |
0 |
0 |
T9 |
13889 |
103 |
0 |
0 |
T10 |
84485 |
762 |
0 |
0 |
T11 |
10395 |
112 |
0 |
0 |
T12 |
2328 |
17 |
0 |
0 |
T13 |
31440 |
455 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3365664 |
0 |
0 |
T1 |
47470 |
747 |
0 |
0 |
T2 |
333429 |
43 |
0 |
0 |
T3 |
40808 |
803 |
0 |
0 |
T7 |
43417 |
5261 |
0 |
0 |
T8 |
49544 |
549 |
0 |
0 |
T9 |
13889 |
103 |
0 |
0 |
T10 |
84485 |
762 |
0 |
0 |
T11 |
10395 |
112 |
0 |
0 |
T12 |
2328 |
17 |
0 |
0 |
T13 |
31440 |
455 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
4767748 |
0 |
0 |
T1 |
47470 |
747 |
0 |
0 |
T2 |
333429 |
1973 |
0 |
0 |
T3 |
40808 |
455 |
0 |
0 |
T7 |
43417 |
1828 |
0 |
0 |
T8 |
49544 |
155 |
0 |
0 |
T9 |
13889 |
88 |
0 |
0 |
T10 |
84485 |
416 |
0 |
0 |
T11 |
10395 |
112 |
0 |
0 |
T12 |
2328 |
17 |
0 |
0 |
T13 |
31440 |
144 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
4767748 |
0 |
0 |
T1 |
47470 |
747 |
0 |
0 |
T2 |
333429 |
1973 |
0 |
0 |
T3 |
40808 |
455 |
0 |
0 |
T7 |
43417 |
1828 |
0 |
0 |
T8 |
49544 |
155 |
0 |
0 |
T9 |
13889 |
88 |
0 |
0 |
T10 |
84485 |
416 |
0 |
0 |
T11 |
10395 |
112 |
0 |
0 |
T12 |
2328 |
17 |
0 |
0 |
T13 |
31440 |
144 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
369061 |
0 |
0 |
T1 |
47470 |
1139 |
0 |
0 |
T2 |
333429 |
4 |
0 |
0 |
T3 |
40808 |
70 |
0 |
0 |
T7 |
43417 |
3065 |
0 |
0 |
T8 |
49544 |
44 |
0 |
0 |
T9 |
13889 |
9 |
0 |
0 |
T10 |
84485 |
43 |
0 |
0 |
T11 |
10395 |
63 |
0 |
0 |
T12 |
2328 |
8 |
0 |
0 |
T13 |
31440 |
29 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3951219 |
0 |
0 |
T1 |
47470 |
377 |
0 |
0 |
T2 |
333429 |
1701 |
0 |
0 |
T3 |
40808 |
394 |
0 |
0 |
T7 |
43417 |
871 |
0 |
0 |
T8 |
49544 |
96 |
0 |
0 |
T9 |
13889 |
80 |
0 |
0 |
T10 |
84485 |
359 |
0 |
0 |
T11 |
10395 |
59 |
0 |
0 |
T12 |
2328 |
8 |
0 |
0 |
T13 |
31440 |
89 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
461744 |
0 |
0 |
T1 |
47470 |
870 |
0 |
0 |
T2 |
333429 |
3 |
0 |
0 |
T3 |
40808 |
62 |
0 |
0 |
T7 |
43417 |
4186 |
0 |
0 |
T8 |
49544 |
65 |
0 |
0 |
T9 |
13889 |
7 |
0 |
0 |
T10 |
84485 |
59 |
0 |
0 |
T11 |
10395 |
55 |
0 |
0 |
T12 |
2328 |
9 |
0 |
0 |
T13 |
31440 |
46 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
816529 |
0 |
0 |
T1 |
47470 |
370 |
0 |
0 |
T2 |
333429 |
272 |
0 |
0 |
T3 |
40808 |
61 |
0 |
0 |
T7 |
43417 |
957 |
0 |
0 |
T8 |
49544 |
59 |
0 |
0 |
T9 |
13889 |
8 |
0 |
0 |
T10 |
84485 |
57 |
0 |
0 |
T11 |
10395 |
53 |
0 |
0 |
T12 |
2328 |
9 |
0 |
0 |
T13 |
31440 |
55 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3291136 |
0 |
0 |
T1 |
47470 |
1118 |
0 |
0 |
T2 |
333429 |
86 |
0 |
0 |
T3 |
40808 |
567 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
870 |
0 |
0 |
T9 |
13889 |
3215 |
0 |
0 |
T10 |
84485 |
887 |
0 |
0 |
T11 |
10395 |
111 |
0 |
0 |
T12 |
2328 |
6 |
0 |
0 |
T13 |
31440 |
419 |
0 |
0 |
T14 |
0 |
111 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
3291136 |
0 |
0 |
T1 |
47470 |
1118 |
0 |
0 |
T2 |
333429 |
86 |
0 |
0 |
T3 |
40808 |
567 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
870 |
0 |
0 |
T9 |
13889 |
3215 |
0 |
0 |
T10 |
84485 |
887 |
0 |
0 |
T11 |
10395 |
111 |
0 |
0 |
T12 |
2328 |
6 |
0 |
0 |
T13 |
31440 |
419 |
0 |
0 |
T14 |
0 |
111 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
4942383 |
0 |
0 |
T1 |
47470 |
1118 |
0 |
0 |
T2 |
333429 |
1756 |
0 |
0 |
T3 |
40808 |
292 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
238 |
0 |
0 |
T9 |
13889 |
1192 |
0 |
0 |
T10 |
84485 |
446 |
0 |
0 |
T11 |
10395 |
111 |
0 |
0 |
T12 |
2328 |
6 |
0 |
0 |
T13 |
31440 |
130 |
0 |
0 |
T14 |
0 |
111 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
427009449 |
0 |
0 |
T1 |
47470 |
47331 |
0 |
0 |
T2 |
333429 |
333388 |
0 |
0 |
T3 |
40808 |
40778 |
0 |
0 |
T7 |
43417 |
43409 |
0 |
0 |
T8 |
49544 |
49504 |
0 |
0 |
T9 |
13889 |
13375 |
0 |
0 |
T10 |
84485 |
84406 |
0 |
0 |
T11 |
10395 |
10328 |
0 |
0 |
T12 |
2328 |
2289 |
0 |
0 |
T13 |
31440 |
31389 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427134500 |
4942383 |
0 |
0 |
T1 |
47470 |
1118 |
0 |
0 |
T2 |
333429 |
1756 |
0 |
0 |
T3 |
40808 |
292 |
0 |
0 |
T7 |
43417 |
0 |
0 |
0 |
T8 |
49544 |
238 |
0 |
0 |
T9 |
13889 |
1192 |
0 |
0 |
T10 |
84485 |
446 |
0 |
0 |
T11 |
10395 |
111 |
0 |
0 |
T12 |
2328 |
6 |
0 |
0 |
T13 |
31440 |
130 |
0 |
0 |
T14 |
0 |
111 |
0 |
0 |