Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	695007	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	695007	0	0
T1	47470	3752	0	0
T2	333429	12	0	0
T3	40808	49	0	0
T7	43417	846	0	0
T8	49544	58	0	0
T9	13889	22	0	0
T10	84485	61	0	0
T11	10395	85	0	0
T12	2328	3	0	0
T13	31440	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3206168	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3206168	0	0
T1	47470	350	0	0
T2	333429	1779	0	0
T3	40808	238	0	0
T7	43417	1422	0	0
T8	49544	155	0	0
T9	13889	77	0	0
T10	84485	449	0	0
T11	10395	54	0	0
T12	2328	3	0	0
T13	31440	116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	741754	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	741754	0	0
T1	47470	1463	0	0
T2	333429	12	0	0
T3	40808	37	0	0
T7	43417	930	0	0
T8	49544	80	0	0
T9	13889	9	0	0
T10	84485	55	0	0
T11	10395	94	0	0
T12	2328	3	0	0
T13	31440	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3829131	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3829131	0	0
T1	47470	320	0	0
T2	333429	3571	0	0
T3	40808	270	0	0
T7	43417	1353	0	0
T8	49544	130	0	0
T9	13889	76	0	0
T10	84485	324	0	0
T11	10395	57	0	0
T12	2328	3	0	0
T13	31440	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	651229	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	651229	0	0
T1	47470	163	0	0
T2	333429	12	0	0
T3	40808	61	0	0
T7	43417	1632	0	0
T8	49544	89	0	0
T9	13889	3	0	0
T10	84485	74	0	0
T11	10395	127	0	0
T12	2328	10	0	0
T13	31440	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3705204	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3705204	0	0
T1	47470	114	0	0
T2	333429	1033	0	0
T3	40808	303	0	0
T7	43417	882	0	0
T8	49544	74	0	0
T9	13889	27	0	0
T10	84485	362	0	0
T11	10395	55	0	0
T12	2328	6	0	0
T13	31440	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	293244	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	293244	0	0
T1	47470	117	0	0
T2	333429	7	0	0
T3	40808	52	0	0
T7	43417	2640	0	0
T8	49544	71	0	0
T9	13889	16	0	0
T10	84485	57	0	0
T11	10395	50	0	0
T12	2328	8	0	0
T13	31440	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3363044	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3363044	0	0
T1	47470	111	0	0
T2	333429	3116	0	0
T3	40808	291	0	0
T7	43417	936	0	0
T8	49544	115	0	0
T9	13889	115	0	0
T10	84485	474	0	0
T11	10395	46	0	0
T12	2328	7	0	0
T13	31440	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	298038	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	298038	0	0
T1	47470	499	0	0
T2	333429	7	0	0
T3	40808	33	0	0
T7	43417	0	0	0
T8	49544	53	0	0
T9	13889	9	0	0
T10	84485	57	0	0
T11	10395	43	0	0
T12	2328	8	0	0
T13	31440	39	0	0
T14	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3164676	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3164676	0	0
T1	47470	347	0	0
T2	333429	3135	0	0
T3	40808	234	0	0
T7	43417	0	0	0
T8	49544	148	0	0
T9	13889	61	0	0
T10	84485	466	0	0
T11	10395	42	0	0
T12	2328	7	0	0
T13	31440	82	0	0
T14	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	474104	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	474104	0	0
T1	47470	642	0	0
T2	333429	8	0	0
T3	40808	90	0	0
T7	43417	0	0	0
T8	49544	77	0	0
T9	13889	7	0	0
T10	84485	75	0	0
T11	10395	50	0	0
T12	2328	14	0	0
T13	31440	45	0	0
T14	0	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3501032	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3501032	0	0
T1	47470	400	0	0
T2	333429	2533	0	0
T3	40808	345	0	0
T7	43417	0	0	0
T8	49544	135	0	0
T9	13889	20	0	0
T10	84485	372	0	0
T11	10395	44	0	0
T12	2328	13	0	0
T13	31440	78	0	0
T14	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	283358	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	283358	0	0
T1	47470	1564	0	0
T2	333429	5	0	0
T3	40808	40	0	0
T7	43417	0	0	0
T8	49544	57	0	0
T9	13889	8	0	0
T10	84485	51	0	0
T11	10395	45	0	0
T12	2328	5	0	0
T13	31440	28	0	0
T14	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	4083955	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4083955	0	0
T1	47470	640	0	0
T2	333429	1129	0	0
T3	40808	255	0	0
T7	43417	0	0	0
T8	49544	87	0	0
T9	13889	99	0	0
T10	84485	341	0	0
T11	10395	44	0	0
T12	2328	5	0	0
T13	31440	56	0	0
T14	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0