Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	320449	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	320449	0	0
T1	47470	140	0	0
T2	333429	6	0	0
T3	40808	51	0	0
T7	43417	0	0	0
T8	49544	42	0	0
T9	13889	12	0	0
T10	84485	50	0	0
T11	10395	72	0	0
T12	2328	12	0	0
T13	31440	36	0	0
T14	0	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3758337	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3758337	0	0
T1	47470	138	0	0
T2	333429	1091	0	0
T3	40808	328	0	0
T7	43417	0	0	0
T8	49544	105	0	0
T9	13889	112	0	0
T10	84485	396	0	0
T11	10395	63	0	0
T12	2328	10	0	0
T13	31440	70	0	0
T14	0	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	269961	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	269961	0	0
T1	47470	113	0	0
T2	333429	5	0	0
T3	40808	39	0	0
T7	43417	0	0	0
T8	49544	68	0	0
T9	13889	30	0	0
T10	84485	57	0	0
T11	10395	55	0	0
T12	2328	8	0	0
T13	31440	33	0	0
T14	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	2683075	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2683075	0	0
T1	47470	112	0	0
T2	333429	1769	0	0
T3	40808	305	0	0
T7	43417	0	0	0
T8	49544	152	0	0
T9	13889	150	0	0
T10	84485	386	0	0
T11	10395	50	0	0
T12	2328	8	0	0
T13	31440	73	0	0
T14	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	273988	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	273988	0	0
T1	47470	622	0	0
T2	333429	2	0	0
T3	40808	35	0	0
T7	43417	0	0	0
T8	49544	56	0	0
T9	13889	3	0	0
T10	84485	56	0	0
T11	10395	52	0	0
T12	2328	10	0	0
T13	31440	28	0	0
T14	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3370023	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3370023	0	0
T1	47470	430	0	0
T2	333429	558	0	0
T3	40808	282	0	0
T7	43417	0	0	0
T8	49544	124	0	0
T9	13889	15	0	0
T10	84485	402	0	0
T11	10395	52	0	0
T12	2328	9	0	0
T13	31440	84	0	0
T14	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	297549	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	297549	0	0
T1	47470	643	0	0
T2	333429	5	0	0
T3	40808	54	0	0
T7	43417	0	0	0
T8	49544	43	0	0
T9	13889	12	0	0
T10	84485	70	0	0
T11	10395	75	0	0
T12	2328	7	0	0
T13	31440	36	0	0
T14	0	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3693891	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3693891	0	0
T1	47470	381	0	0
T2	333429	2700	0	0
T3	40808	258	0	0
T7	43417	0	0	0
T8	49544	88	0	0
T9	13889	82	0	0
T10	84485	573	0	0
T11	10395	70	0	0
T12	2328	7	0	0
T13	31440	64	0	0
T14	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	334516	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	334516	0	0
T1	47470	129	0	0
T2	333429	8	0	0
T3	40808	39	0	0
T7	43417	0	0	0
T8	49544	85	0	0
T9	13889	9	0	0
T10	84485	55	0	0
T11	10395	64	0	0
T12	2328	7	0	0
T13	31440	39	0	0
T14	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3686378	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3686378	0	0
T1	47470	128	0	0
T2	333429	1740	0	0
T3	40808	259	0	0
T7	43417	0	0	0
T8	49544	108	0	0
T9	13889	56	0	0
T10	84485	396	0	0
T11	10395	58	0	0
T12	2328	6	0	0
T13	31440	80	0	0
T14	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	316845	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	316845	0	0
T1	47470	1236	0	0
T2	333429	14	0	0
T3	40808	128	0	0
T7	43417	0	0	0
T8	49544	99	0	0
T9	13889	281	0	0
T10	84485	53	0	0
T11	10395	90	0	0
T12	2328	7	0	0
T13	31440	53	0	0
T14	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3588005	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3588005	0	0
T1	47470	430	0	0
T2	333429	2625	0	0
T3	40808	601	0	0
T7	43417	0	0	0
T8	49544	207	0	0
T9	13889	615	0	0
T10	84485	433	0	0
T11	10395	84	0	0
T12	2328	7	0	0
T13	31440	131	0	0
T14	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	306257	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	306257	0	0
T1	47470	136	0	0
T2	333429	7	0	0
T3	40808	47	0	0
T7	43417	0	0	0
T8	49544	50	0	0
T9	13889	6	0	0
T10	84485	66	0	0
T11	10395	49	0	0
T12	2328	5	0	0
T13	31440	28	0	0
T14	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427134500	3399796	0	0
DepthKnown_A	427134500	427009449	0	0
RvalidKnown_A	427134500	427009449	0	0
WreadyKnown_A	427134500	427009449	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3399796	0	0
T1	47470	133	0	0
T2	333429	1527	0	0
T3	40808	226	0	0
T7	43417	0	0	0
T8	49544	120	0	0
T9	13889	32	0	0
T10	84485	396	0	0
T11	10395	46	0	0
T12	2328	5	0	0
T13	31440	59	0	0
T14	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0