Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7846671	0	0
GntImpliesValid_A	2147483647	7846671	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7846671	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	460234621	0	0
ReadyAndValidImplyGrant_A	2147483647	7846671	0	0
ReqAndReadyImplyGrant_A	2147483647	7846671	0	0
ReqImpliesValid_A	2147483647	34399460	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	37509	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7846671	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1139280	1135944	0	0
T2	8002296	8001312	0	0
T3	979392	978672	0	0
T7	1042008	1041816	0	0
T8	1189056	1188096	0	0
T9	333336	321000	0	0
T10	2027640	2025744	0	0
T11	249480	247872	0	0
T12	55872	54936	0	0
T13	754560	753336	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7846671	0	0
T1	1139280	24939	0	0
T2	8002296	444	0	0
T3	979392	2949	0	0
T7	1042008	5054	0	0
T8	1189056	3701	0	0
T9	333336	1497	0	0
T10	2027640	4098	0	0
T11	249480	3792	0	0
T12	55872	479	0	0
T13	754560	1988	0	0
T14	0	1580	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7846671	0	0
T1	1139280	24939	0	0
T2	8002296	444	0	0
T3	979392	2949	0	0
T7	1042008	5054	0	0
T8	1189056	3701	0	0
T9	333336	1497	0	0
T10	2027640	4098	0	0
T11	249480	3792	0	0
T12	55872	479	0	0
T13	754560	1988	0	0
T14	0	1580	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1139280	1135944	0	0
T2	8002296	8001312	0	0
T3	979392	978672	0	0
T7	1042008	1041816	0	0
T8	1189056	1188096	0	0
T9	333336	321000	0	0
T10	2027640	2025744	0	0
T11	249480	247872	0	0
T12	55872	54936	0	0
T13	754560	753336	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1139280	1135944	0	0
T2	8002296	8001312	0	0
T3	979392	978672	0	0
T7	1042008	1041816	0	0
T8	1189056	1188096	0	0
T9	333336	321000	0	0
T10	2027640	2025744	0	0
T11	249480	247872	0	0
T12	55872	54936	0	0
T13	754560	753336	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7846671	0	0
T1	1139280	24939	0	0
T2	8002296	444	0	0
T3	979392	2949	0	0
T7	1042008	5054	0	0
T8	1189056	3701	0	0
T9	333336	1497	0	0
T10	2027640	4098	0	0
T11	249480	3792	0	0
T12	55872	479	0	0
T13	754560	1988	0	0
T14	0	1580	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	460234621	0	0
T1	1139280	20088	0	0
T2	8002296	279472	0	0
T3	979392	54288	0	0
T7	1042008	51914	0	0
T8	1189056	68523	0	0
T9	333336	19704	0	0
T10	2027640	112177	0	0
T11	249480	5824	0	0
T12	55872	732	0	0
T13	754560	41188	0	0
T14	0	646	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7846671	0	0
T1	1139280	24939	0	0
T2	8002296	444	0	0
T3	979392	2949	0	0
T7	1042008	5054	0	0
T8	1189056	3701	0	0
T9	333336	1497	0	0
T10	2027640	4098	0	0
T11	249480	3792	0	0
T12	55872	479	0	0
T13	754560	1988	0	0
T14	0	1580	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7846671	0	0
T1	1139280	24939	0	0
T2	8002296	444	0	0
T3	979392	2949	0	0
T7	1042008	5054	0	0
T8	1189056	3701	0	0
T9	333336	1497	0	0
T10	2027640	4098	0	0
T11	249480	3792	0	0
T12	55872	479	0	0
T13	754560	1988	0	0
T14	0	1580	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34399460	0	0
T1	1139280	39817	0	0
T2	8002296	684	0	0
T3	979392	5905	0	0
T7	1042008	31404	0	0
T8	1189056	7526	0	0
T9	333336	6250	0	0
T10	2027640	7693	0	0
T11	249480	4378	0	0
T12	55872	574	0	0
T13	754560	3968	0	0
T14	0	1709	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37509	0	21600
T1	94940	682	0	2
T2	666858	0	0	2
T3	81616	0	0	2
T7	86834	17	0	2
T8	99088	0	0	2
T9	27778	0	0	2
T10	168970	0	0	2
T11	20790	6	0	2
T12	4656	0	0	2
T13	62880	0	0	2
T14	0	7	0	0
T15	0	1	0	0
T16	0	3	0	0
T17	0	3	0	0
T18	0	12	0	0
T19	0	21	0	0
T20	0	11	0	0
T21	0	9	0	0
T22	0	4	0	0
T23	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1139280	1135944	0	0
T2	8002296	8001312	0	0
T3	979392	978672	0	0
T7	1042008	1041816	0	0
T8	1189056	1188096	0	0
T9	333336	321000	0	0
T10	2027640	2025744	0	0
T11	249480	247872	0	0
T12	55872	54936	0	0
T13	754560	753336	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7846671	0	0
T1	1139280	24939	0	0
T2	8002296	444	0	0
T3	979392	2949	0	0
T7	1042008	5054	0	0
T8	1189056	3701	0	0
T9	333336	1497	0	0
T10	2027640	4098	0	0
T11	249480	3792	0	0
T12	55872	479	0	0
T13	754560	1988	0	0
T14	0	1580	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	878033	0	0
GntImpliesValid_A	427134500	878033	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	878033	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	11972568	0	0
ReadyAndValidImplyGrant_A	427134500	878033	0	0
ReqAndReadyImplyGrant_A	427134500	878033	0	0
ReqImpliesValid_A	427134500	2473640	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	878033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	878033	0	0
T1	47470	2753	0	0
T2	333429	46	0	0
T3	40808	321	0	0
T7	43417	376	0	0
T8	49544	381	0	0
T9	13889	166	0	0
T10	84485	451	0	0
T11	10395	391	0	0
T12	2328	57	0	0
T13	31440	216	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	878033	0	0
T1	47470	2753	0	0
T2	333429	46	0	0
T3	40808	321	0	0
T7	43417	376	0	0
T8	49544	381	0	0
T9	13889	166	0	0
T10	84485	451	0	0
T11	10395	391	0	0
T12	2328	57	0	0
T13	31440	216	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	878033	0	0
T1	47470	2753	0	0
T2	333429	46	0	0
T3	40808	321	0	0
T7	43417	376	0	0
T8	49544	381	0	0
T9	13889	166	0	0
T10	84485	451	0	0
T11	10395	391	0	0
T12	2328	57	0	0
T13	31440	216	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	11972568	0	0
T1	47470	1666	0	0
T2	333429	186	0	0
T3	40808	2317	0	0
T7	43417	2819	0	0
T8	49544	2841	0	0
T9	13889	1071	0	0
T10	84485	3345	0	0
T11	10395	329	0	0
T12	2328	45	0	0
T13	31440	1539	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	878033	0	0
T1	47470	2753	0	0
T2	333429	46	0	0
T3	40808	321	0	0
T7	43417	376	0	0
T8	49544	381	0	0
T9	13889	166	0	0
T10	84485	451	0	0
T11	10395	391	0	0
T12	2328	57	0	0
T13	31440	216	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	878033	0	0
T1	47470	2753	0	0
T2	333429	46	0	0
T3	40808	321	0	0
T7	43417	376	0	0
T8	49544	381	0	0
T9	13889	166	0	0
T10	84485	451	0	0
T11	10395	391	0	0
T12	2328	57	0	0
T13	31440	216	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2473640	0	0
T1	47470	3842	0	0
T2	333429	52	0	0
T3	40808	436	0	0
T7	43417	660	0	0
T8	49544	504	0	0
T9	13889	269	0	0
T10	84485	488	0	0
T11	10395	454	0	0
T12	2328	70	0	0
T13	31440	270	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	878033	0	0
T1	47470	2753	0	0
T2	333429	46	0	0
T3	40808	321	0	0
T7	43417	376	0	0
T8	49544	381	0	0
T9	13889	166	0	0
T10	84485	451	0	0
T11	10395	391	0	0
T12	2328	57	0	0
T13	31440	216	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	868421	0	0
GntImpliesValid_A	427134500	868421	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	868421	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	11651479	0	0
ReadyAndValidImplyGrant_A	427134500	868421	0	0
ReqAndReadyImplyGrant_A	427134500	868421	0	0
ReqImpliesValid_A	427134500	2372702	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	868421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	868421	0	0
T1	47470	2820	0	0
T2	333429	56	0	0
T3	40808	342	0	0
T7	43417	352	0	0
T8	49544	421	0	0
T9	13889	172	0	0
T10	84485	441	0	0
T11	10395	397	0	0
T12	2328	62	0	0
T13	31440	224	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	868421	0	0
T1	47470	2820	0	0
T2	333429	56	0	0
T3	40808	342	0	0
T7	43417	352	0	0
T8	49544	421	0	0
T9	13889	172	0	0
T10	84485	441	0	0
T11	10395	397	0	0
T12	2328	62	0	0
T13	31440	224	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	868421	0	0
T1	47470	2820	0	0
T2	333429	56	0	0
T3	40808	342	0	0
T7	43417	352	0	0
T8	49544	421	0	0
T9	13889	172	0	0
T10	84485	441	0	0
T11	10395	397	0	0
T12	2328	62	0	0
T13	31440	224	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	11651479	0	0
T1	47470	2011	0	0
T2	333429	243	0	0
T3	40808	2218	0	0
T7	43417	2609	0	0
T8	49544	2963	0	0
T9	13889	1315	0	0
T10	84485	3441	0	0
T11	10395	337	0	0
T12	2328	51	0	0
T13	31440	1747	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	868421	0	0
T1	47470	2820	0	0
T2	333429	56	0	0
T3	40808	342	0	0
T7	43417	352	0	0
T8	49544	421	0	0
T9	13889	172	0	0
T10	84485	441	0	0
T11	10395	397	0	0
T12	2328	62	0	0
T13	31440	224	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	868421	0	0
T1	47470	2820	0	0
T2	333429	56	0	0
T3	40808	342	0	0
T7	43417	352	0	0
T8	49544	421	0	0
T9	13889	172	0	0
T10	84485	441	0	0
T11	10395	397	0	0
T12	2328	62	0	0
T13	31440	224	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2372702	0	0
T1	47470	3631	0	0
T2	333429	58	0	0
T3	40808	501	0	0
T7	43417	501	0	0
T8	49544	606	0	0
T9	13889	305	0	0
T10	84485	525	0	0
T11	10395	458	0	0
T12	2328	74	0	0
T13	31440	342	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	868421	0	0
T1	47470	2820	0	0
T2	333429	56	0	0
T3	40808	342	0	0
T7	43417	352	0	0
T8	49544	421	0	0
T9	13889	172	0	0
T10	84485	441	0	0
T11	10395	397	0	0
T12	2328	62	0	0
T13	31440	224	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	231008	0	0
GntImpliesValid_A	427134500	231008	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	231008	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2958424	0	0
ReadyAndValidImplyGrant_A	427134500	231008	0	0
ReqAndReadyImplyGrant_A	427134500	231008	0	0
ReqImpliesValid_A	427134500	601787	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	231008	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	231008	0	0
T1	47470	737	0	0
T2	333429	14	0	0
T3	40808	67	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	11	0	0
T10	84485	88	0	0
T11	10395	93	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	231008	0	0
T1	47470	737	0	0
T2	333429	14	0	0
T3	40808	67	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	11	0	0
T10	84485	88	0	0
T11	10395	93	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	231008	0	0
T1	47470	737	0	0
T2	333429	14	0	0
T3	40808	67	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	11	0	0
T10	84485	88	0	0
T11	10395	93	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2958424	0	0
T1	47470	648	0	0
T2	333429	60	0	0
T3	40808	431	0	0
T7	43417	1	0	0
T8	49544	859	0	0
T9	13889	71	0	0
T10	84485	652	0	0
T11	10395	92	0	0
T12	2328	14	0	0
T13	31440	497	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	231008	0	0
T1	47470	737	0	0
T2	333429	14	0	0
T3	40808	67	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	11	0	0
T10	84485	88	0	0
T11	10395	93	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	231008	0	0
T1	47470	737	0	0
T2	333429	14	0	0
T3	40808	67	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	11	0	0
T10	84485	88	0	0
T11	10395	93	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	601787	0	0
T1	47470	828	0	0
T2	333429	14	0	0
T3	40808	79	0	0
T7	43417	0	0	0
T8	49544	113	0	0
T9	13889	11	0	0
T10	84485	88	0	0
T11	10395	95	0	0
T12	2328	13	0	0
T13	31440	68	0	0
T14	0	97	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	231008	0	0
T1	47470	737	0	0
T2	333429	14	0	0
T3	40808	67	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	11	0	0
T10	84485	88	0	0
T11	10395	93	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	211340	0	0
GntImpliesValid_A	427134500	211340	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	211340	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2893993	0	0
ReadyAndValidImplyGrant_A	427134500	211340	0	0
ReqAndReadyImplyGrant_A	427134500	211340	0	0
ReqImpliesValid_A	427134500	574904	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	211340	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211340	0	0
T1	47470	704	0	0
T2	333429	9	0	0
T3	40808	82	0	0
T7	43417	421	0	0
T8	49544	87	0	0
T9	13889	24	0	0
T10	84485	132	0	0
T11	10395	84	0	0
T12	2328	12	0	0
T13	31440	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211340	0	0
T1	47470	704	0	0
T2	333429	9	0	0
T3	40808	82	0	0
T7	43417	421	0	0
T8	49544	87	0	0
T9	13889	24	0	0
T10	84485	132	0	0
T11	10395	84	0	0
T12	2328	12	0	0
T13	31440	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211340	0	0
T1	47470	704	0	0
T2	333429	9	0	0
T3	40808	82	0	0
T7	43417	421	0	0
T8	49544	87	0	0
T9	13889	24	0	0
T10	84485	132	0	0
T11	10395	84	0	0
T12	2328	12	0	0
T13	31440	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2893993	0	0
T1	47470	228	0	0
T2	333429	46	0	0
T3	40808	587	0	0
T7	43417	826	0	0
T8	49544	658	0	0
T9	13889	173	0	0
T10	84485	1008	0	0
T11	10395	75	0	0
T12	2328	13	0	0
T13	31440	408	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211340	0	0
T1	47470	704	0	0
T2	333429	9	0	0
T3	40808	82	0	0
T7	43417	421	0	0
T8	49544	87	0	0
T9	13889	24	0	0
T10	84485	132	0	0
T11	10395	84	0	0
T12	2328	12	0	0
T13	31440	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211340	0	0
T1	47470	704	0	0
T2	333429	9	0	0
T3	40808	82	0	0
T7	43417	421	0	0
T8	49544	87	0	0
T9	13889	24	0	0
T10	84485	132	0	0
T11	10395	84	0	0
T12	2328	12	0	0
T13	31440	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	574904	0	0
T1	47470	1182	0	0
T2	333429	9	0	0
T3	40808	92	0	0
T7	43417	3914	0	0
T8	49544	112	0	0
T9	13889	27	0	0
T10	84485	133	0	0
T11	10395	94	0	0
T12	2328	12	0	0
T13	31440	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211340	0	0
T1	47470	704	0	0
T2	333429	9	0	0
T3	40808	82	0	0
T7	43417	421	0	0
T8	49544	87	0	0
T9	13889	24	0	0
T10	84485	132	0	0
T11	10395	84	0	0
T12	2328	12	0	0
T13	31440	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	213376	0	0
GntImpliesValid_A	427134500	213376	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	213376	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	5391319	0	0
ReadyAndValidImplyGrant_A	427134500	213376	0	0
ReqAndReadyImplyGrant_A	427134500	213376	0	0
ReqImpliesValid_A	427134500	1232824	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	213376	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213376	0	0
T1	47470	685	0	0
T2	333429	21	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	14	0	0
T10	84485	101	0	0
T11	10395	97	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213376	0	0
T1	47470	685	0	0
T2	333429	21	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	14	0	0
T10	84485	101	0	0
T11	10395	97	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213376	0	0
T1	47470	685	0	0
T2	333429	21	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	14	0	0
T10	84485	101	0	0
T11	10395	97	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	5391319	0	0
T1	47470	3159	0	0
T2	333429	159	0	0
T3	40808	831	0	0
T7	43417	0	0	0
T8	49544	1076	0	0
T9	13889	340	0	0
T10	84485	4800	0	0
T11	10395	1446	0	0
T12	2328	175	0	0
T13	31440	745	0	0
T14	0	646	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213376	0	0
T1	47470	685	0	0
T2	333429	21	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	14	0	0
T10	84485	101	0	0
T11	10395	97	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213376	0	0
T1	47470	685	0	0
T2	333429	21	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	14	0	0
T10	84485	101	0	0
T11	10395	97	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1232824	0	0
T1	47470	3445	0	0
T2	333429	29	0	0
T3	40808	107	0	0
T7	43417	0	0	0
T8	49544	120	0	0
T9	13889	26	0	0
T10	84485	252	0	0
T11	10395	246	0	0
T12	2328	39	0	0
T13	31440	126	0	0
T14	0	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213376	0	0
T1	47470	685	0	0
T2	333429	21	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	14	0	0
T10	84485	101	0	0
T11	10395	97	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	213916	0	0
GntImpliesValid_A	427134500	213916	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	213916	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	4637735	0	0
ReadyAndValidImplyGrant_A	427134500	213916	0	0
ReqAndReadyImplyGrant_A	427134500	213916	0	0
ReqImpliesValid_A	427134500	1148465	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	213916	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213916	0	0
T1	47470	721	0	0
T2	333429	15	0	0
T3	40808	73	0	0
T7	43417	503	0	0
T8	49544	113	0	0
T9	13889	23	0	0
T10	84485	117	0	0
T11	10395	102	0	0
T12	2328	17	0	0
T13	31440	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213916	0	0
T1	47470	721	0	0
T2	333429	15	0	0
T3	40808	73	0	0
T7	43417	503	0	0
T8	49544	113	0	0
T9	13889	23	0	0
T10	84485	117	0	0
T11	10395	102	0	0
T12	2328	17	0	0
T13	31440	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213916	0	0
T1	47470	721	0	0
T2	333429	15	0	0
T3	40808	73	0	0
T7	43417	503	0	0
T8	49544	113	0	0
T9	13889	23	0	0
T10	84485	117	0	0
T11	10395	102	0	0
T12	2328	17	0	0
T13	31440	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4637735	0	0
T1	47470	1349	0	0
T2	333429	117	0	0
T3	40808	744	0	0
T7	43417	1286	0	0
T8	49544	925	0	0
T9	13889	564	0	0
T10	84485	3585	0	0
T11	10395	485	0	0
T12	2328	138	0	0
T13	31440	478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213916	0	0
T1	47470	721	0	0
T2	333429	15	0	0
T3	40808	73	0	0
T7	43417	503	0	0
T8	49544	113	0	0
T9	13889	23	0	0
T10	84485	117	0	0
T11	10395	102	0	0
T12	2328	17	0	0
T13	31440	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213916	0	0
T1	47470	721	0	0
T2	333429	15	0	0
T3	40808	73	0	0
T7	43417	503	0	0
T8	49544	113	0	0
T9	13889	23	0	0
T10	84485	117	0	0
T11	10395	102	0	0
T12	2328	17	0	0
T13	31440	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1148465	0	0
T1	47470	3903	0	0
T2	333429	24	0	0
T3	40808	120	0	0
T7	43417	1546	0	0
T8	49544	122	0	0
T9	13889	49	0	0
T10	84485	117	0	0
T11	10395	160	0	0
T12	2328	37	0	0
T13	31440	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	213916	0	0
T1	47470	721	0	0
T2	333429	15	0	0
T3	40808	73	0	0
T7	43417	503	0	0
T8	49544	113	0	0
T9	13889	23	0	0
T10	84485	117	0	0
T11	10395	102	0	0
T12	2328	17	0	0
T13	31440	56	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	217636	0	0
GntImpliesValid_A	427134500	217636	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	217636	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	4920185	0	0
ReadyAndValidImplyGrant_A	427134500	217636	0	0
ReqAndReadyImplyGrant_A	427134500	217636	0	0
ReqImpliesValid_A	427134500	1227336	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	217636	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	217636	0	0
T1	47470	677	0	0
T2	333429	15	0	0
T3	40808	79	0	0
T7	43417	475	0	0
T8	49544	110	0	0
T9	13889	20	0	0
T10	84485	102	0	0
T11	10395	118	0	0
T12	2328	12	0	0
T13	31440	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	217636	0	0
T1	47470	677	0	0
T2	333429	15	0	0
T3	40808	79	0	0
T7	43417	475	0	0
T8	49544	110	0	0
T9	13889	20	0	0
T10	84485	102	0	0
T11	10395	118	0	0
T12	2328	12	0	0
T13	31440	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	217636	0	0
T1	47470	677	0	0
T2	333429	15	0	0
T3	40808	79	0	0
T7	43417	475	0	0
T8	49544	110	0	0
T9	13889	20	0	0
T10	84485	102	0	0
T11	10395	118	0	0
T12	2328	12	0	0
T13	31440	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4920185	0	0
T1	47470	3116	0	0
T2	333429	108	0	0
T3	40808	1286	0	0
T7	43417	1176	0	0
T8	49544	1445	0	0
T9	13889	365	0	0
T10	84485	1248	0	0
T11	10395	637	0	0
T12	2328	40	0	0
T13	31440	882	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	217636	0	0
T1	47470	677	0	0
T2	333429	15	0	0
T3	40808	79	0	0
T7	43417	475	0	0
T8	49544	110	0	0
T9	13889	20	0	0
T10	84485	102	0	0
T11	10395	118	0	0
T12	2328	12	0	0
T13	31440	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	217636	0	0
T1	47470	677	0	0
T2	333429	15	0	0
T3	40808	79	0	0
T7	43417	475	0	0
T8	49544	110	0	0
T9	13889	20	0	0
T10	84485	102	0	0
T11	10395	118	0	0
T12	2328	12	0	0
T13	31440	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1227336	0	0
T1	47470	2615	0	0
T2	333429	18	0	0
T3	40808	139	0	0
T7	43417	1609	0	0
T8	49544	145	0	0
T9	13889	20	0	0
T10	84485	102	0	0
T11	10395	185	0	0
T12	2328	19	0	0
T13	31440	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	217636	0	0
T1	47470	677	0	0
T2	333429	15	0	0
T3	40808	79	0	0
T7	43417	475	0	0
T8	49544	110	0	0
T9	13889	20	0	0
T10	84485	102	0	0
T11	10395	118	0	0
T12	2328	12	0	0
T13	31440	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	212371	0	0
GntImpliesValid_A	427134500	212371	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	212371	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	4409241	0	0
ReadyAndValidImplyGrant_A	427134500	212371	0	0
ReqAndReadyImplyGrant_A	427134500	212371	0	0
ReqImpliesValid_A	427134500	1081611	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	212371	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212371	0	0
T1	47470	226	0	0
T2	333429	9	0	0
T3	40808	73	0	0
T7	43417	450	0	0
T8	49544	97	0	0
T9	13889	12	0	0
T10	84485	108	0	0
T11	10395	105	0	0
T12	2328	14	0	0
T13	31440	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212371	0	0
T1	47470	226	0	0
T2	333429	9	0	0
T3	40808	73	0	0
T7	43417	450	0	0
T8	49544	97	0	0
T9	13889	12	0	0
T10	84485	108	0	0
T11	10395	105	0	0
T12	2328	14	0	0
T13	31440	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212371	0	0
T1	47470	226	0	0
T2	333429	9	0	0
T3	40808	73	0	0
T7	43417	450	0	0
T8	49544	97	0	0
T9	13889	12	0	0
T10	84485	108	0	0
T11	10395	105	0	0
T12	2328	14	0	0
T13	31440	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	4409241	0	0
T1	47470	2299	0	0
T2	333429	108	0	0
T3	40808	658	0	0
T7	43417	929	0	0
T8	49544	1908	0	0
T9	13889	135	0	0
T10	84485	6425	0	0
T11	10395	890	0	0
T12	2328	57	0	0
T13	31440	787	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212371	0	0
T1	47470	226	0	0
T2	333429	9	0	0
T3	40808	73	0	0
T7	43417	450	0	0
T8	49544	97	0	0
T9	13889	12	0	0
T10	84485	108	0	0
T11	10395	105	0	0
T12	2328	14	0	0
T13	31440	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212371	0	0
T1	47470	226	0	0
T2	333429	9	0	0
T3	40808	73	0	0
T7	43417	450	0	0
T8	49544	97	0	0
T9	13889	12	0	0
T10	84485	108	0	0
T11	10395	105	0	0
T12	2328	14	0	0
T13	31440	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	1081611	0	0
T1	47470	290	0	0
T2	333429	16	0	0
T3	40808	120	0	0
T7	43417	2721	0	0
T8	49544	181	0	0
T9	13889	12	0	0
T10	84485	161	0	0
T11	10395	220	0	0
T12	2328	27	0	0
T13	31440	77	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212371	0	0
T1	47470	226	0	0
T2	333429	9	0	0
T3	40808	73	0	0
T7	43417	450	0	0
T8	49544	97	0	0
T9	13889	12	0	0
T10	84485	108	0	0
T11	10395	105	0	0
T12	2328	14	0	0
T13	31440	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	215717	0	0
GntImpliesValid_A	427134500	215717	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	215717	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	3014509	0	0
ReadyAndValidImplyGrant_A	427134500	215717	0	0
ReqAndReadyImplyGrant_A	427134500	215717	0	0
ReqImpliesValid_A	427134500	588643	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	215717	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215717	0	0
T1	47470	231	0	0
T2	333429	13	0	0
T3	40808	83	0	0
T7	43417	453	0	0
T8	49544	115	0	0
T9	13889	31	0	0
T10	84485	126	0	0
T11	10395	102	0	0
T12	2328	22	0	0
T13	31440	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215717	0	0
T1	47470	231	0	0
T2	333429	13	0	0
T3	40808	83	0	0
T7	43417	453	0	0
T8	49544	115	0	0
T9	13889	31	0	0
T10	84485	126	0	0
T11	10395	102	0	0
T12	2328	22	0	0
T13	31440	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215717	0	0
T1	47470	231	0	0
T2	333429	13	0	0
T3	40808	83	0	0
T7	43417	453	0	0
T8	49544	115	0	0
T9	13889	31	0	0
T10	84485	126	0	0
T11	10395	102	0	0
T12	2328	22	0	0
T13	31440	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3014509	0	0
T1	47470	229	0	0
T2	333429	48	0	0
T3	40808	662	0	0
T7	43417	1050	0	0
T8	49544	875	0	0
T9	13889	208	0	0
T10	84485	1094	0	0
T11	10395	98	0	0
T12	2328	22	0	0
T13	31440	413	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215717	0	0
T1	47470	231	0	0
T2	333429	13	0	0
T3	40808	83	0	0
T7	43417	453	0	0
T8	49544	115	0	0
T9	13889	31	0	0
T10	84485	126	0	0
T11	10395	102	0	0
T12	2328	22	0	0
T13	31440	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215717	0	0
T1	47470	231	0	0
T2	333429	13	0	0
T3	40808	83	0	0
T7	43417	453	0	0
T8	49544	115	0	0
T9	13889	31	0	0
T10	84485	126	0	0
T11	10395	102	0	0
T12	2328	22	0	0
T13	31440	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	588643	0	0
T1	47470	235	0	0
T2	333429	21	0	0
T3	40808	95	0	0
T7	43417	4239	0	0
T8	49544	182	0	0
T9	13889	33	0	0
T10	84485	126	0	0
T11	10395	107	0	0
T12	2328	23	0	0
T13	31440	92	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215717	0	0
T1	47470	231	0	0
T2	333429	13	0	0
T3	40808	83	0	0
T7	43417	453	0	0
T8	49544	115	0	0
T9	13889	31	0	0
T10	84485	126	0	0
T11	10395	102	0	0
T12	2328	22	0	0
T13	31440	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	216258	0	0
GntImpliesValid_A	427134500	216258	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	216258	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	3036324	0	0
ReadyAndValidImplyGrant_A	427134500	216258	0	0
ReqAndReadyImplyGrant_A	427134500	216258	0	0
ReqImpliesValid_A	427134500	557276	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	216258	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216258	0	0
T1	47470	768	0	0
T2	333429	10	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	103	0	0
T9	13889	19	0	0
T10	84485	114	0	0
T11	10395	100	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216258	0	0
T1	47470	768	0	0
T2	333429	10	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	103	0	0
T9	13889	19	0	0
T10	84485	114	0	0
T11	10395	100	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216258	0	0
T1	47470	768	0	0
T2	333429	10	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	103	0	0
T9	13889	19	0	0
T10	84485	114	0	0
T11	10395	100	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3036324	0	0
T1	47470	616	0	0
T2	333429	39	0	0
T3	40808	608	0	0
T7	43417	1	0	0
T8	49544	698	0	0
T9	13889	150	0	0
T10	84485	827	0	0
T11	10395	100	0	0
T12	2328	13	0	0
T13	31440	399	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216258	0	0
T1	47470	768	0	0
T2	333429	10	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	103	0	0
T9	13889	19	0	0
T10	84485	114	0	0
T11	10395	100	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216258	0	0
T1	47470	768	0	0
T2	333429	10	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	103	0	0
T9	13889	19	0	0
T10	84485	114	0	0
T11	10395	100	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	557276	0	0
T1	47470	922	0	0
T2	333429	10	0	0
T3	40808	94	0	0
T7	43417	0	0	0
T8	49544	125	0	0
T9	13889	19	0	0
T10	84485	117	0	0
T11	10395	101	0	0
T12	2328	14	0	0
T13	31440	72	0	0
T14	0	123	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216258	0	0
T1	47470	768	0	0
T2	333429	10	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	103	0	0
T9	13889	19	0	0
T10	84485	114	0	0
T11	10395	100	0	0
T12	2328	13	0	0
T13	31440	59	0	0
T14	0	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	224964	0	0
GntImpliesValid_A	427134500	224964	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	224964	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2986706	0	0
ReadyAndValidImplyGrant_A	427134500	224964	0	0
ReqAndReadyImplyGrant_A	427134500	224964	0	0
ReqImpliesValid_A	427134500	569031	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	224964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224964	0	0
T1	47470	1349	0	0
T2	333429	14	0	0
T3	40808	75	0	0
T7	43417	0	0	0
T8	49544	95	0	0
T9	13889	13	0	0
T10	84485	109	0	0
T11	10395	96	0	0
T12	2328	11	0	0
T13	31440	54	0	0
T14	0	107	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224964	0	0
T1	47470	1349	0	0
T2	333429	14	0	0
T3	40808	75	0	0
T7	43417	0	0	0
T8	49544	95	0	0
T9	13889	13	0	0
T10	84485	109	0	0
T11	10395	96	0	0
T12	2328	11	0	0
T13	31440	54	0	0
T14	0	107	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224964	0	0
T1	47470	1349	0	0
T2	333429	14	0	0
T3	40808	75	0	0
T7	43417	0	0	0
T8	49544	95	0	0
T9	13889	13	0	0
T10	84485	109	0	0
T11	10395	96	0	0
T12	2328	11	0	0
T13	31440	54	0	0
T14	0	107	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2986706	0	0
T1	47470	650	0	0
T2	333429	63	0	0
T3	40808	626	0	0
T7	43417	1	0	0
T8	49544	701	0	0
T9	13889	150	0	0
T10	84485	836	0	0
T11	10395	96	0	0
T12	2328	12	0	0
T13	31440	419	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224964	0	0
T1	47470	1349	0	0
T2	333429	14	0	0
T3	40808	75	0	0
T7	43417	0	0	0
T8	49544	95	0	0
T9	13889	13	0	0
T10	84485	109	0	0
T11	10395	96	0	0
T12	2328	11	0	0
T13	31440	54	0	0
T14	0	107	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224964	0	0
T1	47470	1349	0	0
T2	333429	14	0	0
T3	40808	75	0	0
T7	43417	0	0	0
T8	49544	95	0	0
T9	13889	13	0	0
T10	84485	109	0	0
T11	10395	96	0	0
T12	2328	11	0	0
T13	31440	54	0	0
T14	0	107	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	569031	0	0
T1	47470	2050	0	0
T2	333429	14	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	122	0	0
T9	13889	13	0	0
T10	84485	109	0	0
T11	10395	97	0	0
T12	2328	11	0	0
T13	31440	54	0	0
T14	0	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224964	0	0
T1	47470	1349	0	0
T2	333429	14	0	0
T3	40808	75	0	0
T7	43417	0	0	0
T8	49544	95	0	0
T9	13889	13	0	0
T10	84485	109	0	0
T11	10395	96	0	0
T12	2328	11	0	0
T13	31440	54	0	0
T14	0	107	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	216709	0	0
GntImpliesValid_A	427134500	216709	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	216709	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2919095	0	0
ReadyAndValidImplyGrant_A	427134500	216709	0	0
ReqAndReadyImplyGrant_A	427134500	216709	0	0
ReqImpliesValid_A	427134500	603860	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	216709	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216709	0	0
T1	47470	254	0	0
T2	333429	11	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	80	0	0
T9	13889	24	0	0
T10	84485	88	0	0
T11	10395	124	0	0
T12	2328	12	0	0
T13	31440	47	0	0
T14	0	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216709	0	0
T1	47470	254	0	0
T2	333429	11	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	80	0	0
T9	13889	24	0	0
T10	84485	88	0	0
T11	10395	124	0	0
T12	2328	12	0	0
T13	31440	47	0	0
T14	0	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216709	0	0
T1	47470	254	0	0
T2	333429	11	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	80	0	0
T9	13889	24	0	0
T10	84485	88	0	0
T11	10395	124	0	0
T12	2328	12	0	0
T13	31440	47	0	0
T14	0	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2919095	0	0
T1	47470	254	0	0
T2	333429	45	0	0
T3	40808	644	0	0
T7	43417	1	0	0
T8	49544	575	0	0
T9	13889	212	0	0
T10	84485	694	0	0
T11	10395	116	0	0
T12	2328	11	0	0
T13	31440	345	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216709	0	0
T1	47470	254	0	0
T2	333429	11	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	80	0	0
T9	13889	24	0	0
T10	84485	88	0	0
T11	10395	124	0	0
T12	2328	12	0	0
T13	31440	47	0	0
T14	0	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216709	0	0
T1	47470	254	0	0
T2	333429	11	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	80	0	0
T9	13889	24	0	0
T10	84485	88	0	0
T11	10395	124	0	0
T12	2328	12	0	0
T13	31440	47	0	0
T14	0	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	603860	0	0
T1	47470	256	0	0
T2	333429	18	0	0
T3	40808	114	0	0
T7	43417	0	0	0
T8	49544	90	0	0
T9	13889	42	0	0
T10	84485	92	0	0
T11	10395	133	0	0
T12	2328	14	0	0
T13	31440	72	0	0
T14	0	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216709	0	0
T1	47470	254	0	0
T2	333429	11	0	0
T3	40808	88	0	0
T7	43417	0	0	0
T8	49544	80	0	0
T9	13889	24	0	0
T10	84485	88	0	0
T11	10395	124	0	0
T12	2328	12	0	0
T13	31440	47	0	0
T14	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	200105	0	0
GntImpliesValid_A	427134500	200105	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	200105	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2983937	0	0
ReadyAndValidImplyGrant_A	427134500	200105	0	0
ReqAndReadyImplyGrant_A	427134500	200105	0	0
ReqImpliesValid_A	427134500	532414	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	200105	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	200105	0	0
T1	47470	232	0	0
T2	333429	14	0	0
T3	40808	81	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	53	0	0
T10	84485	120	0	0
T11	10395	109	0	0
T12	2328	17	0	0
T13	31440	57	0	0
T14	0	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	200105	0	0
T1	47470	232	0	0
T2	333429	14	0	0
T3	40808	81	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	53	0	0
T10	84485	120	0	0
T11	10395	109	0	0
T12	2328	17	0	0
T13	31440	57	0	0
T14	0	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	200105	0	0
T1	47470	232	0	0
T2	333429	14	0	0
T3	40808	81	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	53	0	0
T10	84485	120	0	0
T11	10395	109	0	0
T12	2328	17	0	0
T13	31440	57	0	0
T14	0	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2983937	0	0
T1	47470	232	0	0
T2	333429	76	0	0
T3	40808	527	0	0
T7	43417	1	0	0
T8	49544	808	0	0
T9	13889	393	0	0
T10	84485	908	0	0
T11	10395	104	0	0
T12	2328	18	0	0
T13	31440	441	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	200105	0	0
T1	47470	232	0	0
T2	333429	14	0	0
T3	40808	81	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	53	0	0
T10	84485	120	0	0
T11	10395	109	0	0
T12	2328	17	0	0
T13	31440	57	0	0
T14	0	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	200105	0	0
T1	47470	232	0	0
T2	333429	14	0	0
T3	40808	81	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	53	0	0
T10	84485	120	0	0
T11	10395	109	0	0
T12	2328	17	0	0
T13	31440	57	0	0
T14	0	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	532414	0	0
T1	47470	234	0	0
T2	333429	14	0	0
T3	40808	102	0	0
T7	43417	0	0	0
T8	49544	131	0	0
T9	13889	74	0	0
T10	84485	121	0	0
T11	10395	115	0	0
T12	2328	17	0	0
T13	31440	62	0	0
T14	0	122	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	200105	0	0
T1	47470	232	0	0
T2	333429	14	0	0
T3	40808	81	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	53	0	0
T10	84485	120	0	0
T11	10395	109	0	0
T12	2328	17	0	0
T13	31440	57	0	0
T14	0	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	211033	0	0
GntImpliesValid_A	427134500	211033	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	211033	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2966594	0	0
ReadyAndValidImplyGrant_A	427134500	211033	0	0
ReqAndReadyImplyGrant_A	427134500	211033	0	0
ReqImpliesValid_A	427134500	540327	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	211033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211033	0	0
T1	47470	755	0	0
T2	333429	6	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	97	0	0
T9	13889	16	0	0
T10	84485	119	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	54	0	0
T14	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211033	0	0
T1	47470	755	0	0
T2	333429	6	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	97	0	0
T9	13889	16	0	0
T10	84485	119	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	54	0	0
T14	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211033	0	0
T1	47470	755	0	0
T2	333429	6	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	97	0	0
T9	13889	16	0	0
T10	84485	119	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	54	0	0
T14	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2966594	0	0
T1	47470	566	0	0
T2	333429	16	0	0
T3	40808	562	0	0
T7	43417	1	0	0
T8	49544	773	0	0
T9	13889	145	0	0
T10	84485	880	0	0
T11	10395	107	0	0
T12	2328	17	0	0
T13	31440	412	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211033	0	0
T1	47470	755	0	0
T2	333429	6	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	97	0	0
T9	13889	16	0	0
T10	84485	119	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	54	0	0
T14	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211033	0	0
T1	47470	755	0	0
T2	333429	6	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	97	0	0
T9	13889	16	0	0
T10	84485	119	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	54	0	0
T14	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	540327	0	0
T1	47470	946	0	0
T2	333429	6	0	0
T3	40808	83	0	0
T7	43417	0	0	0
T8	49544	116	0	0
T9	13889	32	0	0
T10	84485	146	0	0
T11	10395	106	0	0
T12	2328	18	0	0
T13	31440	72	0	0
T14	0	124	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	211033	0	0
T1	47470	755	0	0
T2	333429	6	0	0
T3	40808	80	0	0
T7	43417	0	0	0
T8	49544	97	0	0
T9	13889	16	0	0
T10	84485	119	0	0
T11	10395	106	0	0
T12	2328	17	0	0
T13	31440	54	0	0
T14	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	224318	0	0
GntImpliesValid_A	427134500	224318	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	224318	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2974400	0	0
ReadyAndValidImplyGrant_A	427134500	224318	0	0
ReqAndReadyImplyGrant_A	427134500	224318	0	0
ReqImpliesValid_A	427134500	584798	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	224318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224318	0	0
T1	47470	746	0	0
T2	333429	11	0	0
T3	40808	87	0	0
T7	43417	0	0	0
T8	49544	111	0	0
T9	13889	29	0	0
T10	84485	129	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	51	0	0
T14	0	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224318	0	0
T1	47470	746	0	0
T2	333429	11	0	0
T3	40808	87	0	0
T7	43417	0	0	0
T8	49544	111	0	0
T9	13889	29	0	0
T10	84485	129	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	51	0	0
T14	0	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224318	0	0
T1	47470	746	0	0
T2	333429	11	0	0
T3	40808	87	0	0
T7	43417	0	0	0
T8	49544	111	0	0
T9	13889	29	0	0
T10	84485	129	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	51	0	0
T14	0	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2974400	0	0
T1	47470	494	0	0
T2	333429	33	0	0
T3	40808	688	0	0
T7	43417	1	0	0
T8	49544	845	0	0
T9	13889	229	0	0
T10	84485	1045	0	0
T11	10395	117	0	0
T12	2328	12	0	0
T13	31440	376	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224318	0	0
T1	47470	746	0	0
T2	333429	11	0	0
T3	40808	87	0	0
T7	43417	0	0	0
T8	49544	111	0	0
T9	13889	29	0	0
T10	84485	129	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	51	0	0
T14	0	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224318	0	0
T1	47470	746	0	0
T2	333429	11	0	0
T3	40808	87	0	0
T7	43417	0	0	0
T8	49544	111	0	0
T9	13889	29	0	0
T10	84485	129	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	51	0	0
T14	0	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	584798	0	0
T1	47470	1000	0	0
T2	333429	11	0	0
T3	40808	107	0	0
T7	43417	0	0	0
T8	49544	152	0	0
T9	13889	49	0	0
T10	84485	129	0	0
T11	10395	132	0	0
T12	2328	11	0	0
T13	31440	72	0	0
T14	0	133	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	224318	0	0
T1	47470	746	0	0
T2	333429	11	0	0
T3	40808	87	0	0
T7	43417	0	0	0
T8	49544	111	0	0
T9	13889	29	0	0
T10	84485	129	0	0
T11	10395	124	0	0
T12	2328	11	0	0
T13	31440	51	0	0
T14	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	223454	0	0
GntImpliesValid_A	427134500	223454	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	223454	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	3036835	0	0
ReadyAndValidImplyGrant_A	427134500	223454	0	0
ReqAndReadyImplyGrant_A	427134500	223454	0	0
ReqImpliesValid_A	427134500	624853	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	223454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	223454	0	0
T1	47470	243	0	0
T2	333429	7	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	107	0	0
T9	13889	21	0	0
T10	84485	102	0	0
T11	10395	99	0	0
T12	2328	9	0	0
T13	31440	49	0	0
T14	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	223454	0	0
T1	47470	243	0	0
T2	333429	7	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	107	0	0
T9	13889	21	0	0
T10	84485	102	0	0
T11	10395	99	0	0
T12	2328	9	0	0
T13	31440	49	0	0
T14	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	223454	0	0
T1	47470	243	0	0
T2	333429	7	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	107	0	0
T9	13889	21	0	0
T10	84485	102	0	0
T11	10395	99	0	0
T12	2328	9	0	0
T13	31440	49	0	0
T14	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3036835	0	0
T1	47470	242	0	0
T2	333429	38	0	0
T3	40808	610	0	0
T7	43417	1	0	0
T8	49544	872	0	0
T9	13889	153	0	0
T10	84485	803	0	0
T11	10395	94	0	0
T12	2328	9	0	0
T13	31440	375	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	223454	0	0
T1	47470	243	0	0
T2	333429	7	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	107	0	0
T9	13889	21	0	0
T10	84485	102	0	0
T11	10395	99	0	0
T12	2328	9	0	0
T13	31440	49	0	0
T14	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	223454	0	0
T1	47470	243	0	0
T2	333429	7	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	107	0	0
T9	13889	21	0	0
T10	84485	102	0	0
T11	10395	99	0	0
T12	2328	9	0	0
T13	31440	49	0	0
T14	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	624853	0	0
T1	47470	246	0	0
T2	333429	9	0	0
T3	40808	78	0	0
T7	43417	0	0	0
T8	49544	153	0	0
T9	13889	21	0	0
T10	84485	102	0	0
T11	10395	105	0	0
T12	2328	10	0	0
T13	31440	67	0	0
T14	0	125	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	223454	0	0
T1	47470	243	0	0
T2	333429	7	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	107	0	0
T9	13889	21	0	0
T10	84485	102	0	0
T11	10395	99	0	0
T12	2328	9	0	0
T13	31440	49	0	0
T14	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	229827	0	0
GntImpliesValid_A	427134500	229827	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	229827	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	3018628	0	0
ReadyAndValidImplyGrant_A	427134500	229827	0	0
ReqAndReadyImplyGrant_A	427134500	229827	0	0
ReqImpliesValid_A	427134500	604922	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	229827	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	229827	0	0
T1	47470	852	0	0
T2	333429	14	0	0
T3	40808	147	0	0
T7	43417	0	0	0
T8	49544	177	0	0
T9	13889	178	0	0
T10	84485	126	0	0
T11	10395	179	0	0
T12	2328	12	0	0
T13	31440	86	0	0
T14	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	229827	0	0
T1	47470	852	0	0
T2	333429	14	0	0
T3	40808	147	0	0
T7	43417	0	0	0
T8	49544	177	0	0
T9	13889	178	0	0
T10	84485	126	0	0
T11	10395	179	0	0
T12	2328	12	0	0
T13	31440	86	0	0
T14	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	229827	0	0
T1	47470	852	0	0
T2	333429	14	0	0
T3	40808	147	0	0
T7	43417	0	0	0
T8	49544	177	0	0
T9	13889	178	0	0
T10	84485	126	0	0
T11	10395	179	0	0
T12	2328	12	0	0
T13	31440	86	0	0
T14	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	3018628	0	0
T1	47470	312	0	0
T2	333429	81	0	0
T3	40808	1085	0	0
T7	43417	1	0	0
T8	49544	1301	0	0
T9	13889	1108	0	0
T10	84485	967	0	0
T11	10395	174	0	0
T12	2328	13	0	0
T13	31440	675	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	229827	0	0
T1	47470	852	0	0
T2	333429	14	0	0
T3	40808	147	0	0
T7	43417	0	0	0
T8	49544	177	0	0
T9	13889	178	0	0
T10	84485	126	0	0
T11	10395	179	0	0
T12	2328	12	0	0
T13	31440	86	0	0
T14	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	229827	0	0
T1	47470	852	0	0
T2	333429	14	0	0
T3	40808	147	0	0
T7	43417	0	0	0
T8	49544	177	0	0
T9	13889	178	0	0
T10	84485	126	0	0
T11	10395	179	0	0
T12	2328	12	0	0
T13	31440	86	0	0
T14	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	604922	0	0
T1	47470	1394	0	0
T2	333429	21	0	0
T3	40808	235	0	0
T7	43417	0	0	0
T8	49544	203	0	0
T9	13889	579	0	0
T10	84485	126	0	0
T11	10395	185	0	0
T12	2328	12	0	0
T13	31440	100	0	0
T14	0	119	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	229827	0	0
T1	47470	852	0	0
T2	333429	14	0	0
T3	40808	147	0	0
T7	43417	0	0	0
T8	49544	177	0	0
T9	13889	178	0	0
T10	84485	126	0	0
T11	10395	179	0	0
T12	2328	12	0	0
T13	31440	86	0	0
T14	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	220358	0	0
GntImpliesValid_A	427134500	220358	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	220358	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2966133	0	0
ReadyAndValidImplyGrant_A	427134500	220358	0	0
ReqAndReadyImplyGrant_A	427134500	220358	0	0
ReqImpliesValid_A	427134500	585361	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	220358	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	220358	0	0
T1	47470	272	0	0
T2	333429	7	0	0
T3	40808	73	0	0
T7	43417	0	0	0
T8	49544	91	0	0
T9	13889	11	0	0
T10	84485	116	0	0
T11	10395	95	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	109	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	220358	0	0
T1	47470	272	0	0
T2	333429	7	0	0
T3	40808	73	0	0
T7	43417	0	0	0
T8	49544	91	0	0
T9	13889	11	0	0
T10	84485	116	0	0
T11	10395	95	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	109	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	220358	0	0
T1	47470	272	0	0
T2	333429	7	0	0
T3	40808	73	0	0
T7	43417	0	0	0
T8	49544	91	0	0
T9	13889	11	0	0
T10	84485	116	0	0
T11	10395	95	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	109	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2966133	0	0
T1	47470	272	0	0
T2	333429	33	0	0
T3	40808	555	0	0
T7	43417	1	0	0
T8	49544	735	0	0
T9	13889	84	0	0
T10	84485	955	0	0
T11	10395	92	0	0
T12	2328	17	0	0
T13	31440	414	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	220358	0	0
T1	47470	272	0	0
T2	333429	7	0	0
T3	40808	73	0	0
T7	43417	0	0	0
T8	49544	91	0	0
T9	13889	11	0	0
T10	84485	116	0	0
T11	10395	95	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	109	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	220358	0	0
T1	47470	272	0	0
T2	333429	7	0	0
T3	40808	73	0	0
T7	43417	0	0	0
T8	49544	91	0	0
T9	13889	11	0	0
T10	84485	116	0	0
T11	10395	95	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	109	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	585361	0	0
T1	47470	274	0	0
T2	333429	10	0	0
T3	40808	114	0	0
T7	43417	0	0	0
T8	49544	108	0	0
T9	13889	11	0	0
T10	84485	127	0	0
T11	10395	99	0	0
T12	2328	16	0	0
T13	31440	61	0	0
T14	0	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	220358	0	0
T1	47470	272	0	0
T2	333429	7	0	0
T3	40808	73	0	0
T7	43417	0	0	0
T8	49544	91	0	0
T9	13889	11	0	0
T10	84485	116	0	0
T11	10395	95	0	0
T12	2328	16	0	0
T13	31440	58	0	0
T14	0	109	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	238595	0	0
GntImpliesValid_A	427134500	238595	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	238595	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2934275	0	0
ReadyAndValidImplyGrant_A	427134500	238595	0	0
ReqAndReadyImplyGrant_A	427134500	238595	0	0
ReqImpliesValid_A	427134500	671983	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	238595	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	238595	0	0
T1	47470	747	0	0
T2	333429	7	0	0
T3	40808	98	0	0
T7	43417	516	0	0
T8	49544	71	0	0
T9	13889	16	0	0
T10	84485	100	0	0
T11	10395	112	0	0
T12	2328	17	0	0
T13	31440	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	238595	0	0
T1	47470	747	0	0
T2	333429	7	0	0
T3	40808	98	0	0
T7	43417	516	0	0
T8	49544	71	0	0
T9	13889	16	0	0
T10	84485	100	0	0
T11	10395	112	0	0
T12	2328	17	0	0
T13	31440	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	238595	0	0
T1	47470	747	0	0
T2	333429	7	0	0
T3	40808	98	0	0
T7	43417	516	0	0
T8	49544	71	0	0
T9	13889	16	0	0
T10	84485	100	0	0
T11	10395	112	0	0
T12	2328	17	0	0
T13	31440	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2934275	0	0
T1	47470	233	0	0
T2	333429	44	0	0
T3	40808	770	0	0
T7	43417	828	0	0
T8	49544	512	0	0
T9	13889	109	0	0
T10	84485	761	0	0
T11	10395	108	0	0
T12	2328	18	0	0
T13	31440	440	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	238595	0	0
T1	47470	747	0	0
T2	333429	7	0	0
T3	40808	98	0	0
T7	43417	516	0	0
T8	49544	71	0	0
T9	13889	16	0	0
T10	84485	100	0	0
T11	10395	112	0	0
T12	2328	17	0	0
T13	31440	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	238595	0	0
T1	47470	747	0	0
T2	333429	7	0	0
T3	40808	98	0	0
T7	43417	516	0	0
T8	49544	71	0	0
T9	13889	16	0	0
T10	84485	100	0	0
T11	10395	112	0	0
T12	2328	17	0	0
T13	31440	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	671983	0	0
T1	47470	1263	0	0
T2	333429	7	0	0
T3	40808	132	0	0
T7	43417	4950	0	0
T8	49544	109	0	0
T9	13889	16	0	0
T10	84485	102	0	0
T11	10395	117	0	0
T12	2328	17	0	0
T13	31440	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	238595	0	0
T1	47470	747	0	0
T2	333429	7	0	0
T3	40808	98	0	0
T7	43417	516	0	0
T8	49544	71	0	0
T9	13889	16	0	0
T10	84485	100	0	0
T11	10395	112	0	0
T12	2328	17	0	0
T13	31440	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	216023	0	0
GntImpliesValid_A	427134500	216023	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	216023	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2933315	0	0
ReadyAndValidImplyGrant_A	427134500	216023	0	0
ReqAndReadyImplyGrant_A	427134500	216023	0	0
ReqImpliesValid_A	427134500	575843	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	216023	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216023	0	0
T1	47470	1118	0	0
T2	333429	16	0	0
T3	40808	72	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	308	0	0
T10	84485	110	0	0
T11	10395	111	0	0
T12	2328	6	0	0
T13	31440	59	0	0
T14	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216023	0	0
T1	47470	1118	0	0
T2	333429	16	0	0
T3	40808	72	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	308	0	0
T10	84485	110	0	0
T11	10395	111	0	0
T12	2328	6	0	0
T13	31440	59	0	0
T14	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216023	0	0
T1	47470	1118	0	0
T2	333429	16	0	0
T3	40808	72	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	308	0	0
T10	84485	110	0	0
T11	10395	111	0	0
T12	2328	6	0	0
T13	31440	59	0	0
T14	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2933315	0	0
T1	47470	777	0	0
T2	333429	80	0	0
T3	40808	562	0	0
T7	43417	1	0	0
T8	49544	857	0	0
T9	13889	267	0	0
T10	84485	888	0	0
T11	10395	109	0	0
T12	2328	7	0	0
T13	31440	386	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216023	0	0
T1	47470	1118	0	0
T2	333429	16	0	0
T3	40808	72	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	308	0	0
T10	84485	110	0	0
T11	10395	111	0	0
T12	2328	6	0	0
T13	31440	59	0	0
T14	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216023	0	0
T1	47470	1118	0	0
T2	333429	16	0	0
T3	40808	72	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	308	0	0
T10	84485	110	0	0
T11	10395	111	0	0
T12	2328	6	0	0
T13	31440	59	0	0
T14	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	575843	0	0
T1	47470	1461	0	0
T2	333429	23	0	0
T3	40808	78	0	0
T7	43417	0	0	0
T8	49544	126	0	0
T9	13889	3262	0	0
T10	84485	110	0	0
T11	10395	114	0	0
T12	2328	6	0	0
T13	31440	93	0	0
T14	0	117	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	216023	0	0
T1	47470	1118	0	0
T2	333429	16	0	0
T3	40808	72	0	0
T7	43417	0	0	0
T8	49544	112	0	0
T9	13889	308	0	0
T10	84485	110	0	0
T11	10395	111	0	0
T12	2328	6	0	0
T13	31440	59	0	0
T14	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	212663	0	0
GntImpliesValid_A	427134500	212663	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	212663	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2958721	0	0
ReadyAndValidImplyGrant_A	427134500	212663	0	0
ReqAndReadyImplyGrant_A	427134500	212663	0	0
ReqImpliesValid_A	427134500	557047	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	212663	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212663	0	0
T1	47470	1221	0	0
T2	333429	7	0	0
T3	40808	70	0	0
T7	43417	0	0	0
T8	49544	94	0	0
T9	13889	11	0	0
T10	84485	119	0	0
T11	10395	112	0	0
T12	2328	11	0	0
T13	31440	52	0	0
T14	0	104	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212663	0	0
T1	47470	1221	0	0
T2	333429	7	0	0
T3	40808	70	0	0
T7	43417	0	0	0
T8	49544	94	0	0
T9	13889	11	0	0
T10	84485	119	0	0
T11	10395	112	0	0
T12	2328	11	0	0
T13	31440	52	0	0
T14	0	104	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212663	0	0
T1	47470	1221	0	0
T2	333429	7	0	0
T3	40808	70	0	0
T7	43417	0	0	0
T8	49544	94	0	0
T9	13889	11	0	0
T10	84485	119	0	0
T11	10395	112	0	0
T12	2328	11	0	0
T13	31440	52	0	0
T14	0	104	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2958721	0	0
T1	47470	224	0	0
T2	333429	35	0	0
T3	40808	506	0	0
T7	43417	1	0	0
T8	49544	703	0	0
T9	13889	80	0	0
T10	84485	911	0	0
T11	10395	107	0	0
T12	2328	12	0	0
T13	31440	410	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212663	0	0
T1	47470	1221	0	0
T2	333429	7	0	0
T3	40808	70	0	0
T7	43417	0	0	0
T8	49544	94	0	0
T9	13889	11	0	0
T10	84485	119	0	0
T11	10395	112	0	0
T12	2328	11	0	0
T13	31440	52	0	0
T14	0	104	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212663	0	0
T1	47470	1221	0	0
T2	333429	7	0	0
T3	40808	70	0	0
T7	43417	0	0	0
T8	49544	94	0	0
T9	13889	11	0	0
T10	84485	119	0	0
T11	10395	112	0	0
T12	2328	11	0	0
T13	31440	52	0	0
T14	0	104	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	557047	0	0
T1	47470	2220	0	0
T2	333429	7	0	0
T3	40808	95	0	0
T7	43417	0	0	0
T8	49544	96	0	0
T9	13889	16	0	0
T10	84485	133	0	0
T11	10395	118	0	0
T12	2328	11	0	0
T13	31440	58	0	0
T14	0	107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	212663	0	0
T1	47470	1221	0	0
T2	333429	7	0	0
T3	40808	70	0	0
T7	43417	0	0	0
T8	49544	94	0	0
T9	13889	11	0	0
T10	84485	119	0	0
T11	10395	112	0	0
T12	2328	11	0	0
T13	31440	52	0	0
T14	0	104	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	215664	0	0
GntImpliesValid_A	427134500	215664	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	215664	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	2967216	0	0
ReadyAndValidImplyGrant_A	427134500	215664	0	0
ReqAndReadyImplyGrant_A	427134500	215664	0	0
ReqImpliesValid_A	427134500	557931	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	0	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	215664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215664	0	0
T1	47470	1258	0	0
T2	333429	14	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	17	0	0
T10	84485	116	0	0
T11	10395	109	0	0
T12	2328	16	0	0
T13	31440	67	0	0
T14	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215664	0	0
T1	47470	1258	0	0
T2	333429	14	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	17	0	0
T10	84485	116	0	0
T11	10395	109	0	0
T12	2328	16	0	0
T13	31440	67	0	0
T14	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215664	0	0
T1	47470	1258	0	0
T2	333429	14	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	17	0	0
T10	84485	116	0	0
T11	10395	109	0	0
T12	2328	16	0	0
T13	31440	67	0	0
T14	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2967216	0	0
T1	47470	508	0	0
T2	333429	59	0	0
T3	40808	566	0	0
T7	43417	1	0	0
T8	49544	778	0	0
T9	13889	118	0	0
T10	84485	822	0	0
T11	10395	109	0	0
T12	2328	16	0	0
T13	31440	454	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215664	0	0
T1	47470	1258	0	0
T2	333429	14	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	17	0	0
T10	84485	116	0	0
T11	10395	109	0	0
T12	2328	16	0	0
T13	31440	67	0	0
T14	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215664	0	0
T1	47470	1258	0	0
T2	333429	14	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	17	0	0
T10	84485	116	0	0
T11	10395	109	0	0
T12	2328	16	0	0
T13	31440	67	0	0
T14	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	557931	0	0
T1	47470	2010	0	0
T2	333429	14	0	0
T3	40808	97	0	0
T7	43417	0	0	0
T8	49544	128	0	0
T9	13889	17	0	0
T10	84485	119	0	0
T11	10395	110	0	0
T12	2328	17	0	0
T13	31440	109	0	0
T14	0	117	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	215664	0	0
T1	47470	1258	0	0
T2	333429	14	0	0
T3	40808	77	0	0
T7	43417	0	0	0
T8	49544	104	0	0
T9	13889	17	0	0
T10	84485	116	0	0
T11	10395	109	0	0
T12	2328	16	0	0
T13	31440	67	0	0
T14	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	877796	0	0
GntImpliesValid_A	427134500	877796	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	877796	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	11345975	0	0
ReadyAndValidImplyGrant_A	427134500	877796	0	0
ReqAndReadyImplyGrant_A	427134500	877796	0	0
ReqImpliesValid_A	427134500	2279853	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	15230	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	877796	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	877796	0	0
T1	47470	2040	0	0
T2	333429	55	0	0
T3	40808	324	0	0
T7	43417	1158	0	0
T8	49544	418	0	0
T9	13889	157	0	0
T10	84485	485	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	877796	0	0
T1	47470	2040	0	0
T2	333429	55	0	0
T3	40808	324	0	0
T7	43417	1158	0	0
T8	49544	418	0	0
T9	13889	157	0	0
T10	84485	485	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	877796	0	0
T1	47470	2040	0	0
T2	333429	55	0	0
T3	40808	324	0	0
T7	43417	1158	0	0
T8	49544	418	0	0
T9	13889	157	0	0
T10	84485	485	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	11345975	0	0
T1	47470	2	0	0
T2	333429	157	0	0
T3	40808	2090	0	0
T7	43417	3422	0	0
T8	49544	2605	0	0
T9	13889	1100	0	0
T10	84485	3115	0	0
T11	10395	1	0	0
T12	2328	1	0	0
T13	31440	1496	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	877796	0	0
T1	47470	2040	0	0
T2	333429	55	0	0
T3	40808	324	0	0
T7	43417	1158	0	0
T8	49544	418	0	0
T9	13889	157	0	0
T10	84485	485	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	877796	0	0
T1	47470	2040	0	0
T2	333429	55	0	0
T3	40808	324	0	0
T7	43417	1158	0	0
T8	49544	418	0	0
T9	13889	157	0	0
T10	84485	485	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	2279853	0	0
T1	47470	2040	0	0
T2	333429	63	0	0
T3	40808	525	0	0
T7	43417	8413	0	0
T8	49544	594	0	0
T9	13889	193	0	0
T10	84485	546	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	261	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	15230	0	900
T1	47470	13	0	1
T2	333429	0	0	1
T3	40808	0	0	1
T7	43417	17	0	1
T8	49544	0	0	1
T9	13889	0	0	1
T10	84485	0	0	1
T11	10395	3	0	1
T12	2328	0	0	1
T13	31440	0	0	1
T15	0	1	0	0
T16	0	1	0	0
T18	0	6	0	0
T19	0	10	0	0
T20	0	7	0	0
T21	0	9	0	0
T22	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	877796	0	0
T1	47470	2040	0	0
T2	333429	55	0	0
T3	40808	324	0	0
T7	43417	1158	0	0
T8	49544	418	0	0
T9	13889	157	0	0
T10	84485	485	0	0
T11	10395	407	0	0
T12	2328	50	0	0
T13	31440	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427134500	427009449	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427134500	857086	0	0
GntImpliesValid_A	427134500	857086	0	0
GrantKnown_A	427134500	427009449	0	0
IdxKnown_A	427134500	427009449	0	0
IndexIsCorrect_A	427134500	857086	0	0
LockArbDecision_A	427134500	0	0	0
NoReadyValidNoGrant_A	427134500	358357014	0	0
ReadyAndValidImplyGrant_A	427134500	857086	0	0
ReqAndReadyImplyGrant_A	427134500	857086	0	0
ReqImpliesValid_A	427134500	13252049	0	0
ReqStaysHighUntilGranted0_M	427134500	0	0	0
RoundRobin_A	427134500	22279	0	900
ValidKnown_A	427134500	427009449	0	0
gen_data_port_assertion.DataFlow_A	427134500	857086	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	857086	0	0
T1	47470	3530	0	0
T2	333429	53	0	0
T3	40808	312	0	0
T7	43417	350	0	0
T8	49544	389	0	0
T9	13889	151	0	0
T10	84485	479	0	0
T11	10395	420	0	0
T12	2328	36	0	0
T13	31440	198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	857086	0	0
T1	47470	3530	0	0
T2	333429	53	0	0
T3	40808	312	0	0
T7	43417	350	0	0
T8	49544	389	0	0
T9	13889	151	0	0
T10	84485	479	0	0
T11	10395	420	0	0
T12	2328	36	0	0
T13	31440	198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	857086	0	0
T1	47470	3530	0	0
T2	333429	53	0	0
T3	40808	312	0	0
T7	43417	350	0	0
T8	49544	389	0	0
T9	13889	151	0	0
T10	84485	479	0	0
T11	10395	420	0	0
T12	2328	36	0	0
T13	31440	198	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	358357014	0	0
T1	47470	1	0	0
T2	333429	277598	0	0
T3	40808	34155	0	0
T7	43417	36956	0	0
T8	49544	42210	0	0
T9	13889	11164	0	0
T10	84485	72167	0	0
T11	10395	1	0	0
T12	2328	1	0	0
T13	31440	26650	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	857086	0	0
T1	47470	3530	0	0
T2	333429	53	0	0
T3	40808	312	0	0
T7	43417	350	0	0
T8	49544	389	0	0
T9	13889	151	0	0
T10	84485	479	0	0
T11	10395	420	0	0
T12	2328	36	0	0
T13	31440	198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	857086	0	0
T1	47470	3530	0	0
T2	333429	53	0	0
T3	40808	312	0	0
T7	43417	350	0	0
T8	49544	389	0	0
T9	13889	151	0	0
T10	84485	479	0	0
T11	10395	420	0	0
T12	2328	36	0	0
T13	31440	198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	13252049	0	0
T1	47470	3530	0	0
T2	333429	216	0	0
T3	40808	2285	0	0
T7	43417	2851	0	0
T8	49544	3188	0	0
T9	13889	1154	0	0
T10	84485	3622	0	0
T11	10395	420	0	0
T12	2328	36	0	0
T13	31440	1538	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	22279	0	900
T1	47470	669	0	1
T2	333429	0	0	1
T3	40808	0	0	1
T7	43417	0	0	1
T8	49544	0	0	1
T9	13889	0	0	1
T10	84485	0	0	1
T11	10395	3	0	1
T12	2328	0	0	1
T13	31440	0	0	1
T14	0	7	0	0
T16	0	2	0	0
T17	0	3	0	0
T18	0	6	0	0
T19	0	11	0	0
T20	0	4	0	0
T22	0	3	0	0
T23	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	427009449	0	0
T1	47470	47331	0	0
T2	333429	333388	0	0
T3	40808	40778	0	0
T7	43417	43409	0	0
T8	49544	49504	0	0
T9	13889	13375	0	0
T10	84485	84406	0	0
T11	10395	10328	0	0
T12	2328	2289	0	0
T13	31440	31389	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427134500	857086	0	0
T1	47470	3530	0	0
T2	333429	53	0	0
T3	40808	312	0	0
T7	43417	350	0	0
T8	49544	389	0	0
T9	13889	151	0	0
T10	84485	479	0	0
T11	10395	420	0	0
T12	2328	36	0	0
T13	31440	198	0	0