Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1570301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249398

1

T1

543

T2

122

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	618579	1			T1	1275		T2	272		T3	77
values[0x0]	583284	1			T1	1270		T2	306		T3	8
values[0x1]	617836	1			T1	1400		T2	306		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1213861	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

605838

1

T1

1325

T2

297

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28610	1			T1	66		T2	17		T9	15
valid_sources[0x01]	26816	1			T1	62		T2	13		T3	1
valid_sources[0x02]	28803	1			T1	67		T2	16		T3	2
valid_sources[0x03]	28461	1			T1	59		T2	12		T3	2
valid_sources[0x04]	28194	1			T1	62		T2	13		T3	3
valid_sources[0x05]	29113	1			T1	65		T2	7		T3	1
valid_sources[0x06]	27961	1			T1	57		T2	12		T3	4
valid_sources[0x07]	28246	1			T1	60		T2	21		T3	2
valid_sources[0x08]	28497	1			T1	60		T2	16		T3	4
valid_sources[0x09]	29114	1			T1	58		T2	14		T3	1
valid_sources[0x0a]	28125	1			T1	61		T2	15		T3	2
valid_sources[0x0b]	28720	1			T1	73		T2	17		T3	3
valid_sources[0x0c]	27853	1			T1	63		T2	16		T3	2
valid_sources[0x0d]	27941	1			T1	62		T2	16		T3	3
valid_sources[0x0e]	28528	1			T1	63		T2	7		T3	2
valid_sources[0x0f]	29541	1			T1	66		T2	12		T3	5
valid_sources[0x10]	28362	1			T1	49		T2	21		T3	2
valid_sources[0x11]	28022	1			T1	71		T2	16		T3	4
valid_sources[0x12]	27668	1			T1	57		T2	16		T3	5
valid_sources[0x13]	28298	1			T1	68		T2	16		T3	2
valid_sources[0x14]	29896	1			T1	58		T2	10		T3	3
valid_sources[0x15]	28554	1			T1	51		T2	19		T3	1
valid_sources[0x16]	28046	1			T1	68		T2	10		T3	3
valid_sources[0x17]	28536	1			T1	75		T2	15		T3	4
valid_sources[0x18]	28490	1			T1	53		T2	15		T3	2
valid_sources[0x19]	29131	1			T1	55		T2	18		T3	3
valid_sources[0x1a]	28388	1			T1	60		T2	15		T3	4
valid_sources[0x1b]	28539	1			T1	63		T2	17		T8	1
valid_sources[0x1c]	28452	1			T1	66		T2	15		T3	3
valid_sources[0x1d]	27962	1			T1	68		T2	13		T3	1
valid_sources[0x1e]	28731	1			T1	61		T2	13		T3	3
valid_sources[0x1f]	28912	1			T1	50		T2	15		T3	2
valid_sources[0x20]	28415	1			T1	67		T2	19		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26291

1

T1

39

T2

10

T3

8

values[0x0]

all_enables

biggest_size

196922

1

T1

437

T2

103

T8

13

values[0x1]

all_enables

biggest_size

26185

1

T1

67

T2

9

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1578516	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256114

1

T1

537

T2

137

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628000	1			T1	1269		T2	308		T3	65
values[0x0]	577239	1			T1	1216		T2	301		T3	11
values[0x1]	629391	1			T1	1249		T2	296		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1210352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

624278

1

T1

1291

T2

314

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28776	1			T1	55		T2	18		T3	4
valid_sources[0x01]	27906	1			T1	57		T2	22		T3	3
valid_sources[0x02]	28583	1			T1	59		T2	16		T3	3
valid_sources[0x03]	28963	1			T1	54		T2	10		T8	2
valid_sources[0x04]	28294	1			T1	44		T2	21		T10	3
valid_sources[0x05]	29549	1			T1	41		T2	8		T3	4
valid_sources[0x06]	28366	1			T1	51		T2	17		T3	1
valid_sources[0x07]	28612	1			T1	50		T2	8		T3	4
valid_sources[0x08]	28800	1			T1	65		T2	9		T3	4
valid_sources[0x09]	28644	1			T1	65		T2	13		T3	1
valid_sources[0x0a]	28854	1			T1	47		T2	13		T3	3
valid_sources[0x0b]	29033	1			T1	59		T2	20		T3	2
valid_sources[0x0c]	29028	1			T1	58		T2	18		T3	3
valid_sources[0x0d]	28342	1			T1	64		T2	18		T3	2
valid_sources[0x0e]	28670	1			T1	61		T2	13		T3	3
valid_sources[0x0f]	28508	1			T1	56		T2	4		T3	3
valid_sources[0x10]	28814	1			T1	52		T2	12		T8	2
valid_sources[0x11]	28817	1			T1	66		T2	14		T3	1
valid_sources[0x12]	29050	1			T1	64		T2	7		T3	1
valid_sources[0x13]	28912	1			T1	66		T2	16		T3	2
valid_sources[0x14]	28000	1			T1	62		T2	20		T3	3
valid_sources[0x15]	28829	1			T1	67		T2	18		T3	1
valid_sources[0x16]	28200	1			T1	56		T2	20		T3	2
valid_sources[0x17]	28462	1			T1	69		T2	29		T3	2
valid_sources[0x18]	28469	1			T1	57		T2	15		T3	1
valid_sources[0x19]	29829	1			T1	59		T2	10		T3	2
valid_sources[0x1a]	28548	1			T1	61		T2	10		T3	3
valid_sources[0x1b]	29283	1			T1	61		T2	18		T9	14
valid_sources[0x1c]	28779	1			T1	59		T2	15		T3	2
valid_sources[0x1d]	28146	1			T1	64		T2	11		T3	1
valid_sources[0x1e]	28760	1			T1	63		T2	14		T3	2
valid_sources[0x1f]	28703	1			T1	61		T2	16		T3	2
valid_sources[0x20]	28256	1			T1	60		T2	11		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26950

1

T1

57

T2

10

T3

4

values[0x0]

all_enables

biggest_size

202357

1

T1

436

T2

113

T3

4

values[0x1]

all_enables

biggest_size

26807

1

T1

44

T2

14

T3

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1582417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250690

1

T1

556

T2

125

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	622304	1			T1	1343		T2	266		T3	43
values[0x0]	587600	1			T1	1328		T2	274		T3	7
values[0x1]	623203	1			T1	1418		T2	279		T3	68

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1223033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

610074

1

T1

1377

T2

265

T3

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29629	1			T1	64		T2	5		T3	2
valid_sources[0x01]	28288	1			T1	69		T2	40		T3	3
valid_sources[0x02]	28834	1			T1	64		T2	3		T3	3
valid_sources[0x03]	28137	1			T1	64		T2	16		T8	2
valid_sources[0x04]	28347	1			T1	62		T2	3		T3	1
valid_sources[0x05]	29475	1			T1	54		T2	8		T3	2
valid_sources[0x06]	29179	1			T1	70		T2	11		T3	2
valid_sources[0x07]	28830	1			T1	63		T2	14		T3	1
valid_sources[0x08]	28572	1			T1	62		T2	5		T3	2
valid_sources[0x09]	28773	1			T1	69		T2	22		T8	1
valid_sources[0x0a]	29116	1			T1	68		T2	2		T3	2
valid_sources[0x0b]	29564	1			T1	53		T2	8		T3	2
valid_sources[0x0c]	28050	1			T1	88		T2	10		T3	1
valid_sources[0x0d]	28440	1			T1	62		T2	11		T8	2
valid_sources[0x0e]	28363	1			T1	70		T2	10		T8	4
valid_sources[0x0f]	28685	1			T1	64		T2	5		T3	5
valid_sources[0x10]	28383	1			T1	60		T2	12		T3	1
valid_sources[0x11]	30339	1			T1	62		T2	10		T3	3
valid_sources[0x12]	28603	1			T1	56		T2	41		T3	1
valid_sources[0x13]	28958	1			T1	64		T2	15		T3	4
valid_sources[0x14]	28113	1			T1	66		T2	9		T3	2
valid_sources[0x15]	29114	1			T1	69		T2	11		T3	1
valid_sources[0x16]	28467	1			T1	54		T2	35		T8	1
valid_sources[0x17]	28512	1			T1	49		T2	10		T3	1
valid_sources[0x18]	27675	1			T1	61		T2	16		T3	3
valid_sources[0x19]	28906	1			T1	56		T2	23		T3	1
valid_sources[0x1a]	28656	1			T1	61		T2	10		T8	1
valid_sources[0x1b]	28720	1			T1	64		T2	17		T3	3
valid_sources[0x1c]	29088	1			T1	58		T2	19		T3	5
valid_sources[0x1d]	27782	1			T1	62		T2	15		T3	2
valid_sources[0x1e]	28487	1			T1	65		T2	16		T3	1
valid_sources[0x1f]	28805	1			T1	58		T2	23		T3	2
valid_sources[0x20]	28205	1			T1	72		T2	5		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26565

1

T1

56

T2

11

T3

4

values[0x0]

all_enables

biggest_size

197726

1

T1

438

T2

104

T3

4

values[0x1]

all_enables

biggest_size

26399

1

T1

62

T2

10

T3

4