Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8187220	0	0
GntImpliesValid_A	2147483647	8187220	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8187220	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	463837648	0	0
ReadyAndValidImplyGrant_A	2147483647	8187220	0	0
ReqAndReadyImplyGrant_A	2147483647	8187220	0	0
ReqImpliesValid_A	2147483647	35439633	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	51550	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8187220	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10888704	10888656	0	0
T2	451728	450696	0	0
T3	397008	396072	0	0
T7	317304	298776	0	0
T8	39648	39264	0	0
T9	414288	414024	0	0
T10	2504088	2479128	0	0
T11	1151808	1151208	0	0
T12	47040	45960	0	0
T13	54048	52224	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8187220	0	0
T1	5898048	11764	0	0
T2	451728	1311	0	0
T3	397008	8856	0	0
T7	317304	1343	0	0
T8	39648	415	0	0
T9	414288	978	0	0
T10	2504088	8746	0	0
T11	1151808	23297	0	0
T12	47040	416	0	0
T13	54048	357	0	0
T14	473055	918	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8187220	0	0
T1	5898048	11764	0	0
T2	451728	1311	0	0
T3	397008	8856	0	0
T7	317304	1343	0	0
T8	39648	415	0	0
T9	414288	978	0	0
T10	2504088	8746	0	0
T11	1151808	23297	0	0
T12	47040	416	0	0
T13	54048	357	0	0
T14	473055	918	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10888704	10888656	0	0
T2	451728	450696	0	0
T3	397008	396072	0	0
T7	317304	298776	0	0
T8	39648	39264	0	0
T9	414288	414024	0	0
T10	2504088	2479128	0	0
T11	1151808	1151208	0	0
T12	47040	45960	0	0
T13	54048	52224	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10888704	10888656	0	0
T2	451728	450696	0	0
T3	397008	396072	0	0
T7	317304	298776	0	0
T8	39648	39264	0	0
T9	414288	414024	0	0
T10	2504088	2479128	0	0
T11	1151808	1151208	0	0
T12	47040	45960	0	0
T13	54048	52224	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8187220	0	0
T1	5898048	11764	0	0
T2	451728	1311	0	0
T3	397008	8856	0	0
T7	317304	1343	0	0
T8	39648	415	0	0
T9	414288	978	0	0
T10	2504088	8746	0	0
T11	1151808	23297	0	0
T12	47040	416	0	0
T13	54048	357	0	0
T14	473055	918	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	463837648	0	0
T1	10435008	414982	0	0
T2	451728	25407	0	0
T3	397008	12424	0	0
T7	317304	16976	0	0
T8	39648	434	0	0
T9	414288	21640	0	0
T10	2504088	145098	0	0
T11	1151808	11827	0	0
T12	47040	547	0	0
T13	54048	695	0	0
T14	43005	841	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8187220	0	0
T1	5898048	11764	0	0
T2	451728	1311	0	0
T3	397008	8856	0	0
T7	317304	1343	0	0
T8	39648	415	0	0
T9	414288	978	0	0
T10	2504088	8746	0	0
T11	1151808	23297	0	0
T12	47040	416	0	0
T13	54048	357	0	0
T14	473055	918	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8187220	0	0
T1	5898048	11764	0	0
T2	451728	1311	0	0
T3	397008	8856	0	0
T7	317304	1343	0	0
T8	39648	415	0	0
T9	414288	978	0	0
T10	2504088	8746	0	0
T11	1151808	23297	0	0
T12	47040	416	0	0
T13	54048	357	0	0
T14	473055	918	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35439633	0	0
T1	5898048	30169	0	0
T2	451728	2704	0	0
T3	397008	10633	0	0
T7	317304	4925	0	0
T8	39648	466	0	0
T9	414288	1715	0	0
T10	2504088	19113	0	0
T11	1151808	40150	0	0
T12	47040	476	0	0
T13	54048	445	0	0
T14	473055	1176	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51550	0	21600
T1	453696	14	0	1
T2	18822	0	0	1
T3	33084	24	0	2
T7	26442	0	0	2
T8	3304	0	0	2
T9	34524	0	0	2
T10	208674	2	0	2
T11	95984	634	0	2
T12	3920	0	0	2
T13	4504	0	0	2
T14	43005	0	0	1
T15	0	5	0	0
T16	0	43	0	0
T17	0	18	0	0
T18	0	6	0	0
T19	0	871	0	0
T20	0	15	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	1829	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10888704	10888656	0	0
T2	451728	450696	0	0
T3	397008	396072	0	0
T7	317304	298776	0	0
T8	39648	39264	0	0
T9	414288	414024	0	0
T10	2504088	2479128	0	0
T11	1151808	1151208	0	0
T12	47040	45960	0	0
T13	54048	52224	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8187220	0	0
T1	5898048	11764	0	0
T2	451728	1311	0	0
T3	397008	8856	0	0
T7	317304	1343	0	0
T8	39648	415	0	0
T9	414288	978	0	0
T10	2504088	8746	0	0
T11	1151808	23297	0	0
T12	47040	416	0	0
T13	54048	357	0	0
T14	473055	918	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	916795	0	0
GntImpliesValid_A	426957799	916795	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	916795	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	12119260	0	0
ReadyAndValidImplyGrant_A	426957799	916795	0	0
ReqAndReadyImplyGrant_A	426957799	916795	0	0
ReqImpliesValid_A	426957799	2575205	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	916795	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	916795	0	0
T1	453696	864	0	0
T2	18822	139	0	0
T3	16542	986	0	0
T7	13221	135	0	0
T8	1652	50	0	0
T9	17262	113	0	0
T10	104337	973	0	0
T11	47992	3147	0	0
T12	1960	36	0	0
T13	2252	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	916795	0	0
T1	453696	864	0	0
T2	18822	139	0	0
T3	16542	986	0	0
T7	13221	135	0	0
T8	1652	50	0	0
T9	17262	113	0	0
T10	104337	973	0	0
T11	47992	3147	0	0
T12	1960	36	0	0
T13	2252	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	916795	0	0
T1	453696	864	0	0
T2	18822	139	0	0
T3	16542	986	0	0
T7	13221	135	0	0
T8	1652	50	0	0
T9	17262	113	0	0
T10	104337	973	0	0
T11	47992	3147	0	0
T12	1960	36	0	0
T13	2252	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	12119260	0	0
T1	453696	3647	0	0
T2	18822	1007	0	0
T3	16542	739	0	0
T7	13221	913	0	0
T8	1652	40	0	0
T9	17262	862	0	0
T10	104337	6758	0	0
T11	47992	1468	0	0
T12	1960	31	0	0
T13	2252	25	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	916795	0	0
T1	453696	864	0	0
T2	18822	139	0	0
T3	16542	986	0	0
T7	13221	135	0	0
T8	1652	50	0	0
T9	17262	113	0	0
T10	104337	973	0	0
T11	47992	3147	0	0
T12	1960	36	0	0
T13	2252	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	916795	0	0
T1	453696	864	0	0
T2	18822	139	0	0
T3	16542	986	0	0
T7	13221	135	0	0
T8	1652	50	0	0
T9	17262	113	0	0
T10	104337	973	0	0
T11	47992	3147	0	0
T12	1960	36	0	0
T13	2252	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	2575205	0	0
T1	453696	1223	0	0
T2	18822	228	0	0
T3	16542	1234	0	0
T7	13221	217	0	0
T8	1652	61	0	0
T9	17262	113	0	0
T10	104337	1280	0	0
T11	47992	4828	0	0
T12	1960	42	0	0
T13	2252	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	916795	0	0
T1	453696	864	0	0
T2	18822	139	0	0
T3	16542	986	0	0
T7	13221	135	0	0
T8	1652	50	0	0
T9	17262	113	0	0
T10	104337	973	0	0
T11	47992	3147	0	0
T12	1960	36	0	0
T13	2252	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	915867	0	0
GntImpliesValid_A	426957799	915867	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	915867	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	11887310	0	0
ReadyAndValidImplyGrant_A	426957799	915867	0	0
ReqAndReadyImplyGrant_A	426957799	915867	0	0
ReqImpliesValid_A	426957799	2528113	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	915867	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915867	0	0
T1	453696	1473	0	0
T2	18822	155	0	0
T3	16542	1015	0	0
T7	13221	157	0	0
T8	1652	53	0	0
T9	17262	99	0	0
T10	104337	962	0	0
T11	47992	3309	0	0
T12	1960	38	0	0
T13	2252	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915867	0	0
T1	453696	1473	0	0
T2	18822	155	0	0
T3	16542	1015	0	0
T7	13221	157	0	0
T8	1652	53	0	0
T9	17262	99	0	0
T10	104337	962	0	0
T11	47992	3309	0	0
T12	1960	38	0	0
T13	2252	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915867	0	0
T1	453696	1473	0	0
T2	18822	155	0	0
T3	16542	1015	0	0
T7	13221	157	0	0
T8	1652	53	0	0
T9	17262	99	0	0
T10	104337	962	0	0
T11	47992	3309	0	0
T12	1960	38	0	0
T13	2252	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	11887310	0	0
T1	453696	5435	0	0
T2	18822	1024	0	0
T3	16542	735	0	0
T7	13221	1145	0	0
T8	1652	44	0	0
T9	17262	731	0	0
T10	104337	6783	0	0
T11	47992	1817	0	0
T12	1960	31	0	0
T13	2252	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915867	0	0
T1	453696	1473	0	0
T2	18822	155	0	0
T3	16542	1015	0	0
T7	13221	157	0	0
T8	1652	53	0	0
T9	17262	99	0	0
T10	104337	962	0	0
T11	47992	3309	0	0
T12	1960	38	0	0
T13	2252	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915867	0	0
T1	453696	1473	0	0
T2	18822	155	0	0
T3	16542	1015	0	0
T7	13221	157	0	0
T8	1652	53	0	0
T9	17262	99	0	0
T10	104337	962	0	0
T11	47992	3309	0	0
T12	1960	38	0	0
T13	2252	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	2528113	0	0
T1	453696	2821	0	0
T2	18822	251	0	0
T3	16542	1296	0	0
T7	13221	293	0	0
T8	1652	63	0	0
T9	17262	100	0	0
T10	104337	1453	0	0
T11	47992	4803	0	0
T12	1960	46	0	0
T13	2252	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915867	0	0
T1	453696	1473	0	0
T2	18822	155	0	0
T3	16542	1015	0	0
T7	13221	157	0	0
T8	1652	53	0	0
T9	17262	99	0	0
T10	104337	962	0	0
T11	47992	3309	0	0
T12	1960	38	0	0
T13	2252	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	225422	0	0
GntImpliesValid_A	426957799	225422	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	225422	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3051129	0	0
ReadyAndValidImplyGrant_A	426957799	225422	0	0
ReqAndReadyImplyGrant_A	426957799	225422	0	0
ReqImpliesValid_A	426957799	600281	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	225422	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	225422	0	0
T2	18822	32	0	0
T3	16542	242	0	0
T7	13221	12	0	0
T8	1652	12	0	0
T9	17262	25	0	0
T10	104337	230	0	0
T11	47992	1270	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	225422	0	0
T2	18822	32	0	0
T3	16542	242	0	0
T7	13221	12	0	0
T8	1652	12	0	0
T9	17262	25	0	0
T10	104337	230	0	0
T11	47992	1270	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	225422	0	0
T2	18822	32	0	0
T3	16542	242	0	0
T7	13221	12	0	0
T8	1652	12	0	0
T9	17262	25	0	0
T10	104337	230	0	0
T11	47992	1270	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3051129	0	0
T1	453696	1	0	0
T2	18822	246	0	0
T3	16542	230	0	0
T7	13221	108	0	0
T8	1652	13	0	0
T9	17262	178	0	0
T10	104337	1758	0	0
T11	47992	246	0	0
T12	1960	13	0	0
T13	2252	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	225422	0	0
T2	18822	32	0	0
T3	16542	242	0	0
T7	13221	12	0	0
T8	1652	12	0	0
T9	17262	25	0	0
T10	104337	230	0	0
T11	47992	1270	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	225422	0	0
T2	18822	32	0	0
T3	16542	242	0	0
T7	13221	12	0	0
T8	1652	12	0	0
T9	17262	25	0	0
T10	104337	230	0	0
T11	47992	1270	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	600281	0	0
T2	18822	34	0	0
T3	16542	255	0	0
T7	13221	12	0	0
T8	1652	12	0	0
T9	17262	25	0	0
T10	104337	275	0	0
T11	47992	2296	0	0
T12	1960	16	0	0
T13	2252	12	0	0
T14	43005	114	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	225422	0	0
T2	18822	32	0	0
T3	16542	242	0	0
T7	13221	12	0	0
T8	1652	12	0	0
T9	17262	25	0	0
T10	104337	230	0	0
T11	47992	1270	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	226643	0	0
GntImpliesValid_A	426957799	226643	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	226643	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3053846	0	0
ReadyAndValidImplyGrant_A	426957799	226643	0	0
ReqAndReadyImplyGrant_A	426957799	226643	0	0
ReqImpliesValid_A	426957799	600715	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	226643	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226643	0	0
T1	453696	461	0	0
T2	18822	32	0	0
T3	16542	244	0	0
T7	13221	15	0	0
T8	1652	14	0	0
T9	17262	31	0	0
T10	104337	223	0	0
T11	47992	699	0	0
T12	1960	7	0	0
T13	2252	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226643	0	0
T1	453696	461	0	0
T2	18822	32	0	0
T3	16542	244	0	0
T7	13221	15	0	0
T8	1652	14	0	0
T9	17262	31	0	0
T10	104337	223	0	0
T11	47992	699	0	0
T12	1960	7	0	0
T13	2252	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226643	0	0
T1	453696	461	0	0
T2	18822	32	0	0
T3	16542	244	0	0
T7	13221	15	0	0
T8	1652	14	0	0
T9	17262	31	0	0
T10	104337	223	0	0
T11	47992	699	0	0
T12	1960	7	0	0
T13	2252	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3053846	0	0
T1	453696	1504	0	0
T2	18822	247	0	0
T3	16542	236	0	0
T7	13221	104	0	0
T8	1652	14	0	0
T9	17262	249	0	0
T10	104337	1647	0	0
T11	47992	232	0	0
T12	1960	8	0	0
T13	2252	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226643	0	0
T1	453696	461	0	0
T2	18822	32	0	0
T3	16542	244	0	0
T7	13221	15	0	0
T8	1652	14	0	0
T9	17262	31	0	0
T10	104337	223	0	0
T11	47992	699	0	0
T12	1960	7	0	0
T13	2252	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226643	0	0
T1	453696	461	0	0
T2	18822	32	0	0
T3	16542	244	0	0
T7	13221	15	0	0
T8	1652	14	0	0
T9	17262	31	0	0
T10	104337	223	0	0
T11	47992	699	0	0
T12	1960	7	0	0
T13	2252	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	600715	0	0
T1	453696	1258	0	0
T2	18822	32	0	0
T3	16542	253	0	0
T7	13221	15	0	0
T8	1652	15	0	0
T9	17262	34	0	0
T10	104337	285	0	0
T11	47992	1168	0	0
T12	1960	7	0	0
T13	2252	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226643	0	0
T1	453696	461	0	0
T2	18822	32	0	0
T3	16542	244	0	0
T7	13221	15	0	0
T8	1652	14	0	0
T9	17262	31	0	0
T10	104337	223	0	0
T11	47992	699	0	0
T12	1960	7	0	0
T13	2252	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	226315	0	0
GntImpliesValid_A	426957799	226315	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	226315	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	5634170	0	0
ReadyAndValidImplyGrant_A	426957799	226315	0	0
ReqAndReadyImplyGrant_A	426957799	226315	0	0
ReqImpliesValid_A	426957799	1354564	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	226315	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226315	0	0
T2	18822	36	0	0
T3	16542	252	0	0
T7	13221	15	0	0
T8	1652	13	0	0
T9	17262	20	0	0
T10	104337	240	0	0
T11	47992	1115	0	0
T12	1960	11	0	0
T13	2252	10	0	0
T14	43005	86	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226315	0	0
T2	18822	36	0	0
T3	16542	252	0	0
T7	13221	15	0	0
T8	1652	13	0	0
T9	17262	20	0	0
T10	104337	240	0	0
T11	47992	1115	0	0
T12	1960	11	0	0
T13	2252	10	0	0
T14	43005	86	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226315	0	0
T2	18822	36	0	0
T3	16542	252	0	0
T7	13221	15	0	0
T8	1652	13	0	0
T9	17262	20	0	0
T10	104337	240	0	0
T11	47992	1115	0	0
T12	1960	11	0	0
T13	2252	10	0	0
T14	43005	86	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	5634170	0	0
T2	18822	480	0	0
T3	16542	2430	0	0
T7	13221	345	0	0
T8	1652	47	0	0
T9	17262	172	0	0
T10	104337	2310	0	0
T11	47992	1310	0	0
T12	1960	66	0	0
T13	2252	159	0	0
T14	43005	841	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226315	0	0
T2	18822	36	0	0
T3	16542	252	0	0
T7	13221	15	0	0
T8	1652	13	0	0
T9	17262	20	0	0
T10	104337	240	0	0
T11	47992	1115	0	0
T12	1960	11	0	0
T13	2252	10	0	0
T14	43005	86	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226315	0	0
T2	18822	36	0	0
T3	16542	252	0	0
T7	13221	15	0	0
T8	1652	13	0	0
T9	17262	20	0	0
T10	104337	240	0	0
T11	47992	1115	0	0
T12	1960	11	0	0
T13	2252	10	0	0
T14	43005	86	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	1354564	0	0
T2	18822	64	0	0
T3	16542	693	0	0
T7	13221	68	0	0
T8	1652	21	0	0
T9	17262	20	0	0
T10	104337	324	0	0
T11	47992	4500	0	0
T12	1960	21	0	0
T13	2252	22	0	0
T14	43005	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226315	0	0
T2	18822	36	0	0
T3	16542	252	0	0
T7	13221	15	0	0
T8	1652	13	0	0
T9	17262	20	0	0
T10	104337	240	0	0
T11	47992	1115	0	0
T12	1960	11	0	0
T13	2252	10	0	0
T14	43005	86	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	224196	0	0
GntImpliesValid_A	426957799	224196	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	224196	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	5417452	0	0
ReadyAndValidImplyGrant_A	426957799	224196	0	0
ReqAndReadyImplyGrant_A	426957799	224196	0	0
ReqImpliesValid_A	426957799	1306374	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	224196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224196	0	0
T1	453696	424	0	0
T2	18822	30	0	0
T3	16542	243	0	0
T7	13221	11	0	0
T8	1652	10	0	0
T9	17262	25	0	0
T10	104337	227	0	0
T11	47992	654	0	0
T12	1960	18	0	0
T13	2252	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224196	0	0
T1	453696	424	0	0
T2	18822	30	0	0
T3	16542	243	0	0
T7	13221	11	0	0
T8	1652	10	0	0
T9	17262	25	0	0
T10	104337	227	0	0
T11	47992	654	0	0
T12	1960	18	0	0
T13	2252	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224196	0	0
T1	453696	424	0	0
T2	18822	30	0	0
T3	16542	243	0	0
T7	13221	11	0	0
T8	1652	10	0	0
T9	17262	25	0	0
T10	104337	227	0	0
T11	47992	654	0	0
T12	1960	18	0	0
T13	2252	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	5417452	0	0
T1	453696	1537	0	0
T2	18822	477	0	0
T3	16542	1225	0	0
T7	13221	333	0	0
T8	1652	34	0	0
T9	17262	135	0	0
T10	104337	2127	0	0
T11	47992	1383	0	0
T12	1960	72	0	0
T13	2252	96	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224196	0	0
T1	453696	424	0	0
T2	18822	30	0	0
T3	16542	243	0	0
T7	13221	11	0	0
T8	1652	10	0	0
T9	17262	25	0	0
T10	104337	227	0	0
T11	47992	654	0	0
T12	1960	18	0	0
T13	2252	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224196	0	0
T1	453696	424	0	0
T2	18822	30	0	0
T3	16542	243	0	0
T7	13221	11	0	0
T8	1652	10	0	0
T9	17262	25	0	0
T10	104337	227	0	0
T11	47992	654	0	0
T12	1960	18	0	0
T13	2252	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	1306374	0	0
T1	453696	1176	0	0
T2	18822	41	0	0
T3	16542	389	0	0
T7	13221	11	0	0
T8	1652	14	0	0
T9	17262	25	0	0
T10	104337	241	0	0
T11	47992	3656	0	0
T12	1960	34	0	0
T13	2252	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224196	0	0
T1	453696	424	0	0
T2	18822	30	0	0
T3	16542	243	0	0
T7	13221	11	0	0
T8	1652	10	0	0
T9	17262	25	0	0
T10	104337	227	0	0
T11	47992	654	0	0
T12	1960	18	0	0
T13	2252	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	213999	0	0
GntImpliesValid_A	426957799	213999	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	213999	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	5525950	0	0
ReadyAndValidImplyGrant_A	426957799	213999	0	0
ReqAndReadyImplyGrant_A	426957799	213999	0	0
ReqImpliesValid_A	426957799	1351270	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	213999	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	213999	0	0
T1	453696	526	0	0
T2	18822	35	0	0
T3	16542	241	0	0
T7	13221	10	0	0
T8	1652	10	0	0
T9	17262	28	0	0
T10	104337	244	0	0
T11	47992	666	0	0
T12	1960	14	0	0
T13	2252	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	213999	0	0
T1	453696	526	0	0
T2	18822	35	0	0
T3	16542	241	0	0
T7	13221	10	0	0
T8	1652	10	0	0
T9	17262	28	0	0
T10	104337	244	0	0
T11	47992	666	0	0
T12	1960	14	0	0
T13	2252	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	213999	0	0
T1	453696	526	0	0
T2	18822	35	0	0
T3	16542	241	0	0
T7	13221	10	0	0
T8	1652	10	0	0
T9	17262	28	0	0
T10	104337	244	0	0
T11	47992	666	0	0
T12	1960	14	0	0
T13	2252	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	5525950	0	0
T1	453696	2296	0	0
T2	18822	669	0	0
T3	16542	2192	0	0
T7	13221	141	0	0
T8	1652	32	0	0
T9	17262	156	0	0
T10	104337	2818	0	0
T11	47992	958	0	0
T12	1960	62	0	0
T13	2252	110	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	213999	0	0
T1	453696	526	0	0
T2	18822	35	0	0
T3	16542	241	0	0
T7	13221	10	0	0
T8	1652	10	0	0
T9	17262	28	0	0
T10	104337	244	0	0
T11	47992	666	0	0
T12	1960	14	0	0
T13	2252	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	213999	0	0
T1	453696	526	0	0
T2	18822	35	0	0
T3	16542	241	0	0
T7	13221	10	0	0
T8	1652	10	0	0
T9	17262	28	0	0
T10	104337	244	0	0
T11	47992	666	0	0
T12	1960	14	0	0
T13	2252	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	1351270	0	0
T1	453696	1444	0	0
T2	18822	52	0	0
T3	16542	554	0	0
T7	13221	20	0	0
T8	1652	16	0	0
T9	17262	28	0	0
T10	104337	434	0	0
T11	47992	2834	0	0
T12	1960	14	0	0
T13	2252	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	213999	0	0
T1	453696	526	0	0
T2	18822	35	0	0
T3	16542	241	0	0
T7	13221	10	0	0
T8	1652	10	0	0
T9	17262	28	0	0
T10	104337	244	0	0
T11	47992	666	0	0
T12	1960	14	0	0
T13	2252	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	224883	0	0
GntImpliesValid_A	426957799	224883	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	224883	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	5456536	0	0
ReadyAndValidImplyGrant_A	426957799	224883	0	0
ReqAndReadyImplyGrant_A	426957799	224883	0	0
ReqImpliesValid_A	426957799	1220792	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	224883	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224883	0	0
T1	453696	1510	0	0
T2	18822	45	0	0
T3	16542	232	0	0
T7	13221	10	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	254	0	0
T11	47992	241	0	0
T12	1960	11	0	0
T13	2252	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224883	0	0
T1	453696	1510	0	0
T2	18822	45	0	0
T3	16542	232	0	0
T7	13221	10	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	254	0	0
T11	47992	241	0	0
T12	1960	11	0	0
T13	2252	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224883	0	0
T1	453696	1510	0	0
T2	18822	45	0	0
T3	16542	232	0	0
T7	13221	10	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	254	0	0
T11	47992	241	0	0
T12	1960	11	0	0
T13	2252	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	5456536	0	0
T1	453696	6714	0	0
T2	18822	651	0	0
T3	16542	1366	0	0
T7	13221	169	0	0
T8	1652	46	0	0
T9	17262	366	0	0
T10	104337	3217	0	0
T11	47992	883	0	0
T12	1960	72	0	0
T13	2252	99	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224883	0	0
T1	453696	1510	0	0
T2	18822	45	0	0
T3	16542	232	0	0
T7	13221	10	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	254	0	0
T11	47992	241	0	0
T12	1960	11	0	0
T13	2252	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224883	0	0
T1	453696	1510	0	0
T2	18822	45	0	0
T3	16542	232	0	0
T7	13221	10	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	254	0	0
T11	47992	241	0	0
T12	1960	11	0	0
T13	2252	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	1220792	0	0
T1	453696	4296	0	0
T2	18822	72	0	0
T3	16542	368	0	0
T7	13221	10	0	0
T8	1652	21	0	0
T9	17262	28	0	0
T10	104337	367	0	0
T11	47992	264	0	0
T12	1960	16	0	0
T13	2252	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	224883	0	0
T1	453696	1510	0	0
T2	18822	45	0	0
T3	16542	232	0	0
T7	13221	10	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	254	0	0
T11	47992	241	0	0
T12	1960	11	0	0
T13	2252	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	222010	0	0
GntImpliesValid_A	426957799	222010	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	222010	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	2955193	0	0
ReadyAndValidImplyGrant_A	426957799	222010	0	0
ReqAndReadyImplyGrant_A	426957799	222010	0	0
ReqImpliesValid_A	426957799	574017	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	222010	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222010	0	0
T2	18822	38	0	0
T3	16542	256	0	0
T7	13221	8	0	0
T8	1652	17	0	0
T9	17262	37	0	0
T10	104337	220	0	0
T11	47992	212	0	0
T12	1960	14	0	0
T13	2252	3	0	0
T14	43005	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222010	0	0
T2	18822	38	0	0
T3	16542	256	0	0
T7	13221	8	0	0
T8	1652	17	0	0
T9	17262	37	0	0
T10	104337	220	0	0
T11	47992	212	0	0
T12	1960	14	0	0
T13	2252	3	0	0
T14	43005	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222010	0	0
T2	18822	38	0	0
T3	16542	256	0	0
T7	13221	8	0	0
T8	1652	17	0	0
T9	17262	37	0	0
T10	104337	220	0	0
T11	47992	212	0	0
T12	1960	14	0	0
T13	2252	3	0	0
T14	43005	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	2955193	0	0
T1	453696	1	0	0
T2	18822	306	0	0
T3	16542	242	0	0
T7	13221	59	0	0
T8	1652	18	0	0
T9	17262	226	0	0
T10	104337	1660	0	0
T11	47992	213	0	0
T12	1960	15	0	0
T13	2252	4	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222010	0	0
T2	18822	38	0	0
T3	16542	256	0	0
T7	13221	8	0	0
T8	1652	17	0	0
T9	17262	37	0	0
T10	104337	220	0	0
T11	47992	212	0	0
T12	1960	14	0	0
T13	2252	3	0	0
T14	43005	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222010	0	0
T2	18822	38	0	0
T3	16542	256	0	0
T7	13221	8	0	0
T8	1652	17	0	0
T9	17262	37	0	0
T10	104337	220	0	0
T11	47992	212	0	0
T12	1960	14	0	0
T13	2252	3	0	0
T14	43005	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	574017	0	0
T2	18822	50	0	0
T3	16542	271	0	0
T7	13221	15	0	0
T8	1652	17	0	0
T9	17262	37	0	0
T10	104337	237	0	0
T11	47992	213	0	0
T12	1960	14	0	0
T13	2252	3	0	0
T14	43005	107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222010	0	0
T2	18822	38	0	0
T3	16542	256	0	0
T7	13221	8	0	0
T8	1652	17	0	0
T9	17262	37	0	0
T10	104337	220	0	0
T11	47992	212	0	0
T12	1960	14	0	0
T13	2252	3	0	0
T14	43005	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	229320	0	0
GntImpliesValid_A	426957799	229320	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	229320	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3087234	0	0
ReadyAndValidImplyGrant_A	426957799	229320	0	0
ReqAndReadyImplyGrant_A	426957799	229320	0	0
ReqImpliesValid_A	426957799	608693	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	229320	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	229320	0	0
T2	18822	34	0	0
T3	16542	230	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	31	0	0
T10	104337	239	0	0
T11	47992	768	0	0
T12	1960	14	0	0
T13	2252	10	0	0
T14	43005	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	229320	0	0
T2	18822	34	0	0
T3	16542	230	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	31	0	0
T10	104337	239	0	0
T11	47992	768	0	0
T12	1960	14	0	0
T13	2252	10	0	0
T14	43005	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	229320	0	0
T2	18822	34	0	0
T3	16542	230	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	31	0	0
T10	104337	239	0	0
T11	47992	768	0	0
T12	1960	14	0	0
T13	2252	10	0	0
T14	43005	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3087234	0	0
T1	453696	1	0	0
T2	18822	284	0	0
T3	16542	220	0	0
T7	13221	96	0	0
T8	1652	14	0	0
T9	17262	265	0	0
T10	104337	1840	0	0
T11	47992	561	0	0
T12	1960	15	0	0
T13	2252	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	229320	0	0
T2	18822	34	0	0
T3	16542	230	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	31	0	0
T10	104337	239	0	0
T11	47992	768	0	0
T12	1960	14	0	0
T13	2252	10	0	0
T14	43005	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	229320	0	0
T2	18822	34	0	0
T3	16542	230	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	31	0	0
T10	104337	239	0	0
T11	47992	768	0	0
T12	1960	14	0	0
T13	2252	10	0	0
T14	43005	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	608693	0	0
T2	18822	38	0	0
T3	16542	241	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	31	0	0
T10	104337	360	0	0
T11	47992	977	0	0
T12	1960	14	0	0
T13	2252	10	0	0
T14	43005	111	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	229320	0	0
T2	18822	34	0	0
T3	16542	230	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	31	0	0
T10	104337	239	0	0
T11	47992	768	0	0
T12	1960	14	0	0
T13	2252	10	0	0
T14	43005	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	222223	0	0
GntImpliesValid_A	426957799	222223	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	222223	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3002957	0	0
ReadyAndValidImplyGrant_A	426957799	222223	0	0
ReqAndReadyImplyGrant_A	426957799	222223	0	0
ReqImpliesValid_A	426957799	551924	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	222223	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222223	0	0
T2	18822	36	0	0
T3	16542	257	0	0
T7	13221	10	0	0
T8	1652	4	0	0
T9	17262	22	0	0
T10	104337	238	0	0
T11	47992	691	0	0
T12	1960	25	0	0
T13	2252	19	0	0
T14	43005	79	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222223	0	0
T2	18822	36	0	0
T3	16542	257	0	0
T7	13221	10	0	0
T8	1652	4	0	0
T9	17262	22	0	0
T10	104337	238	0	0
T11	47992	691	0	0
T12	1960	25	0	0
T13	2252	19	0	0
T14	43005	79	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222223	0	0
T2	18822	36	0	0
T3	16542	257	0	0
T7	13221	10	0	0
T8	1652	4	0	0
T9	17262	22	0	0
T10	104337	238	0	0
T11	47992	691	0	0
T12	1960	25	0	0
T13	2252	19	0	0
T14	43005	79	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3002957	0	0
T1	453696	1	0	0
T2	18822	250	0	0
T3	16542	248	0	0
T7	13221	58	0	0
T8	1652	5	0	0
T9	17262	133	0	0
T10	104337	1927	0	0
T11	47992	250	0	0
T12	1960	24	0	0
T13	2252	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222223	0	0
T2	18822	36	0	0
T3	16542	257	0	0
T7	13221	10	0	0
T8	1652	4	0	0
T9	17262	22	0	0
T10	104337	238	0	0
T11	47992	691	0	0
T12	1960	25	0	0
T13	2252	19	0	0
T14	43005	79	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222223	0	0
T2	18822	36	0	0
T3	16542	257	0	0
T7	13221	10	0	0
T8	1652	4	0	0
T9	17262	22	0	0
T10	104337	238	0	0
T11	47992	691	0	0
T12	1960	25	0	0
T13	2252	19	0	0
T14	43005	79	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	551924	0	0
T2	18822	38	0	0
T3	16542	267	0	0
T7	13221	10	0	0
T8	1652	4	0	0
T9	17262	22	0	0
T10	104337	287	0	0
T11	47992	1134	0	0
T12	1960	27	0	0
T13	2252	20	0	0
T14	43005	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	222223	0	0
T2	18822	36	0	0
T3	16542	257	0	0
T7	13221	10	0	0
T8	1652	4	0	0
T9	17262	22	0	0
T10	104337	238	0	0
T11	47992	691	0	0
T12	1960	25	0	0
T13	2252	19	0	0
T14	43005	79	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	223922	0	0
GntImpliesValid_A	426957799	223922	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	223922	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3042758	0	0
ReadyAndValidImplyGrant_A	426957799	223922	0	0
ReqAndReadyImplyGrant_A	426957799	223922	0	0
ReqImpliesValid_A	426957799	573394	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	223922	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223922	0	0
T2	18822	41	0	0
T3	16542	223	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	237	0	0
T11	47992	673	0	0
T12	1960	6	0	0
T13	2252	9	0	0
T14	43005	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223922	0	0
T2	18822	41	0	0
T3	16542	223	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	237	0	0
T11	47992	673	0	0
T12	1960	6	0	0
T13	2252	9	0	0
T14	43005	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223922	0	0
T2	18822	41	0	0
T3	16542	223	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	237	0	0
T11	47992	673	0	0
T12	1960	6	0	0
T13	2252	9	0	0
T14	43005	83	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3042758	0	0
T1	453696	1	0	0
T2	18822	333	0	0
T3	16542	211	0	0
T7	13221	113	0	0
T8	1652	11	0	0
T9	17262	208	0	0
T10	104337	1895	0	0
T11	47992	236	0	0
T12	1960	7	0	0
T13	2252	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223922	0	0
T2	18822	41	0	0
T3	16542	223	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	237	0	0
T11	47992	673	0	0
T12	1960	6	0	0
T13	2252	9	0	0
T14	43005	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223922	0	0
T2	18822	41	0	0
T3	16542	223	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	237	0	0
T11	47992	673	0	0
T12	1960	6	0	0
T13	2252	9	0	0
T14	43005	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	573394	0	0
T2	18822	50	0	0
T3	16542	236	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	286	0	0
T11	47992	1112	0	0
T12	1960	6	0	0
T13	2252	10	0	0
T14	43005	147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223922	0	0
T2	18822	41	0	0
T3	16542	223	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	237	0	0
T11	47992	673	0	0
T12	1960	6	0	0
T13	2252	9	0	0
T14	43005	83	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	233639	0	0
GntImpliesValid_A	426957799	233639	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	233639	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3042002	0	0
ReadyAndValidImplyGrant_A	426957799	233639	0	0
ReqAndReadyImplyGrant_A	426957799	233639	0	0
ReqImpliesValid_A	426957799	636425	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	233639	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	233639	0	0
T1	453696	964	0	0
T2	18822	41	0	0
T3	16542	241	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	27	0	0
T10	104337	230	0	0
T11	47992	712	0	0
T12	1960	16	0	0
T13	2252	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	233639	0	0
T1	453696	964	0	0
T2	18822	41	0	0
T3	16542	241	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	27	0	0
T10	104337	230	0	0
T11	47992	712	0	0
T12	1960	16	0	0
T13	2252	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	233639	0	0
T1	453696	964	0	0
T2	18822	41	0	0
T3	16542	241	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	27	0	0
T10	104337	230	0	0
T11	47992	712	0	0
T12	1960	16	0	0
T13	2252	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3042002	0	0
T1	453696	3054	0	0
T2	18822	317	0	0
T3	16542	227	0	0
T7	13221	126	0	0
T8	1652	14	0	0
T9	17262	179	0	0
T10	104337	1737	0	0
T11	47992	228	0	0
T12	1960	15	0	0
T13	2252	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	233639	0	0
T1	453696	964	0	0
T2	18822	41	0	0
T3	16542	241	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	27	0	0
T10	104337	230	0	0
T11	47992	712	0	0
T12	1960	16	0	0
T13	2252	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	233639	0	0
T1	453696	964	0	0
T2	18822	41	0	0
T3	16542	241	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	27	0	0
T10	104337	230	0	0
T11	47992	712	0	0
T12	1960	16	0	0
T13	2252	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	636425	0	0
T1	453696	2330	0	0
T2	18822	42	0	0
T3	16542	256	0	0
T7	13221	22	0	0
T8	1652	15	0	0
T9	17262	27	0	0
T10	104337	267	0	0
T11	47992	1198	0	0
T12	1960	18	0	0
T13	2252	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	233639	0	0
T1	453696	964	0	0
T2	18822	41	0	0
T3	16542	241	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	27	0	0
T10	104337	230	0	0
T11	47992	712	0	0
T12	1960	16	0	0
T13	2252	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	228740	0	0
GntImpliesValid_A	426957799	228740	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	228740	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	2994459	0	0
ReadyAndValidImplyGrant_A	426957799	228740	0	0
ReqAndReadyImplyGrant_A	426957799	228740	0	0
ReqImpliesValid_A	426957799	548113	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	228740	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228740	0	0
T1	453696	970	0	0
T2	18822	43	0	0
T3	16542	246	0	0
T7	13221	15	0	0
T8	1652	6	0	0
T9	17262	32	0	0
T10	104337	208	0	0
T11	47992	793	0	0
T12	1960	15	0	0
T13	2252	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228740	0	0
T1	453696	970	0	0
T2	18822	43	0	0
T3	16542	246	0	0
T7	13221	15	0	0
T8	1652	6	0	0
T9	17262	32	0	0
T10	104337	208	0	0
T11	47992	793	0	0
T12	1960	15	0	0
T13	2252	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228740	0	0
T1	453696	970	0	0
T2	18822	43	0	0
T3	16542	246	0	0
T7	13221	15	0	0
T8	1652	6	0	0
T9	17262	32	0	0
T10	104337	208	0	0
T11	47992	793	0	0
T12	1960	15	0	0
T13	2252	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	2994459	0	0
T1	453696	3114	0	0
T2	18822	322	0	0
T3	16542	235	0	0
T7	13221	117	0	0
T8	1652	7	0	0
T9	17262	284	0	0
T10	104337	1630	0	0
T11	47992	234	0	0
T12	1960	16	0	0
T13	2252	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228740	0	0
T1	453696	970	0	0
T2	18822	43	0	0
T3	16542	246	0	0
T7	13221	15	0	0
T8	1652	6	0	0
T9	17262	32	0	0
T10	104337	208	0	0
T11	47992	793	0	0
T12	1960	15	0	0
T13	2252	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228740	0	0
T1	453696	970	0	0
T2	18822	43	0	0
T3	16542	246	0	0
T7	13221	15	0	0
T8	1652	6	0	0
T9	17262	32	0	0
T10	104337	208	0	0
T11	47992	793	0	0
T12	1960	15	0	0
T13	2252	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	548113	0	0
T1	453696	2444	0	0
T2	18822	61	0	0
T3	16542	258	0	0
T7	13221	26	0	0
T8	1652	6	0	0
T9	17262	32	0	0
T10	104337	244	0	0
T11	47992	1354	0	0
T12	1960	15	0	0
T13	2252	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228740	0	0
T1	453696	970	0	0
T2	18822	43	0	0
T3	16542	246	0	0
T7	13221	15	0	0
T8	1652	6	0	0
T9	17262	32	0	0
T10	104337	208	0	0
T11	47992	793	0	0
T12	1960	15	0	0
T13	2252	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	220977	0	0
GntImpliesValid_A	426957799	220977	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	220977	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	2954830	0	0
ReadyAndValidImplyGrant_A	426957799	220977	0	0
ReqAndReadyImplyGrant_A	426957799	220977	0	0
ReqImpliesValid_A	426957799	544186	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	220977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	220977	0	0
T2	18822	30	0	0
T3	16542	232	0	0
T7	13221	17	0	0
T8	1652	13	0	0
T9	17262	28	0	0
T10	104337	219	0	0
T11	47992	744	0	0
T12	1960	13	0	0
T13	2252	12	0	0
T14	43005	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	220977	0	0
T2	18822	30	0	0
T3	16542	232	0	0
T7	13221	17	0	0
T8	1652	13	0	0
T9	17262	28	0	0
T10	104337	219	0	0
T11	47992	744	0	0
T12	1960	13	0	0
T13	2252	12	0	0
T14	43005	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	220977	0	0
T2	18822	30	0	0
T3	16542	232	0	0
T7	13221	17	0	0
T8	1652	13	0	0
T9	17262	28	0	0
T10	104337	219	0	0
T11	47992	744	0	0
T12	1960	13	0	0
T13	2252	12	0	0
T14	43005	74	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	2954830	0	0
T1	453696	1	0	0
T2	18822	231	0	0
T3	16542	216	0	0
T7	13221	183	0	0
T8	1652	14	0	0
T9	17262	232	0	0
T10	104337	1637	0	0
T11	47992	224	0	0
T12	1960	13	0	0
T13	2252	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	220977	0	0
T2	18822	30	0	0
T3	16542	232	0	0
T7	13221	17	0	0
T8	1652	13	0	0
T9	17262	28	0	0
T10	104337	219	0	0
T11	47992	744	0	0
T12	1960	13	0	0
T13	2252	12	0	0
T14	43005	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	220977	0	0
T2	18822	30	0	0
T3	16542	232	0	0
T7	13221	17	0	0
T8	1652	13	0	0
T9	17262	28	0	0
T10	104337	219	0	0
T11	47992	744	0	0
T12	1960	13	0	0
T13	2252	12	0	0
T14	43005	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	544186	0	0
T2	18822	41	0	0
T3	16542	249	0	0
T7	13221	17	0	0
T8	1652	13	0	0
T9	17262	32	0	0
T10	104337	283	0	0
T11	47992	1266	0	0
T12	1960	14	0	0
T13	2252	16	0	0
T14	43005	76	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	220977	0	0
T2	18822	30	0	0
T3	16542	232	0	0
T7	13221	17	0	0
T8	1652	13	0	0
T9	17262	28	0	0
T10	104337	219	0	0
T11	47992	744	0	0
T12	1960	13	0	0
T13	2252	12	0	0
T14	43005	74	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	223509	0	0
GntImpliesValid_A	426957799	223509	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	223509	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3011970	0	0
ReadyAndValidImplyGrant_A	426957799	223509	0	0
ReqAndReadyImplyGrant_A	426957799	223509	0	0
ReqImpliesValid_A	426957799	518164	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	223509	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223509	0	0
T1	453696	576	0	0
T2	18822	43	0	0
T3	16542	254	0	0
T7	13221	431	0	0
T8	1652	7	0	0
T9	17262	23	0	0
T10	104337	227	0	0
T11	47992	220	0	0
T12	1960	9	0	0
T13	2252	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223509	0	0
T1	453696	576	0	0
T2	18822	43	0	0
T3	16542	254	0	0
T7	13221	431	0	0
T8	1652	7	0	0
T9	17262	23	0	0
T10	104337	227	0	0
T11	47992	220	0	0
T12	1960	9	0	0
T13	2252	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223509	0	0
T1	453696	576	0	0
T2	18822	43	0	0
T3	16542	254	0	0
T7	13221	431	0	0
T8	1652	7	0	0
T9	17262	23	0	0
T10	104337	227	0	0
T11	47992	220	0	0
T12	1960	9	0	0
T13	2252	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3011970	0	0
T1	453696	1916	0	0
T2	18822	274	0	0
T3	16542	243	0	0
T7	13221	879	0	0
T8	1652	8	0	0
T9	17262	207	0	0
T10	104337	1805	0	0
T11	47992	212	0	0
T12	1960	10	0	0
T13	2252	5	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223509	0	0
T1	453696	576	0	0
T2	18822	43	0	0
T3	16542	254	0	0
T7	13221	431	0	0
T8	1652	7	0	0
T9	17262	23	0	0
T10	104337	227	0	0
T11	47992	220	0	0
T12	1960	9	0	0
T13	2252	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223509	0	0
T1	453696	576	0	0
T2	18822	43	0	0
T3	16542	254	0	0
T7	13221	431	0	0
T8	1652	7	0	0
T9	17262	23	0	0
T10	104337	227	0	0
T11	47992	220	0	0
T12	1960	9	0	0
T13	2252	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	518164	0	0
T1	453696	1309	0	0
T2	18822	43	0	0
T3	16542	266	0	0
T7	13221	1734	0	0
T8	1652	7	0	0
T9	17262	23	0	0
T10	104337	273	0	0
T11	47992	230	0	0
T12	1960	9	0	0
T13	2252	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	223509	0	0
T1	453696	576	0	0
T2	18822	43	0	0
T3	16542	254	0	0
T7	13221	431	0	0
T8	1652	7	0	0
T9	17262	23	0	0
T10	104337	227	0	0
T11	47992	220	0	0
T12	1960	9	0	0
T13	2252	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	257666	0	0
GntImpliesValid_A	426957799	257666	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	257666	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3104973	0	0
ReadyAndValidImplyGrant_A	426957799	257666	0	0
ReqAndReadyImplyGrant_A	426957799	257666	0	0
ReqImpliesValid_A	426957799	693663	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	257666	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	257666	0	0
T1	453696	1065	0	0
T2	18822	41	0	0
T3	16542	267	0	0
T7	13221	113	0	0
T8	1652	6	0	0
T9	17262	25	0	0
T10	104337	269	0	0
T11	47992	264	0	0
T12	1960	15	0	0
T13	2252	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	257666	0	0
T1	453696	1065	0	0
T2	18822	41	0	0
T3	16542	267	0	0
T7	13221	113	0	0
T8	1652	6	0	0
T9	17262	25	0	0
T10	104337	269	0	0
T11	47992	264	0	0
T12	1960	15	0	0
T13	2252	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	257666	0	0
T1	453696	1065	0	0
T2	18822	41	0	0
T3	16542	267	0	0
T7	13221	113	0	0
T8	1652	6	0	0
T9	17262	25	0	0
T10	104337	269	0	0
T11	47992	264	0	0
T12	1960	15	0	0
T13	2252	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3104973	0	0
T1	453696	3696	0	0
T2	18822	279	0	0
T3	16542	257	0	0
T7	13221	280	0	0
T8	1652	7	0	0
T9	17262	191	0	0
T10	104337	1902	0	0
T11	47992	260	0	0
T12	1960	16	0	0
T13	2252	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	257666	0	0
T1	453696	1065	0	0
T2	18822	41	0	0
T3	16542	267	0	0
T7	13221	113	0	0
T8	1652	6	0	0
T9	17262	25	0	0
T10	104337	269	0	0
T11	47992	264	0	0
T12	1960	15	0	0
T13	2252	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	257666	0	0
T1	453696	1065	0	0
T2	18822	41	0	0
T3	16542	267	0	0
T7	13221	113	0	0
T8	1652	6	0	0
T9	17262	25	0	0
T10	104337	269	0	0
T11	47992	264	0	0
T12	1960	15	0	0
T13	2252	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	693663	0	0
T1	453696	2345	0	0
T2	18822	57	0	0
T3	16542	278	0	0
T7	13221	910	0	0
T8	1652	6	0	0
T9	17262	25	0	0
T10	104337	313	0	0
T11	47992	270	0	0
T12	1960	15	0	0
T13	2252	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	257666	0	0
T1	453696	1065	0	0
T2	18822	41	0	0
T3	16542	267	0	0
T7	13221	113	0	0
T8	1652	6	0	0
T9	17262	25	0	0
T10	104337	269	0	0
T11	47992	264	0	0
T12	1960	15	0	0
T13	2252	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	231236	0	0
GntImpliesValid_A	426957799	231236	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	231236	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3011745	0	0
ReadyAndValidImplyGrant_A	426957799	231236	0	0
ReqAndReadyImplyGrant_A	426957799	231236	0	0
ReqImpliesValid_A	426957799	633149	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	231236	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	231236	0	0
T2	18822	36	0	0
T3	16542	251	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	203	0	0
T11	47992	622	0	0
T12	1960	11	0	0
T13	2252	15	0	0
T14	43005	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	231236	0	0
T2	18822	36	0	0
T3	16542	251	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	203	0	0
T11	47992	622	0	0
T12	1960	11	0	0
T13	2252	15	0	0
T14	43005	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	231236	0	0
T2	18822	36	0	0
T3	16542	251	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	203	0	0
T11	47992	622	0	0
T12	1960	11	0	0
T13	2252	15	0	0
T14	43005	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3011745	0	0
T1	453696	1	0	0
T2	18822	266	0	0
T3	16542	234	0	0
T7	13221	141	0	0
T8	1652	10	0	0
T9	17262	249	0	0
T10	104337	1490	0	0
T11	47992	232	0	0
T12	1960	12	0	0
T13	2252	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	231236	0	0
T2	18822	36	0	0
T3	16542	251	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	203	0	0
T11	47992	622	0	0
T12	1960	11	0	0
T13	2252	15	0	0
T14	43005	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	231236	0	0
T2	18822	36	0	0
T3	16542	251	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	203	0	0
T11	47992	622	0	0
T12	1960	11	0	0
T13	2252	15	0	0
T14	43005	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	633149	0	0
T2	18822	37	0	0
T3	16542	269	0	0
T7	13221	15	0	0
T8	1652	11	0	0
T9	17262	31	0	0
T10	104337	213	0	0
T11	47992	1014	0	0
T12	1960	11	0	0
T13	2252	17	0	0
T14	43005	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	231236	0	0
T2	18822	36	0	0
T3	16542	251	0	0
T7	13221	15	0	0
T8	1652	10	0	0
T9	17262	31	0	0
T10	104337	203	0	0
T11	47992	622	0	0
T12	1960	11	0	0
T13	2252	15	0	0
T14	43005	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	228941	0	0
GntImpliesValid_A	426957799	228941	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	228941	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3055235	0	0
ReadyAndValidImplyGrant_A	426957799	228941	0	0
ReqAndReadyImplyGrant_A	426957799	228941	0	0
ReqImpliesValid_A	426957799	633765	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	228941	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228941	0	0
T2	18822	35	0	0
T3	16542	252	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	214	0	0
T11	47992	224	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228941	0	0
T2	18822	35	0	0
T3	16542	252	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	214	0	0
T11	47992	224	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228941	0	0
T2	18822	35	0	0
T3	16542	252	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	214	0	0
T11	47992	224	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3055235	0	0
T1	453696	1	0	0
T2	18822	281	0	0
T3	16542	240	0	0
T7	13221	110	0	0
T8	1652	15	0	0
T9	17262	255	0	0
T10	104337	1439	0	0
T11	47992	225	0	0
T12	1960	13	0	0
T13	2252	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228941	0	0
T2	18822	35	0	0
T3	16542	252	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	214	0	0
T11	47992	224	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228941	0	0
T2	18822	35	0	0
T3	16542	252	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	214	0	0
T11	47992	224	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	633765	0	0
T2	18822	38	0	0
T3	16542	265	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	34	0	0
T10	104337	268	0	0
T11	47992	225	0	0
T12	1960	16	0	0
T13	2252	13	0	0
T14	43005	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	228941	0	0
T2	18822	35	0	0
T3	16542	252	0	0
T7	13221	18	0	0
T8	1652	14	0	0
T9	17262	28	0	0
T10	104337	214	0	0
T11	47992	224	0	0
T12	1960	14	0	0
T13	2252	12	0	0
T14	43005	79	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	221583	0	0
GntImpliesValid_A	426957799	221583	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	221583	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3012301	0	0
ReadyAndValidImplyGrant_A	426957799	221583	0	0
ReqAndReadyImplyGrant_A	426957799	221583	0	0
ReqImpliesValid_A	426957799	557527	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	221583	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	221583	0	0
T2	18822	26	0	0
T3	16542	238	0	0
T7	13221	9	0	0
T8	1652	10	0	0
T9	17262	23	0	0
T10	104337	258	0	0
T11	47992	212	0	0
T12	1960	19	0	0
T13	2252	16	0	0
T14	43005	80	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	221583	0	0
T2	18822	26	0	0
T3	16542	238	0	0
T7	13221	9	0	0
T8	1652	10	0	0
T9	17262	23	0	0
T10	104337	258	0	0
T11	47992	212	0	0
T12	1960	19	0	0
T13	2252	16	0	0
T14	43005	80	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	221583	0	0
T2	18822	26	0	0
T3	16542	238	0	0
T7	13221	9	0	0
T8	1652	10	0	0
T9	17262	23	0	0
T10	104337	258	0	0
T11	47992	212	0	0
T12	1960	19	0	0
T13	2252	16	0	0
T14	43005	80	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3012301	0	0
T1	453696	1	0	0
T2	18822	185	0	0
T3	16542	227	0	0
T7	13221	59	0	0
T8	1652	11	0	0
T9	17262	157	0	0
T10	104337	1879	0	0
T11	47992	210	0	0
T12	1960	15	0	0
T13	2252	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	221583	0	0
T2	18822	26	0	0
T3	16542	238	0	0
T7	13221	9	0	0
T8	1652	10	0	0
T9	17262	23	0	0
T10	104337	258	0	0
T11	47992	212	0	0
T12	1960	19	0	0
T13	2252	16	0	0
T14	43005	80	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	221583	0	0
T2	18822	26	0	0
T3	16542	238	0	0
T7	13221	9	0	0
T8	1652	10	0	0
T9	17262	23	0	0
T10	104337	258	0	0
T11	47992	212	0	0
T12	1960	19	0	0
T13	2252	16	0	0
T14	43005	80	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	557527	0	0
T2	18822	73	0	0
T3	16542	250	0	0
T7	13221	9	0	0
T8	1652	10	0	0
T9	17262	30	0	0
T10	104337	360	0	0
T11	47992	216	0	0
T12	1960	24	0	0
T13	2252	17	0	0
T14	43005	80	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	221583	0	0
T2	18822	26	0	0
T3	16542	238	0	0
T7	13221	9	0	0
T8	1652	10	0	0
T9	17262	23	0	0
T10	104337	258	0	0
T11	47992	212	0	0
T12	1960	19	0	0
T13	2252	16	0	0
T14	43005	80	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	226602	0	0
GntImpliesValid_A	426957799	226602	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	226602	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	2974383	0	0
ReadyAndValidImplyGrant_A	426957799	226602	0	0
ReqAndReadyImplyGrant_A	426957799	226602	0	0
ReqImpliesValid_A	426957799	570843	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	226602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226602	0	0
T2	18822	38	0	0
T3	16542	248	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	23	0	0
T10	104337	229	0	0
T11	47992	226	0	0
T12	1960	9	0	0
T13	2252	7	0	0
T14	43005	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226602	0	0
T2	18822	38	0	0
T3	16542	248	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	23	0	0
T10	104337	229	0	0
T11	47992	226	0	0
T12	1960	9	0	0
T13	2252	7	0	0
T14	43005	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226602	0	0
T2	18822	38	0	0
T3	16542	248	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	23	0	0
T10	104337	229	0	0
T11	47992	226	0	0
T12	1960	9	0	0
T13	2252	7	0	0
T14	43005	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	2974383	0	0
T1	453696	1	0	0
T2	18822	336	0	0
T3	16542	233	0	0
T7	13221	100	0	0
T8	1652	14	0	0
T9	17262	194	0	0
T10	104337	1575	0	0
T11	47992	226	0	0
T12	1960	9	0	0
T13	2252	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226602	0	0
T2	18822	38	0	0
T3	16542	248	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	23	0	0
T10	104337	229	0	0
T11	47992	226	0	0
T12	1960	9	0	0
T13	2252	7	0	0
T14	43005	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226602	0	0
T2	18822	38	0	0
T3	16542	248	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	23	0	0
T10	104337	229	0	0
T11	47992	226	0	0
T12	1960	9	0	0
T13	2252	7	0	0
T14	43005	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	570843	0	0
T2	18822	38	0	0
T3	16542	264	0	0
T7	13221	36	0	0
T8	1652	13	0	0
T9	17262	23	0	0
T10	104337	275	0	0
T11	47992	228	0	0
T12	1960	10	0	0
T13	2252	7	0	0
T14	43005	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	226602	0	0
T2	18822	38	0	0
T3	16542	248	0	0
T7	13221	11	0	0
T8	1652	13	0	0
T9	17262	23	0	0
T10	104337	229	0	0
T11	47992	226	0	0
T12	1960	9	0	0
T13	2252	7	0	0
T14	43005	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	217430	0	0
GntImpliesValid_A	426957799	217430	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	217430	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	3055721	0	0
ReadyAndValidImplyGrant_A	426957799	217430	0	0
ReqAndReadyImplyGrant_A	426957799	217430	0	0
ReqImpliesValid_A	426957799	566946	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	0	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	217430	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	217430	0	0
T1	453696	562	0	0
T2	18822	44	0	0
T3	16542	250	0	0
T7	13221	16	0	0
T8	1652	15	0	0
T9	17262	30	0	0
T10	104337	471	0	0
T11	47992	743	0	0
T12	1960	9	0	0
T13	2252	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	217430	0	0
T1	453696	562	0	0
T2	18822	44	0	0
T3	16542	250	0	0
T7	13221	16	0	0
T8	1652	15	0	0
T9	17262	30	0	0
T10	104337	471	0	0
T11	47992	743	0	0
T12	1960	9	0	0
T13	2252	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	217430	0	0
T1	453696	562	0	0
T2	18822	44	0	0
T3	16542	250	0	0
T7	13221	16	0	0
T8	1652	15	0	0
T9	17262	30	0	0
T10	104337	471	0	0
T11	47992	743	0	0
T12	1960	9	0	0
T13	2252	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	3055721	0	0
T1	453696	1908	0	0
T2	18822	363	0	0
T3	16542	236	0	0
T7	13221	125	0	0
T8	1652	14	0	0
T9	17262	221	0	0
T10	104337	2971	0	0
T11	47992	216	0	0
T12	1960	10	0	0
T13	2252	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	217430	0	0
T1	453696	562	0	0
T2	18822	44	0	0
T3	16542	250	0	0
T7	13221	16	0	0
T8	1652	15	0	0
T9	17262	30	0	0
T10	104337	471	0	0
T11	47992	743	0	0
T12	1960	9	0	0
T13	2252	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	217430	0	0
T1	453696	562	0	0
T2	18822	44	0	0
T3	16542	250	0	0
T7	13221	16	0	0
T8	1652	15	0	0
T9	17262	30	0	0
T10	104337	471	0	0
T11	47992	743	0	0
T12	1960	9	0	0
T13	2252	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	566946	0	0
T1	453696	1240	0	0
T2	18822	44	0	0
T3	16542	265	0	0
T7	13221	16	0	0
T8	1652	17	0	0
T9	17262	30	0	0
T10	104337	948	0	0
T11	47992	1272	0	0
T12	1960	9	0	0
T13	2252	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	217430	0	0
T1	453696	562	0	0
T2	18822	44	0	0
T3	16542	250	0	0
T7	13221	16	0	0
T8	1652	15	0	0
T9	17262	30	0	0
T10	104337	471	0	0
T11	47992	743	0	0
T12	1960	9	0	0
T13	2252	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	915939	0	0
GntImpliesValid_A	426957799	915939	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	915939	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	11148087	0	0
ReadyAndValidImplyGrant_A	426957799	915939	0	0
ReqAndReadyImplyGrant_A	426957799	915939	0	0
ReqImpliesValid_A	426957799	2394839	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	20576	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	915939	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915939	0	0
T1	453696	778	0	0
T2	18822	146	0	0
T3	16542	944	0	0
T7	13221	140	0	0
T8	1652	39	0	0
T9	17262	116	0	0
T10	104337	910	0	0
T11	47992	3277	0	0
T12	1960	34	0	0
T13	2252	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915939	0	0
T1	453696	778	0	0
T2	18822	146	0	0
T3	16542	944	0	0
T7	13221	140	0	0
T8	1652	39	0	0
T9	17262	116	0	0
T10	104337	910	0	0
T11	47992	3277	0	0
T12	1960	34	0	0
T13	2252	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915939	0	0
T1	453696	778	0	0
T2	18822	146	0	0
T3	16542	944	0	0
T7	13221	140	0	0
T8	1652	39	0	0
T9	17262	116	0	0
T10	104337	910	0	0
T11	47992	3277	0	0
T12	1960	34	0	0
T13	2252	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	11148087	0	0
T1	453696	2691	0	0
T2	18822	872	0	0
T3	16542	1	0	0
T7	13221	925	0	0
T8	1652	1	0	0
T9	17262	821	0	0
T10	104337	5932	0	0
T11	47992	2	0	0
T12	1960	1	0	0
T13	2252	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915939	0	0
T1	453696	778	0	0
T2	18822	146	0	0
T3	16542	944	0	0
T7	13221	140	0	0
T8	1652	39	0	0
T9	17262	116	0	0
T10	104337	910	0	0
T11	47992	3277	0	0
T12	1960	34	0	0
T13	2252	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915939	0	0
T1	453696	778	0	0
T2	18822	146	0	0
T3	16542	944	0	0
T7	13221	140	0	0
T8	1652	39	0	0
T9	17262	116	0	0
T10	104337	910	0	0
T11	47992	3277	0	0
T12	1960	34	0	0
T13	2252	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	2394839	0	0
T1	453696	953	0	0
T2	18822	177	0	0
T3	16542	944	0	0
T7	13221	293	0	0
T8	1652	39	0	0
T9	17262	130	0	0
T10	104337	1229	0	0
T11	47992	3277	0	0
T12	1960	34	0	0
T13	2252	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	20576	0	900
T3	16542	11	0	1
T7	13221	0	0	1
T8	1652	0	0	1
T9	17262	0	0	1
T10	104337	0	0	1
T11	47992	619	0	1
T12	1960	0	0	1
T13	2252	0	0	1
T14	43005	0	0	1
T15	0	2	0	0
T16	0	43	0	0
T17	0	18	0	0
T18	0	3	0	0
T19	0	289	0	0
T20	0	4	0	0
T21	0	1	0	0
T22	0	1	0	0
T24	1829	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	915939	0	0
T1	453696	778	0	0
T2	18822	146	0	0
T3	16542	944	0	0
T7	13221	140	0	0
T8	1652	39	0	0
T9	17262	116	0	0
T10	104337	910	0	0
T11	47992	3277	0	0
T12	1960	34	0	0
T13	2252	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426957799	426832574	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	426957799	909363	0	0
GntImpliesValid_A	426957799	909363	0	0
GrantKnown_A	426957799	426832574	0	0
IdxKnown_A	426957799	426832574	0	0
IndexIsCorrect_A	426957799	909363	0	0
LockArbDecision_A	426957799	0	0	0
NoReadyValidNoGrant_A	426957799	358238147	0	0
ReadyAndValidImplyGrant_A	426957799	909363	0	0
ReqAndReadyImplyGrant_A	426957799	909363	0	0
ReqImpliesValid_A	426957799	13296671	0	0
ReqStaysHighUntilGranted0_M	426957799	0	0	0
RoundRobin_A	426957799	30974	0	900
ValidKnown_A	426957799	426832574	0	0
gen_data_port_assertion.DataFlow_A	426957799	909363	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	909363	0	0
T1	453696	1591	0	0
T2	18822	135	0	0
T3	16542	1012	0	0
T7	13221	131	0	0
T8	1652	48	0	0
T9	17262	102	0	0
T10	104337	1021	0	0
T11	47992	1815	0	0
T12	1960	44	0	0
T13	2252	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	909363	0	0
T1	453696	1591	0	0
T2	18822	135	0	0
T3	16542	1012	0	0
T7	13221	131	0	0
T8	1652	48	0	0
T9	17262	102	0	0
T10	104337	1021	0	0
T11	47992	1815	0	0
T12	1960	44	0	0
T13	2252	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	909363	0	0
T1	453696	1591	0	0
T2	18822	135	0	0
T3	16542	1012	0	0
T7	13221	131	0	0
T8	1652	48	0	0
T9	17262	102	0	0
T10	104337	1021	0	0
T11	47992	1815	0	0
T12	1960	44	0	0
T13	2252	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	358238147	0	0
T1	453696	377460	0	0
T2	18822	15707	0	0
T3	16542	1	0	0
T7	13221	10347	0	0
T8	1652	1	0	0
T9	17262	14969	0	0
T10	104337	86361	0	0
T11	47992	1	0	0
T12	1960	1	0	0
T13	2252	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	909363	0	0
T1	453696	1591	0	0
T2	18822	135	0	0
T3	16542	1012	0	0
T7	13221	131	0	0
T8	1652	48	0	0
T9	17262	102	0	0
T10	104337	1021	0	0
T11	47992	1815	0	0
T12	1960	44	0	0
T13	2252	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	909363	0	0
T1	453696	1591	0	0
T2	18822	135	0	0
T3	16542	1012	0	0
T7	13221	131	0	0
T8	1652	48	0	0
T9	17262	102	0	0
T10	104337	1021	0	0
T11	47992	1815	0	0
T12	1960	44	0	0
T13	2252	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	13296671	0	0
T1	453696	7330	0	0
T2	18822	1103	0	0
T3	16542	1012	0	0
T7	13221	1132	0	0
T8	1652	48	0	0
T9	17262	804	0	0
T10	104337	8611	0	0
T11	47992	1815	0	0
T12	1960	44	0	0
T13	2252	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	30974	0	900
T1	453696	14	0	1
T2	18822	0	0	1
T3	16542	13	0	1
T7	13221	0	0	1
T8	1652	0	0	1
T9	17262	0	0	1
T10	104337	2	0	1
T11	47992	15	0	1
T12	1960	0	0	1
T13	2252	0	0	1
T15	0	3	0	0
T18	0	3	0	0
T19	0	582	0	0
T20	0	11	0	0
T22	0	1	0	0
T23	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	426832574	0	0
T1	453696	453694	0	0
T2	18822	18779	0	0
T3	16542	16503	0	0
T7	13221	12449	0	0
T8	1652	1636	0	0
T9	17262	17251	0	0
T10	104337	103297	0	0
T11	47992	47967	0	0
T12	1960	1915	0	0
T13	2252	2176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426957799	909363	0	0
T1	453696	1591	0	0
T2	18822	135	0	0
T3	16542	1012	0	0
T7	13221	131	0	0
T8	1652	48	0	0
T9	17262	102	0	0
T10	104337	1021	0	0
T11	47992	1815	0	0
T12	1960	44	0	0
T13	2252	43	0	0