Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1481005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

235731

1

T1

14

T2

13

T3

1331

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	582413	1			T1	62		T2	37		T3	3421
values[0x0]	551832	1			T1	7		T2	30		T3	3278
values[0x1]	582491	1			T1	40		T2	33		T3	3293

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1144560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

572176

1

T1

43

T2

34

T3

3303

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26216	1			T1	2		T3	138		T7	7
valid_sources[0x01]	26786	1			T1	3		T2	2		T3	169
valid_sources[0x02]	26707	1			T1	3		T2	2		T3	176
valid_sources[0x03]	26675	1			T1	1		T2	3		T3	92
valid_sources[0x04]	26473	1			T1	2		T2	2		T3	143
valid_sources[0x05]	26491	1			T1	1		T3	188		T7	16
valid_sources[0x06]	26639	1			T1	1		T2	1		T3	133
valid_sources[0x07]	27227	1			T1	2		T2	3		T3	207
valid_sources[0x08]	26878	1			T3	154		T7	8		T8	3
valid_sources[0x09]	27225	1			T2	1		T3	127		T7	5
valid_sources[0x0a]	27551	1			T1	5		T2	2		T3	174
valid_sources[0x0b]	26679	1			T1	3		T2	2		T3	143
valid_sources[0x0c]	26775	1			T1	1		T3	198		T7	8
valid_sources[0x0d]	26985	1			T1	2		T3	125		T7	13
valid_sources[0x0e]	26820	1			T2	1		T3	186		T7	18
valid_sources[0x0f]	27101	1			T1	1		T2	5		T3	135
valid_sources[0x10]	27301	1			T2	1		T3	175		T7	15
valid_sources[0x11]	26010	1			T2	4		T3	144		T7	25
valid_sources[0x12]	27060	1			T2	2		T3	88		T7	23
valid_sources[0x13]	26498	1			T2	1		T3	129		T7	19
valid_sources[0x14]	26695	1			T2	1		T3	137		T7	9
valid_sources[0x15]	26786	1			T1	1		T2	2		T3	163
valid_sources[0x16]	27327	1			T3	145		T7	8		T8	1
valid_sources[0x17]	27470	1			T1	2		T2	2		T3	147
valid_sources[0x18]	26559	1			T2	1		T3	179		T7	17
valid_sources[0x19]	26565	1			T2	2		T3	194		T7	18
valid_sources[0x1a]	26748	1			T1	1		T2	1		T3	173
valid_sources[0x1b]	26636	1			T1	2		T2	1		T3	135
valid_sources[0x1c]	26492	1			T2	4		T3	148		T7	19
valid_sources[0x1d]	27489	1			T1	4		T2	3		T3	156
valid_sources[0x1e]	26109	1			T2	1		T3	223		T7	22
valid_sources[0x1f]	26094	1			T2	1		T3	189		T7	15
valid_sources[0x20]	27367	1			T1	2		T2	3		T3	159

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24769

1

T1

7

T2

3

T3

128

values[0x0]

all_enables

biggest_size

186284

1

T1

4

T2

9

T3

1077

values[0x1]

all_enables

biggest_size

24678

1

T1

3

T2

1

T3

126

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1492361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242631

1

T1

9

T2

19

T3

1446

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	594527	1			T1	55		T2	48		T3	3339
values[0x0]	546176	1			T1	4		T2	41		T3	3207
values[0x1]	594289	1			T1	56		T2	54		T3	3310

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1145350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

589642

1

T1

32

T2

51

T3

3435

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27082	1			T1	1		T3	175		T7	22
valid_sources[0x01]	27665	1			T1	3		T2	4		T3	118
valid_sources[0x02]	27059	1			T1	6		T2	4		T3	188
valid_sources[0x03]	26498	1			T2	3		T3	125		T7	20
valid_sources[0x04]	26473	1			T1	2		T3	167		T7	34
valid_sources[0x05]	26694	1			T3	159		T7	11		T8	1
valid_sources[0x06]	27131	1			T1	1		T3	163		T7	18
valid_sources[0x07]	26472	1			T3	151		T7	11		T9	1
valid_sources[0x08]	27417	1			T2	1		T3	152		T7	9
valid_sources[0x09]	27352	1			T1	2		T3	126		T7	23
valid_sources[0x0a]	27364	1			T2	5		T3	154		T7	14
valid_sources[0x0b]	27467	1			T1	1		T2	3		T3	166
valid_sources[0x0c]	26652	1			T1	1		T3	133		T7	12
valid_sources[0x0d]	26517	1			T1	2		T2	8		T3	181
valid_sources[0x0e]	27101	1			T1	3		T2	4		T3	166
valid_sources[0x0f]	27163	1			T3	133		T7	21		T8	1
valid_sources[0x10]	27005	1			T1	2		T2	11		T3	133
valid_sources[0x11]	26894	1			T1	4		T3	145		T7	27
valid_sources[0x12]	27079	1			T3	150		T7	21		T9	2
valid_sources[0x13]	26544	1			T1	1		T2	5		T3	130
valid_sources[0x14]	27529	1			T3	143		T7	20		T9	1
valid_sources[0x15]	26658	1			T1	1		T2	6		T3	162
valid_sources[0x16]	27363	1			T1	3		T2	12		T3	136
valid_sources[0x17]	27680	1			T1	1		T2	4		T3	201
valid_sources[0x18]	26432	1			T1	11		T2	1		T3	123
valid_sources[0x19]	27852	1			T1	1		T3	170		T7	25
valid_sources[0x1a]	27298	1			T1	7		T2	6		T3	166
valid_sources[0x1b]	27144	1			T3	135		T7	19		T8	2
valid_sources[0x1c]	26301	1			T2	4		T3	126		T7	16
valid_sources[0x1d]	27926	1			T1	4		T3	180		T7	18
valid_sources[0x1e]	27790	1			T2	2		T3	184		T7	7
valid_sources[0x1f]	26485	1			T2	3		T3	202		T7	50
valid_sources[0x20]	27608	1			T1	1		T3	151		T7	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25608

1

T1

5

T2

3

T3

130

values[0x0]

all_enables

biggest_size

191498

1

T1

1

T2

16

T3

1178

values[0x1]

all_enables

biggest_size

25525

1

T1

3

T3

138

T7

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1492240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238182

1

T1

14

T2

18

T3

1452

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	588044	1			T1	61		T2	37		T3	3446
values[0x0]	555690	1			T1	9		T2	46		T3	3416
values[0x1]	586688	1			T1	44		T2	46		T3	3427

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1152778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

577644

1

T1

48

T2

37

T3

3439

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27553	1			T1	3		T2	5		T3	160
valid_sources[0x01]	27049	1			T1	1		T3	157		T7	14
valid_sources[0x02]	27291	1			T2	5		T3	221		T7	8
valid_sources[0x03]	27052	1			T1	1		T2	10		T3	127
valid_sources[0x04]	26226	1			T1	3		T3	144		T7	22
valid_sources[0x05]	26932	1			T1	3		T2	2		T3	195
valid_sources[0x06]	27204	1			T1	3		T2	6		T3	160
valid_sources[0x07]	27325	1			T1	1		T2	1		T3	162
valid_sources[0x08]	27144	1			T1	1		T2	2		T3	136
valid_sources[0x09]	27151	1			T1	2		T2	3		T3	163
valid_sources[0x0a]	27352	1			T1	2		T2	1		T3	159
valid_sources[0x0b]	27296	1			T1	3		T2	1		T3	215
valid_sources[0x0c]	27097	1			T1	4		T3	120		T7	8
valid_sources[0x0d]	26254	1			T3	171		T7	15		T8	2
valid_sources[0x0e]	27116	1			T1	2		T3	193		T7	20
valid_sources[0x0f]	26346	1			T1	2		T3	121		T7	14
valid_sources[0x10]	27049	1			T1	3		T3	123		T7	21
valid_sources[0x11]	26091	1			T1	2		T2	1		T3	145
valid_sources[0x12]	26975	1			T1	1		T3	160		T7	20
valid_sources[0x13]	27958	1			T1	2		T3	178		T7	9
valid_sources[0x14]	27968	1			T1	5		T2	6		T3	191
valid_sources[0x15]	26541	1			T1	2		T3	127		T7	15
valid_sources[0x16]	26877	1			T1	2		T3	144		T7	10
valid_sources[0x17]	28133	1			T1	3		T3	195		T7	18
valid_sources[0x18]	27770	1			T1	1		T2	4		T3	136
valid_sources[0x19]	26896	1			T1	2		T2	11		T3	178
valid_sources[0x1a]	27165	1			T1	1		T2	5		T3	209
valid_sources[0x1b]	26372	1			T1	2		T2	1		T3	136
valid_sources[0x1c]	26349	1			T3	146		T7	13		T8	3
valid_sources[0x1d]	27493	1			T1	3		T3	178		T7	11
valid_sources[0x1e]	26388	1			T1	2		T3	172		T7	20
valid_sources[0x1f]	26927	1			T1	1		T2	8		T3	213
valid_sources[0x20]	27104	1			T1	1		T3	132		T7	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25091

1

T1

7

T2

3

T3

157

values[0x0]

all_enables

biggest_size

187759

1

T1

5

T2

14

T3

1141

values[0x1]

all_enables

biggest_size

25332

1

T1

2

T2

1

T3

154