Line Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_async ( parameter Width=107,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_async ( parameter Width=64,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_async
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
65082 |
64614 |
0 |
0 |
T2 |
26207 |
25894 |
0 |
0 |
T3 |
1767302 |
1766362 |
0 |
0 |
T7 |
2076676 |
2076664 |
0 |
0 |
T8 |
485515 |
485176 |
0 |
0 |
T9 |
65387 |
64985 |
0 |
0 |
T10 |
232502 |
223244 |
0 |
0 |
T11 |
1595572 |
1595487 |
0 |
0 |
T12 |
20411 |
20039 |
0 |
0 |
T13 |
668647 |
668309 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
65082 |
64614 |
0 |
0 |
T2 |
26207 |
25894 |
0 |
0 |
T3 |
1767302 |
1766362 |
0 |
0 |
T7 |
2076676 |
2076664 |
0 |
0 |
T8 |
485515 |
485176 |
0 |
0 |
T9 |
65387 |
64985 |
0 |
0 |
T10 |
232502 |
223244 |
0 |
0 |
T11 |
1595572 |
1595487 |
0 |
0 |
T12 |
20411 |
20039 |
0 |
0 |
T13 |
668647 |
668309 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7200 |
7200 |
0 |
0 |
T1 |
8 |
8 |
0 |
0 |
T2 |
8 |
8 |
0 |
0 |
T3 |
8 |
8 |
0 |
0 |
T7 |
8 |
8 |
0 |
0 |
T8 |
8 |
8 |
0 |
0 |
T9 |
8 |
8 |
0 |
0 |
T10 |
8 |
8 |
0 |
0 |
T11 |
8 |
8 |
0 |
0 |
T12 |
8 |
8 |
0 |
0 |
T13 |
8 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_35.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_35.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
572301612 |
572167788 |
0 |
0 |
T1 |
4005 |
3976 |
0 |
0 |
T2 |
5971 |
5900 |
0 |
0 |
T3 |
143752 |
143674 |
0 |
0 |
T7 |
214679 |
214678 |
0 |
0 |
T8 |
22006 |
21990 |
0 |
0 |
T9 |
3986 |
3962 |
0 |
0 |
T10 |
38495 |
36961 |
0 |
0 |
T11 |
131208 |
131201 |
0 |
0 |
T12 |
3865 |
3795 |
0 |
0 |
T13 |
108428 |
108374 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_37.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_37.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
617358164 |
617226639 |
0 |
0 |
T1 |
5117 |
5080 |
0 |
0 |
T2 |
4420 |
4367 |
0 |
0 |
T3 |
405878 |
405664 |
0 |
0 |
T7 |
130239 |
130238 |
0 |
0 |
T8 |
61894 |
61851 |
0 |
0 |
T9 |
7335 |
7290 |
0 |
0 |
T10 |
14243 |
13669 |
0 |
0 |
T11 |
134453 |
134446 |
0 |
0 |
T12 |
1486 |
1459 |
0 |
0 |
T13 |
18071 |
18061 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_39.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_39.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
558337532 |
558203406 |
0 |
0 |
T1 |
7898 |
7841 |
0 |
0 |
T2 |
4187 |
4138 |
0 |
0 |
T3 |
67648 |
67610 |
0 |
0 |
T7 |
701294 |
701290 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
8771 |
8717 |
0 |
0 |
T10 |
38110 |
36596 |
0 |
0 |
T11 |
599362 |
599330 |
0 |
0 |
T12 |
4410 |
4330 |
0 |
0 |
T13 |
62645 |
62614 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Total | Covered | Percent |
Conditions | 14 | 13 | 92.86 |
Logical | 14 | 13 | 92.86 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_41.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_41.rspfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
557958554 |
557826219 |
0 |
0 |
T1 |
4450 |
4417 |
0 |
0 |
T2 |
6049 |
5977 |
0 |
0 |
T3 |
67648 |
67610 |
0 |
0 |
T7 |
457984 |
457982 |
0 |
0 |
T8 |
50890 |
50855 |
0 |
0 |
T9 |
7655 |
7608 |
0 |
0 |
T10 |
12318 |
11822 |
0 |
0 |
T11 |
134453 |
134446 |
0 |
0 |
T12 |
3914 |
3843 |
0 |
0 |
T13 |
12047 |
12040 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_35.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_35.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
572301612 |
572167788 |
0 |
0 |
T1 |
4005 |
3976 |
0 |
0 |
T2 |
5971 |
5900 |
0 |
0 |
T3 |
143752 |
143674 |
0 |
0 |
T7 |
214679 |
214678 |
0 |
0 |
T8 |
22006 |
21990 |
0 |
0 |
T9 |
3986 |
3962 |
0 |
0 |
T10 |
38495 |
36961 |
0 |
0 |
T11 |
131208 |
131201 |
0 |
0 |
T12 |
3865 |
3795 |
0 |
0 |
T13 |
108428 |
108374 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_37.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_37.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
617358164 |
617226639 |
0 |
0 |
T1 |
5117 |
5080 |
0 |
0 |
T2 |
4420 |
4367 |
0 |
0 |
T3 |
405878 |
405664 |
0 |
0 |
T7 |
130239 |
130238 |
0 |
0 |
T8 |
61894 |
61851 |
0 |
0 |
T9 |
7335 |
7290 |
0 |
0 |
T10 |
14243 |
13669 |
0 |
0 |
T11 |
134453 |
134446 |
0 |
0 |
T12 |
1486 |
1459 |
0 |
0 |
T13 |
18071 |
18061 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_39.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_39.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
558337532 |
558203406 |
0 |
0 |
T1 |
7898 |
7841 |
0 |
0 |
T2 |
4187 |
4138 |
0 |
0 |
T3 |
67648 |
67610 |
0 |
0 |
T7 |
701294 |
701290 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
8771 |
8717 |
0 |
0 |
T10 |
38110 |
36596 |
0 |
0 |
T11 |
599362 |
599330 |
0 |
0 |
T12 |
4410 |
4330 |
0 |
0 |
T13 |
62645 |
62614 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
ALWAYS | 59 | 4 | 4 | 100.00 |
ALWAYS | 68 | 4 | 4 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
ALWAYS | 92 | 4 | 4 | 100.00 |
ALWAYS | 101 | 4 | 4 | 100.00 |
ALWAYS | 117 | 3 | 3 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
ALWAYS | 192 | 2 | 2 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 287 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
53 |
1 |
1 |
56 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
|
|
|
MISSING_ELSE |
86 |
1 |
1 |
89 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
|
|
|
MISSING_ELSE |
197 |
1 |
1 |
211 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
287 |
1 |
1 |
288 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Total | Covered | Percent |
Conditions | 14 | 14 | 100.00 |
Logical | 14 | 14 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (rvalid_o ? rdata_int : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_asf_41.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
18 |
18 |
100.00 |
TERNARY |
211 |
2 |
2 |
100.00 |
IF |
59 |
3 |
3 |
100.00 |
IF |
68 |
3 |
3 |
100.00 |
IF |
92 |
3 |
3 |
100.00 |
IF |
101 |
3 |
3 |
100.00 |
IF |
117 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 211 (rvalid_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 59 if ((!rst_wr_ni))
-2-: 61 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 68 if ((!rst_wr_ni))
-2-: 70 if (fifo_incr_wptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 if ((!rst_rd_ni))
-2-: 94 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_rd_ni))
-2-: 103 if (fifo_incr_rptr)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 117 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if (fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_asf_41.reqfifo
Assertion Details
GrayRptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
557958554 |
557826219 |
0 |
0 |
T1 |
4450 |
4417 |
0 |
0 |
T2 |
6049 |
5977 |
0 |
0 |
T3 |
67648 |
67610 |
0 |
0 |
T7 |
457984 |
457982 |
0 |
0 |
T8 |
50890 |
50855 |
0 |
0 |
T9 |
7655 |
7608 |
0 |
0 |
T10 |
12318 |
11822 |
0 |
0 |
T11 |
134453 |
134446 |
0 |
0 |
T12 |
3914 |
3843 |
0 |
0 |
T13 |
12047 |
12040 |
0 |
0 |
GrayWptr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455996258 |
0 |
0 |
T1 |
10903 |
10825 |
0 |
0 |
T2 |
1395 |
1378 |
0 |
0 |
T3 |
270594 |
270451 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70096 |
0 |
0 |
T9 |
9410 |
9352 |
0 |
0 |
T10 |
32334 |
31049 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1653 |
0 |
0 |
T13 |
116864 |
116805 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |