Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
283932 |
0 |
0 |
T1 |
10903 |
51 |
0 |
0 |
T2 |
1395 |
5 |
0 |
0 |
T3 |
270594 |
185 |
0 |
0 |
T7 |
143120 |
371 |
0 |
0 |
T8 |
70145 |
90 |
0 |
0 |
T9 |
9410 |
84 |
0 |
0 |
T10 |
32334 |
57 |
0 |
0 |
T11 |
149024 |
815 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
125 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4158058 |
0 |
0 |
T1 |
10903 |
50 |
0 |
0 |
T2 |
1395 |
5 |
0 |
0 |
T3 |
270594 |
429 |
0 |
0 |
T7 |
143120 |
13272 |
0 |
0 |
T8 |
70145 |
671 |
0 |
0 |
T9 |
9410 |
74 |
0 |
0 |
T10 |
32334 |
83 |
0 |
0 |
T11 |
149024 |
3000 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
258 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
358254 |
0 |
0 |
T1 |
10903 |
58 |
0 |
0 |
T2 |
1395 |
5 |
0 |
0 |
T3 |
270594 |
248 |
0 |
0 |
T7 |
143120 |
307 |
0 |
0 |
T8 |
70145 |
124 |
0 |
0 |
T9 |
9410 |
55 |
0 |
0 |
T10 |
32334 |
56 |
0 |
0 |
T11 |
149024 |
988 |
0 |
0 |
T12 |
1684 |
9 |
0 |
0 |
T13 |
116864 |
206 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
837678 |
0 |
0 |
T1 |
10903 |
56 |
0 |
0 |
T2 |
1395 |
5 |
0 |
0 |
T3 |
270594 |
211 |
0 |
0 |
T7 |
143120 |
331 |
0 |
0 |
T8 |
70145 |
76 |
0 |
0 |
T9 |
9410 |
53 |
0 |
0 |
T10 |
32334 |
38 |
0 |
0 |
T11 |
149024 |
146 |
0 |
0 |
T12 |
1684 |
9 |
0 |
0 |
T13 |
116864 |
190 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3346138 |
0 |
0 |
T1 |
10903 |
99 |
0 |
0 |
T2 |
1395 |
10 |
0 |
0 |
T3 |
270594 |
3483 |
0 |
0 |
T7 |
143120 |
26551 |
0 |
0 |
T8 |
70145 |
1193 |
0 |
0 |
T9 |
9410 |
149 |
0 |
0 |
T10 |
32334 |
410 |
0 |
0 |
T11 |
149024 |
35736 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
1606 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3346138 |
0 |
0 |
T1 |
10903 |
99 |
0 |
0 |
T2 |
1395 |
10 |
0 |
0 |
T3 |
270594 |
3483 |
0 |
0 |
T7 |
143120 |
26551 |
0 |
0 |
T8 |
70145 |
1193 |
0 |
0 |
T9 |
9410 |
149 |
0 |
0 |
T10 |
32334 |
410 |
0 |
0 |
T11 |
149024 |
35736 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
1606 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4749678 |
0 |
0 |
T1 |
10903 |
99 |
0 |
0 |
T2 |
1395 |
10 |
0 |
0 |
T3 |
270594 |
714 |
0 |
0 |
T7 |
143120 |
15844 |
0 |
0 |
T8 |
70145 |
711 |
0 |
0 |
T9 |
9410 |
149 |
0 |
0 |
T10 |
32334 |
144 |
0 |
0 |
T11 |
149024 |
5510 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
442 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4749678 |
0 |
0 |
T1 |
10903 |
99 |
0 |
0 |
T2 |
1395 |
10 |
0 |
0 |
T3 |
270594 |
714 |
0 |
0 |
T7 |
143120 |
15844 |
0 |
0 |
T8 |
70145 |
711 |
0 |
0 |
T9 |
9410 |
149 |
0 |
0 |
T10 |
32334 |
144 |
0 |
0 |
T11 |
149024 |
5510 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
442 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
272364 |
0 |
0 |
T1 |
10903 |
52 |
0 |
0 |
T2 |
1395 |
8 |
0 |
0 |
T3 |
270594 |
274 |
0 |
0 |
T7 |
143120 |
711 |
0 |
0 |
T8 |
70145 |
77 |
0 |
0 |
T9 |
9410 |
85 |
0 |
0 |
T10 |
32334 |
32 |
0 |
0 |
T11 |
149024 |
1400 |
0 |
0 |
T12 |
1684 |
3 |
0 |
0 |
T13 |
116864 |
140 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3973638 |
0 |
0 |
T1 |
10903 |
51 |
0 |
0 |
T2 |
1395 |
6 |
0 |
0 |
T3 |
270594 |
469 |
0 |
0 |
T7 |
143120 |
15808 |
0 |
0 |
T8 |
70145 |
607 |
0 |
0 |
T9 |
9410 |
78 |
0 |
0 |
T10 |
32334 |
104 |
0 |
0 |
T11 |
149024 |
4048 |
0 |
0 |
T12 |
1684 |
3 |
0 |
0 |
T13 |
116864 |
262 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
364297 |
0 |
0 |
T1 |
10903 |
48 |
0 |
0 |
T2 |
1395 |
4 |
0 |
0 |
T3 |
270594 |
309 |
0 |
0 |
T7 |
143120 |
1118 |
0 |
0 |
T8 |
70145 |
153 |
0 |
0 |
T9 |
9410 |
74 |
0 |
0 |
T10 |
32334 |
30 |
0 |
0 |
T11 |
149024 |
1929 |
0 |
0 |
T12 |
1684 |
4 |
0 |
0 |
T13 |
116864 |
143 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
776040 |
0 |
0 |
T1 |
10903 |
48 |
0 |
0 |
T2 |
1395 |
4 |
0 |
0 |
T3 |
270594 |
245 |
0 |
0 |
T7 |
143120 |
36 |
0 |
0 |
T8 |
70145 |
104 |
0 |
0 |
T9 |
9410 |
71 |
0 |
0 |
T10 |
32334 |
40 |
0 |
0 |
T11 |
149024 |
1462 |
0 |
0 |
T12 |
1684 |
4 |
0 |
0 |
T13 |
116864 |
180 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3534036 |
0 |
0 |
T1 |
10903 |
98 |
0 |
0 |
T2 |
1395 |
8 |
0 |
0 |
T3 |
270594 |
3170 |
0 |
0 |
T7 |
143120 |
27754 |
0 |
0 |
T8 |
70145 |
1271 |
0 |
0 |
T9 |
9410 |
126 |
0 |
0 |
T10 |
32334 |
419 |
0 |
0 |
T11 |
149024 |
41748 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
1895 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3534036 |
0 |
0 |
T1 |
10903 |
98 |
0 |
0 |
T2 |
1395 |
8 |
0 |
0 |
T3 |
270594 |
3170 |
0 |
0 |
T7 |
143120 |
27754 |
0 |
0 |
T8 |
70145 |
1271 |
0 |
0 |
T9 |
9410 |
126 |
0 |
0 |
T10 |
32334 |
419 |
0 |
0 |
T11 |
149024 |
41748 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
1895 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3758179 |
0 |
0 |
T1 |
10903 |
98 |
0 |
0 |
T2 |
1395 |
8 |
0 |
0 |
T3 |
270594 |
773 |
0 |
0 |
T7 |
143120 |
12991 |
0 |
0 |
T8 |
70145 |
649 |
0 |
0 |
T9 |
9410 |
126 |
0 |
0 |
T10 |
32334 |
73 |
0 |
0 |
T11 |
149024 |
4213 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
503 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3758179 |
0 |
0 |
T1 |
10903 |
98 |
0 |
0 |
T2 |
1395 |
8 |
0 |
0 |
T3 |
270594 |
773 |
0 |
0 |
T7 |
143120 |
12991 |
0 |
0 |
T8 |
70145 |
649 |
0 |
0 |
T9 |
9410 |
126 |
0 |
0 |
T10 |
32334 |
73 |
0 |
0 |
T11 |
149024 |
4213 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
503 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
303384 |
0 |
0 |
T1 |
10903 |
48 |
0 |
0 |
T2 |
1395 |
5 |
0 |
0 |
T3 |
270594 |
224 |
0 |
0 |
T7 |
143120 |
183 |
0 |
0 |
T8 |
70145 |
120 |
0 |
0 |
T9 |
9410 |
74 |
0 |
0 |
T10 |
32334 |
25 |
0 |
0 |
T11 |
149024 |
1178 |
0 |
0 |
T12 |
1684 |
6 |
0 |
0 |
T13 |
116864 |
147 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3135526 |
0 |
0 |
T1 |
10903 |
41 |
0 |
0 |
T2 |
1395 |
4 |
0 |
0 |
T3 |
270594 |
543 |
0 |
0 |
T7 |
143120 |
12566 |
0 |
0 |
T8 |
70145 |
557 |
0 |
0 |
T9 |
9410 |
68 |
0 |
0 |
T10 |
32334 |
37 |
0 |
0 |
T11 |
149024 |
3898 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
271 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |