Unified Coverage Report :: Module Instance :: tb.dut.u_sm1_52.u_devicefifo.reqfifo

Module Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3481979	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	3481979	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3481979	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	7697	0	0
T7	143120	21979	0	0
T8	70145	1397	0	0
T9	9410	132	0	0
T10	32334	499	0	0
T11	149024	42409	0	0
T12	1684	18	0	0
T13	116864	1657	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3481979	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	7697	0	0
T7	143120	21979	0	0
T8	70145	1397	0	0
T9	9410	132	0	0
T10	32334	499	0	0
T11	149024	42409	0	0
T12	1684	18	0	0
T13	116864	1657	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	4012921	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	4012921	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4012921	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	1778	0	0
T7	143120	10730	0	0
T8	70145	784	0	0
T9	9410	132	0	0
T10	32334	118	0	0
T11	149024	3819	0	0
T12	1684	18	0	0
T13	116864	511	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4012921	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	1778	0	0
T7	143120	10730	0	0
T8	70145	784	0	0
T9	9410	132	0	0
T10	32334	118	0	0
T11	149024	3819	0	0
T12	1684	18	0	0
T13	116864	511	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	266661	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	266661	0	0
T1	10903	69	0	0
T2	1395	2	0	0
T3	270594	3254	0	0
T7	143120	29	0	0
T8	70145	132	0	0
T9	9410	60	0	0
T10	32334	48	0	0
T11	149024	307	0	0
T12	1684	12	0	0
T13	116864	144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3301607	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3301607	0	0
T1	10903	62	0	0
T2	1395	2	0	0
T3	270594	1212	0	0
T7	143120	10082	0	0
T8	70145	668	0	0
T9	9410	59	0	0
T10	32334	80	0	0
T11	149024	3767	0	0
T12	1684	11	0	0
T13	116864	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	366194	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	366194	0	0
T1	10903	52	0	0
T2	1395	9	0	0
T3	270594	4496	0	0
T7	143120	1213	0	0
T8	70145	173	0	0
T9	9410	75	0	0
T10	32334	21	0	0
T11	149024	1533	0	0
T12	1684	7	0	0
T13	116864	132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	711314	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	711314	0	0
T1	10903	51	0	0
T2	1395	9	0	0
T3	270594	566	0	0
T7	143120	648	0	0
T8	70145	116	0	0
T9	9410	73	0	0
T10	32334	38	0	0
T11	149024	52	0	0
T12	1684	7	0	0
T13	116864	147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3438986	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	3438986	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3438986	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	6822	0	0
T7	143120	24001	0	0
T8	70145	1486	0	0
T9	9410	153	0	0
T10	32334	366	0	0
T11	149024	43916	0	0
T12	1684	18	0	0
T13	116864	1723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3438986	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	6822	0	0
T7	143120	24001	0	0
T8	70145	1486	0	0
T9	9410	153	0	0
T10	32334	366	0	0
T11	149024	43916	0	0
T12	1684	18	0	0
T13	116864	1723	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	4452229	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	4452229	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4452229	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	1448	0	0
T7	143120	9919	0	0
T8	70145	766	0	0
T9	9410	153	0	0
T10	32334	80	0	0
T11	149024	3543	0	0
T12	1684	18	0	0
T13	116864	419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4452229	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	1448	0	0
T7	143120	9919	0	0
T8	70145	766	0	0
T9	9410	153	0	0
T10	32334	80	0	0
T11	149024	3543	0	0
T12	1684	18	0	0
T13	116864	419	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	268206	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	268206	0	0
T1	10903	59	0	0
T2	1395	3	0	0
T3	270594	670	0	0
T7	143120	32	0	0
T8	70145	109	0	0
T9	9410	79	0	0
T10	32334	27	0	0
T11	149024	328	0	0
T12	1684	5	0	0
T13	116864	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3696957	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3696957	0	0
T1	10903	55	0	0
T2	1395	3	0	0
T3	270594	800	0	0
T7	143120	9883	0	0
T8	70145	654	0	0
T9	9410	73	0	0
T10	32334	53	0	0
T11	149024	2970	0	0
T12	1684	5	0	0
T13	116864	272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	345764	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	345764	0	0
T1	10903	55	0	0
T2	1395	11	0	0
T3	270594	946	0	0
T7	143120	356	0	0
T8	70145	191	0	0
T9	9410	81	0	0
T10	32334	27	0	0
T11	149024	1069	0	0
T12	1684	13	0	0
T13	116864	163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	755272	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	755272	0	0
T1	10903	55	0	0
T2	1395	11	0	0
T3	270594	648	0	0
T7	143120	36	0	0
T8	70145	112	0	0
T9	9410	80	0	0
T10	32334	27	0	0
T11	149024	573	0	0
T12	1684	13	0	0
T13	116864	147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3383468	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	3383468	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3383468	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	9549	0	0
T7	143120	31255	0	0
T8	70145	1325	0	0
T9	9410	134	0	0
T10	32334	2429	0	0
T11	149024	42318	0	0
T12	1684	15	0	0
T13	116864	2075	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3383468	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	9549	0	0
T7	143120	31255	0	0
T8	70145	1325	0	0
T9	9410	134	0	0
T10	32334	2429	0	0
T11	149024	42318	0	0
T12	1684	15	0	0
T13	116864	2075	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	5177505	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	5177505	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	5177505	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	2648	0	0
T7	143120	18083	0	0
T8	70145	656	0	0
T9	9410	134	0	0
T10	32334	724	0	0
T11	149024	3529	0	0
T12	1684	15	0	0
T13	116864	471	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	5177505	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	2648	0	0
T7	143120	18083	0	0
T8	70145	656	0	0
T9	9410	134	0	0
T10	32334	724	0	0
T11	149024	3529	0	0
T12	1684	15	0	0
T13	116864	471	0	0