Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
271164 |
0 |
0 |
T1 |
10903 |
59 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
865 |
0 |
0 |
T7 |
143120 |
464 |
0 |
0 |
T8 |
70145 |
109 |
0 |
0 |
T9 |
9410 |
78 |
0 |
0 |
T10 |
32334 |
242 |
0 |
0 |
T11 |
149024 |
970 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
131 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4327991 |
0 |
0 |
T1 |
10903 |
56 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
1166 |
0 |
0 |
T7 |
143120 |
17991 |
0 |
0 |
T8 |
70145 |
546 |
0 |
0 |
T9 |
9410 |
65 |
0 |
0 |
T10 |
32334 |
482 |
0 |
0 |
T11 |
149024 |
3451 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
262 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
371348 |
0 |
0 |
T1 |
10903 |
68 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
2129 |
0 |
0 |
T7 |
143120 |
510 |
0 |
0 |
T8 |
70145 |
105 |
0 |
0 |
T9 |
9410 |
69 |
0 |
0 |
T10 |
32334 |
439 |
0 |
0 |
T11 |
149024 |
1804 |
0 |
0 |
T12 |
1684 |
10 |
0 |
0 |
T13 |
116864 |
228 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
849514 |
0 |
0 |
T1 |
10903 |
68 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
1482 |
0 |
0 |
T7 |
143120 |
92 |
0 |
0 |
T8 |
70145 |
110 |
0 |
0 |
T9 |
9410 |
69 |
0 |
0 |
T10 |
32334 |
242 |
0 |
0 |
T11 |
149024 |
78 |
0 |
0 |
T12 |
1684 |
10 |
0 |
0 |
T13 |
116864 |
209 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3440621 |
0 |
0 |
T1 |
10903 |
112 |
0 |
0 |
T2 |
1395 |
12 |
0 |
0 |
T3 |
270594 |
7540 |
0 |
0 |
T7 |
143120 |
25520 |
0 |
0 |
T8 |
70145 |
1387 |
0 |
0 |
T9 |
9410 |
155 |
0 |
0 |
T10 |
32334 |
274 |
0 |
0 |
T11 |
149024 |
41392 |
0 |
0 |
T12 |
1684 |
11 |
0 |
0 |
T13 |
116864 |
1869 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3440621 |
0 |
0 |
T1 |
10903 |
112 |
0 |
0 |
T2 |
1395 |
12 |
0 |
0 |
T3 |
270594 |
7540 |
0 |
0 |
T7 |
143120 |
25520 |
0 |
0 |
T8 |
70145 |
1387 |
0 |
0 |
T9 |
9410 |
155 |
0 |
0 |
T10 |
32334 |
274 |
0 |
0 |
T11 |
149024 |
41392 |
0 |
0 |
T12 |
1684 |
11 |
0 |
0 |
T13 |
116864 |
1869 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4158818 |
0 |
0 |
T1 |
10903 |
112 |
0 |
0 |
T2 |
1395 |
12 |
0 |
0 |
T3 |
270594 |
1797 |
0 |
0 |
T7 |
143120 |
9867 |
0 |
0 |
T8 |
70145 |
966 |
0 |
0 |
T9 |
9410 |
155 |
0 |
0 |
T10 |
32334 |
62 |
0 |
0 |
T11 |
149024 |
2675 |
0 |
0 |
T12 |
1684 |
11 |
0 |
0 |
T13 |
116864 |
495 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4158818 |
0 |
0 |
T1 |
10903 |
112 |
0 |
0 |
T2 |
1395 |
12 |
0 |
0 |
T3 |
270594 |
1797 |
0 |
0 |
T7 |
143120 |
9867 |
0 |
0 |
T8 |
70145 |
966 |
0 |
0 |
T9 |
9410 |
155 |
0 |
0 |
T10 |
32334 |
62 |
0 |
0 |
T11 |
149024 |
2675 |
0 |
0 |
T12 |
1684 |
11 |
0 |
0 |
T13 |
116864 |
495 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
283194 |
0 |
0 |
T1 |
10903 |
69 |
0 |
0 |
T2 |
1395 |
5 |
0 |
0 |
T3 |
270594 |
1667 |
0 |
0 |
T7 |
143120 |
62 |
0 |
0 |
T8 |
70145 |
119 |
0 |
0 |
T9 |
9410 |
76 |
0 |
0 |
T10 |
32334 |
16 |
0 |
0 |
T11 |
149024 |
1432 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
156 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3488667 |
0 |
0 |
T1 |
10903 |
63 |
0 |
0 |
T2 |
1395 |
5 |
0 |
0 |
T3 |
270594 |
1344 |
0 |
0 |
T7 |
143120 |
9588 |
0 |
0 |
T8 |
70145 |
867 |
0 |
0 |
T9 |
9410 |
71 |
0 |
0 |
T10 |
32334 |
39 |
0 |
0 |
T11 |
149024 |
2083 |
0 |
0 |
T12 |
1684 |
6 |
0 |
0 |
T13 |
116864 |
316 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
365778 |
0 |
0 |
T1 |
10903 |
49 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
1017 |
0 |
0 |
T7 |
143120 |
1712 |
0 |
0 |
T8 |
70145 |
98 |
0 |
0 |
T9 |
9410 |
84 |
0 |
0 |
T10 |
32334 |
23 |
0 |
0 |
T11 |
149024 |
2127 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
162 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
670151 |
0 |
0 |
T1 |
10903 |
49 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
453 |
0 |
0 |
T7 |
143120 |
279 |
0 |
0 |
T8 |
70145 |
99 |
0 |
0 |
T9 |
9410 |
84 |
0 |
0 |
T10 |
32334 |
23 |
0 |
0 |
T11 |
149024 |
592 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
179 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3535774 |
0 |
0 |
T1 |
10903 |
96 |
0 |
0 |
T2 |
1395 |
6 |
0 |
0 |
T3 |
270594 |
13491 |
0 |
0 |
T7 |
143120 |
27165 |
0 |
0 |
T8 |
70145 |
1563 |
0 |
0 |
T9 |
9410 |
134 |
0 |
0 |
T10 |
32334 |
342 |
0 |
0 |
T11 |
149024 |
37430 |
0 |
0 |
T12 |
1684 |
17 |
0 |
0 |
T13 |
116864 |
1864 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3535774 |
0 |
0 |
T1 |
10903 |
96 |
0 |
0 |
T2 |
1395 |
6 |
0 |
0 |
T3 |
270594 |
13491 |
0 |
0 |
T7 |
143120 |
27165 |
0 |
0 |
T8 |
70145 |
1563 |
0 |
0 |
T9 |
9410 |
134 |
0 |
0 |
T10 |
32334 |
342 |
0 |
0 |
T11 |
149024 |
37430 |
0 |
0 |
T12 |
1684 |
17 |
0 |
0 |
T13 |
116864 |
1864 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4757327 |
0 |
0 |
T1 |
10903 |
96 |
0 |
0 |
T2 |
1395 |
6 |
0 |
0 |
T3 |
270594 |
2657 |
0 |
0 |
T7 |
143120 |
10332 |
0 |
0 |
T8 |
70145 |
812 |
0 |
0 |
T9 |
9410 |
134 |
0 |
0 |
T10 |
32334 |
70 |
0 |
0 |
T11 |
149024 |
4116 |
0 |
0 |
T12 |
1684 |
17 |
0 |
0 |
T13 |
116864 |
563 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4757327 |
0 |
0 |
T1 |
10903 |
96 |
0 |
0 |
T2 |
1395 |
6 |
0 |
0 |
T3 |
270594 |
2657 |
0 |
0 |
T7 |
143120 |
10332 |
0 |
0 |
T8 |
70145 |
812 |
0 |
0 |
T9 |
9410 |
134 |
0 |
0 |
T10 |
32334 |
70 |
0 |
0 |
T11 |
149024 |
4116 |
0 |
0 |
T12 |
1684 |
17 |
0 |
0 |
T13 |
116864 |
563 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
300727 |
0 |
0 |
T1 |
10903 |
43 |
0 |
0 |
T2 |
1395 |
2 |
0 |
0 |
T3 |
270594 |
2469 |
0 |
0 |
T7 |
143120 |
29 |
0 |
0 |
T8 |
70145 |
108 |
0 |
0 |
T9 |
9410 |
77 |
0 |
0 |
T10 |
32334 |
15 |
0 |
0 |
T11 |
149024 |
1257 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
160 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3990266 |
0 |
0 |
T1 |
10903 |
41 |
0 |
0 |
T2 |
1395 |
2 |
0 |
0 |
T3 |
270594 |
1643 |
0 |
0 |
T7 |
143120 |
9889 |
0 |
0 |
T8 |
70145 |
700 |
0 |
0 |
T9 |
9410 |
68 |
0 |
0 |
T10 |
32334 |
39 |
0 |
0 |
T11 |
149024 |
3420 |
0 |
0 |
T12 |
1684 |
6 |
0 |
0 |
T13 |
116864 |
358 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |