Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	755464	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	755464	0	0
T1	10903	86	0	0
T2	1395	2	0	0
T3	270594	395	0	0
T7	143120	37	0	0
T8	70145	341	0	0
T9	9410	163	0	0
T10	32334	32	0	0
T11	149024	1512	0	0
T12	1684	6	0	0
T13	116864	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	1050525	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	1050525	0	0
T1	10903	46	0	0
T2	1395	2	0	0
T3	270594	214	0	0
T7	143120	674	0	0
T8	70145	78	0	0
T9	9410	67	0	0
T10	32334	18	0	0
T11	149024	640	0	0
T12	1684	6	0	0
T13	116864	176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	751772	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	751772	0	0
T1	10903	113	0	0
T2	1395	8	0	0
T3	270594	216	0	0
T7	143120	125	0	0
T8	70145	153	0	0
T9	9410	138	0	0
T10	32334	56	0	0
T11	149024	3628	0	0
T12	1684	8	0	0
T13	116864	1401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	821973	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	821973	0	0
T1	10903	55	0	0
T2	1395	8	0	0
T3	270594	180	0	0
T7	143120	2767	0	0
T8	70145	76	0	0
T9	9410	66	0	0
T10	32334	28	0	0
T11	149024	62	0	0
T12	1684	4	0	0
T13	116864	127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	753472	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	753472	0	0
T1	10903	89	0	0
T2	1395	9	0	0
T3	270594	7828	0	0
T7	143120	216	0	0
T8	70145	193	0	0
T9	9410	137	0	0
T10	32334	26	0	0
T11	149024	2425	0	0
T12	1684	13	0	0
T13	116864	310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	962989	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	962989	0	0
T1	10903	56	0	0
T2	1395	9	0	0
T3	270594	516	0	0
T7	143120	1787	0	0
T8	70145	86	0	0
T9	9410	68	0	0
T10	32334	28	0	0
T11	149024	54	0	0
T12	1684	7	0	0
T13	116864	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	653801	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	653801	0	0
T1	10903	45	0	0
T2	1395	2	0	0
T3	270594	548	0	0
T7	143120	330	0	0
T8	70145	142	0	0
T9	9410	150	0	0
T10	32334	42	0	0
T11	149024	828	0	0
T12	1684	5	0	0
T13	116864	1195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	931729	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	931729	0	0
T1	10903	45	0	0
T2	1395	2	0	0
T3	270594	190	0	0
T7	143120	1913	0	0
T8	70145	74	0	0
T9	9410	81	0	0
T10	32334	31	0	0
T11	149024	228	0	0
T12	1684	5	0	0
T13	116864	107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	349733	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	349733	0	0
T1	10903	56	0	0
T2	1395	4	0	0
T3	270594	235	0	0
T7	143120	2129	0	0
T8	70145	160	0	0
T9	9410	78	0	0
T10	32334	32	0	0
T11	149024	2059	0	0
T12	1684	8	0	0
T13	116864	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	685877	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	685877	0	0
T1	10903	56	0	0
T2	1395	4	0	0
T3	270594	207	0	0
T7	143120	307	0	0
T8	70145	91	0	0
T9	9410	77	0	0
T10	32334	30	0	0
T11	149024	114	0	0
T12	1684	8	0	0
T13	116864	223	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	358028	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	358028	0	0
T1	10903	67	0	0
T2	1395	4	0	0
T3	270594	1552	0	0
T7	143120	681	0	0
T8	70145	118	0	0
T9	9410	69	0	0
T10	32334	26	0	0
T11	149024	2453	0	0
T12	1684	6	0	0
T13	116864	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	553610	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	553610	0	0
T1	10903	67	0	0
T2	1395	4	0	0
T3	270594	530	0	0
T7	143120	141	0	0
T8	70145	80	0	0
T9	9410	69	0	0
T10	32334	26	0	0
T11	149024	332	0	0
T12	1684	6	0	0
T13	116864	226	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	550146	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	550146	0	0
T1	10903	47	0	0
T2	1395	6	0	0
T3	270594	2107	0	0
T7	143120	2109	0	0
T8	70145	204	0	0
T9	9410	74	0	0
T10	32334	51	0	0
T11	149024	3103	0	0
T12	1684	13	0	0
T13	116864	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	567726	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	567726	0	0
T1	10903	46	0	0
T2	1395	6	0	0
T3	270594	444	0	0
T7	143120	457	0	0
T8	70145	102	0	0
T9	9410	66	0	0
T10	32334	28	0	0
T11	149024	218	0	0
T12	1684	13	0	0
T13	116864	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0