Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	366194	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	366194	0	0
T1	10903	52	0	0
T2	1395	9	0	0
T3	270594	4496	0	0
T7	143120	1213	0	0
T8	70145	173	0	0
T9	9410	75	0	0
T10	32334	21	0	0
T11	149024	1533	0	0
T12	1684	7	0	0
T13	116864	132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	711314	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	711314	0	0
T1	10903	51	0	0
T2	1395	9	0	0
T3	270594	566	0	0
T7	143120	648	0	0
T8	70145	116	0	0
T9	9410	73	0	0
T10	32334	38	0	0
T11	149024	52	0	0
T12	1684	7	0	0
T13	116864	147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	345764	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	345764	0	0
T1	10903	55	0	0
T2	1395	11	0	0
T3	270594	946	0	0
T7	143120	356	0	0
T8	70145	191	0	0
T9	9410	81	0	0
T10	32334	27	0	0
T11	149024	1069	0	0
T12	1684	13	0	0
T13	116864	163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	755272	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	755272	0	0
T1	10903	55	0	0
T2	1395	11	0	0
T3	270594	648	0	0
T7	143120	36	0	0
T8	70145	112	0	0
T9	9410	80	0	0
T10	32334	27	0	0
T11	149024	573	0	0
T12	1684	13	0	0
T13	116864	147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	371348	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	371348	0	0
T1	10903	68	0	0
T2	1395	3	0	0
T3	270594	2129	0	0
T7	143120	510	0	0
T8	70145	105	0	0
T9	9410	69	0	0
T10	32334	439	0	0
T11	149024	1804	0	0
T12	1684	10	0	0
T13	116864	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	849514	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	849514	0	0
T1	10903	68	0	0
T2	1395	3	0	0
T3	270594	1482	0	0
T7	143120	92	0	0
T8	70145	110	0	0
T9	9410	69	0	0
T10	32334	242	0	0
T11	149024	78	0	0
T12	1684	10	0	0
T13	116864	209	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	365778	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	365778	0	0
T1	10903	49	0	0
T2	1395	7	0	0
T3	270594	1017	0	0
T7	143120	1712	0	0
T8	70145	98	0	0
T9	9410	84	0	0
T10	32334	23	0	0
T11	149024	2127	0	0
T12	1684	5	0	0
T13	116864	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	670151	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	670151	0	0
T1	10903	49	0	0
T2	1395	7	0	0
T3	270594	453	0	0
T7	143120	279	0	0
T8	70145	99	0	0
T9	9410	84	0	0
T10	32334	23	0	0
T11	149024	592	0	0
T12	1684	5	0	0
T13	116864	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	383582	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	383582	0	0
T1	10903	55	0	0
T2	1395	4	0	0
T3	270594	3708	0	0
T7	143120	892	0	0
T8	70145	148	0	0
T9	9410	69	0	0
T10	32334	40	0	0
T11	149024	991	0	0
T12	1684	11	0	0
T13	116864	190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	767061	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	767061	0	0
T1	10903	55	0	0
T2	1395	4	0	0
T3	270594	1014	0	0
T7	143120	443	0	0
T8	70145	112	0	0
T9	9410	66	0	0
T10	32334	31	0	0
T11	149024	696	0	0
T12	1684	11	0	0
T13	116864	205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0