Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	268206	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	268206	0	0
T1	10903	59	0	0
T2	1395	3	0	0
T3	270594	670	0	0
T7	143120	32	0	0
T8	70145	109	0	0
T9	9410	79	0	0
T10	32334	27	0	0
T11	149024	328	0	0
T12	1684	5	0	0
T13	116864	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3696957	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3696957	0	0
T1	10903	55	0	0
T2	1395	3	0	0
T3	270594	800	0	0
T7	143120	9883	0	0
T8	70145	654	0	0
T9	9410	73	0	0
T10	32334	53	0	0
T11	149024	2970	0	0
T12	1684	5	0	0
T13	116864	272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	271164	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	271164	0	0
T1	10903	59	0	0
T2	1395	3	0	0
T3	270594	865	0	0
T7	143120	464	0	0
T8	70145	109	0	0
T9	9410	78	0	0
T10	32334	242	0	0
T11	149024	970	0	0
T12	1684	5	0	0
T13	116864	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	4327991	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4327991	0	0
T1	10903	56	0	0
T2	1395	3	0	0
T3	270594	1166	0	0
T7	143120	17991	0	0
T8	70145	546	0	0
T9	9410	65	0	0
T10	32334	482	0	0
T11	149024	3451	0	0
T12	1684	5	0	0
T13	116864	262	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	283194	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	283194	0	0
T1	10903	69	0	0
T2	1395	5	0	0
T3	270594	1667	0	0
T7	143120	62	0	0
T8	70145	119	0	0
T9	9410	76	0	0
T10	32334	16	0	0
T11	149024	1432	0	0
T12	1684	7	0	0
T13	116864	156	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3488667	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3488667	0	0
T1	10903	63	0	0
T2	1395	5	0	0
T3	270594	1344	0	0
T7	143120	9588	0	0
T8	70145	867	0	0
T9	9410	71	0	0
T10	32334	39	0	0
T11	149024	2083	0	0
T12	1684	6	0	0
T13	116864	316	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	300727	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	300727	0	0
T1	10903	43	0	0
T2	1395	2	0	0
T3	270594	2469	0	0
T7	143120	29	0	0
T8	70145	108	0	0
T9	9410	77	0	0
T10	32334	15	0	0
T11	149024	1257	0	0
T12	1684	7	0	0
T13	116864	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3990266	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3990266	0	0
T1	10903	41	0	0
T2	1395	2	0	0
T3	270594	1643	0	0
T7	143120	9889	0	0
T8	70145	700	0	0
T9	9410	68	0	0
T10	32334	39	0	0
T11	149024	3420	0	0
T12	1684	6	0	0
T13	116864	358	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3459203	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	3459203	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3459203	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	3329	0	0
T7	143120	25192	0	0
T8	70145	1421	0	0
T9	9410	129	0	0
T10	32334	457	0	0
T11	149024	39825	0	0
T12	1684	17	0	0
T13	116864	1923	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3459203	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	3329	0	0
T7	143120	25192	0	0
T8	70145	1421	0	0
T9	9410	129	0	0
T10	32334	457	0	0
T11	149024	39825	0	0
T12	1684	17	0	0
T13	116864	1923	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	3369101	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	456130957	3369101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3369101	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	663	0	0
T7	143120	14444	0	0
T8	70145	938	0	0
T9	9410	129	0	0
T10	32334	125	0	0
T11	149024	4291	0	0
T12	1684	17	0	0
T13	116864	497	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3369101	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	663	0	0
T7	143120	14444	0	0
T8	70145	938	0	0
T9	9410	129	0	0
T10	32334	125	0	0
T11	149024	4291	0	0
T12	1684	17	0	0
T13	116864	497	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	294593	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	294593	0	0
T1	10903	51	0	0
T2	1395	3	0	0
T3	270594	219	0	0
T7	143120	325	0	0
T8	70145	144	0	0
T9	9410	78	0	0
T10	32334	31	0	0
T11	149024	811	0	0
T12	1684	6	0	0
T13	116864	127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	2813303	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	2813303	0	0
T1	10903	48	0	0
T2	1395	3	0	0
T3	270594	454	0	0
T7	143120	13992	0	0
T8	70145	825	0	0
T9	9410	70	0	0
T10	32334	96	0	0
T11	149024	4216	0	0
T12	1684	6	0	0
T13	116864	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	395998	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	395998	0	0
T1	10903	50	0	0
T2	1395	4	0	0
T3	270594	243	0	0
T7	143120	2015	0	0
T8	70145	153	0	0
T9	9410	61	0	0
T10	32334	35	0	0
T11	149024	50	0	0
T12	1684	11	0	0
T13	116864	179	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456130957	555798	0	0
DepthKnown_A	456130957	455998313	0	0
RvalidKnown_A	456130957	455998313	0	0
WreadyKnown_A	456130957	455998313	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	555798	0	0
T1	10903	50	0	0
T2	1395	4	0	0
T3	270594	209	0	0
T7	143120	452	0	0
T8	70145	113	0	0
T9	9410	59	0	0
T10	32334	29	0	0
T11	149024	75	0	0
T12	1684	11	0	0
T13	116864	212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0