Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
653801 |
0 |
0 |
T1 |
10903 |
45 |
0 |
0 |
T2 |
1395 |
2 |
0 |
0 |
T3 |
270594 |
548 |
0 |
0 |
T7 |
143120 |
330 |
0 |
0 |
T8 |
70145 |
142 |
0 |
0 |
T9 |
9410 |
150 |
0 |
0 |
T10 |
32334 |
42 |
0 |
0 |
T11 |
149024 |
828 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
1195 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
931729 |
0 |
0 |
T1 |
10903 |
45 |
0 |
0 |
T2 |
1395 |
2 |
0 |
0 |
T3 |
270594 |
190 |
0 |
0 |
T7 |
143120 |
1913 |
0 |
0 |
T8 |
70145 |
74 |
0 |
0 |
T9 |
9410 |
81 |
0 |
0 |
T10 |
32334 |
31 |
0 |
0 |
T11 |
149024 |
228 |
0 |
0 |
T12 |
1684 |
5 |
0 |
0 |
T13 |
116864 |
107 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3392768 |
0 |
0 |
T1 |
10903 |
94 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
3258 |
0 |
0 |
T7 |
143120 |
30721 |
0 |
0 |
T8 |
70145 |
1378 |
0 |
0 |
T9 |
9410 |
159 |
0 |
0 |
T10 |
32334 |
478 |
0 |
0 |
T11 |
149024 |
38038 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
2021 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3392768 |
0 |
0 |
T1 |
10903 |
94 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
3258 |
0 |
0 |
T7 |
143120 |
30721 |
0 |
0 |
T8 |
70145 |
1378 |
0 |
0 |
T9 |
9410 |
159 |
0 |
0 |
T10 |
32334 |
478 |
0 |
0 |
T11 |
149024 |
38038 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
2021 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4233653 |
0 |
0 |
T1 |
10903 |
94 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
664 |
0 |
0 |
T7 |
143120 |
12190 |
0 |
0 |
T8 |
70145 |
749 |
0 |
0 |
T9 |
9410 |
159 |
0 |
0 |
T10 |
32334 |
114 |
0 |
0 |
T11 |
149024 |
1870 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
533 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
4233653 |
0 |
0 |
T1 |
10903 |
94 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
664 |
0 |
0 |
T7 |
143120 |
12190 |
0 |
0 |
T8 |
70145 |
749 |
0 |
0 |
T9 |
9410 |
159 |
0 |
0 |
T10 |
32334 |
114 |
0 |
0 |
T11 |
149024 |
1870 |
0 |
0 |
T12 |
1684 |
12 |
0 |
0 |
T13 |
116864 |
533 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
263574 |
0 |
0 |
T1 |
10903 |
44 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
224 |
0 |
0 |
T7 |
143120 |
253 |
0 |
0 |
T8 |
70145 |
111 |
0 |
0 |
T9 |
9410 |
89 |
0 |
0 |
T10 |
32334 |
31 |
0 |
0 |
T11 |
149024 |
578 |
0 |
0 |
T12 |
1684 |
4 |
0 |
0 |
T13 |
116864 |
149 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3547776 |
0 |
0 |
T1 |
10903 |
38 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
457 |
0 |
0 |
T7 |
143120 |
11883 |
0 |
0 |
T8 |
70145 |
658 |
0 |
0 |
T9 |
9410 |
82 |
0 |
0 |
T10 |
32334 |
84 |
0 |
0 |
T11 |
149024 |
1756 |
0 |
0 |
T12 |
1684 |
4 |
0 |
0 |
T13 |
116864 |
310 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
349733 |
0 |
0 |
T1 |
10903 |
56 |
0 |
0 |
T2 |
1395 |
4 |
0 |
0 |
T3 |
270594 |
235 |
0 |
0 |
T7 |
143120 |
2129 |
0 |
0 |
T8 |
70145 |
160 |
0 |
0 |
T9 |
9410 |
78 |
0 |
0 |
T10 |
32334 |
32 |
0 |
0 |
T11 |
149024 |
2059 |
0 |
0 |
T12 |
1684 |
8 |
0 |
0 |
T13 |
116864 |
179 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
685877 |
0 |
0 |
T1 |
10903 |
56 |
0 |
0 |
T2 |
1395 |
4 |
0 |
0 |
T3 |
270594 |
207 |
0 |
0 |
T7 |
143120 |
307 |
0 |
0 |
T8 |
70145 |
91 |
0 |
0 |
T9 |
9410 |
77 |
0 |
0 |
T10 |
32334 |
30 |
0 |
0 |
T11 |
149024 |
114 |
0 |
0 |
T12 |
1684 |
8 |
0 |
0 |
T13 |
116864 |
223 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T3,T7,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3445371 |
0 |
0 |
T1 |
10903 |
124 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
7809 |
0 |
0 |
T7 |
143120 |
23121 |
0 |
0 |
T8 |
70145 |
1244 |
0 |
0 |
T9 |
9410 |
132 |
0 |
0 |
T10 |
32334 |
388 |
0 |
0 |
T11 |
149024 |
41494 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
1779 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3445371 |
0 |
0 |
T1 |
10903 |
124 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
7809 |
0 |
0 |
T7 |
143120 |
23121 |
0 |
0 |
T8 |
70145 |
1244 |
0 |
0 |
T9 |
9410 |
132 |
0 |
0 |
T10 |
32334 |
388 |
0 |
0 |
T11 |
149024 |
41494 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
1779 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3293184 |
0 |
0 |
T1 |
10903 |
124 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
1789 |
0 |
0 |
T7 |
143120 |
14205 |
0 |
0 |
T8 |
70145 |
825 |
0 |
0 |
T9 |
9410 |
132 |
0 |
0 |
T10 |
32334 |
79 |
0 |
0 |
T11 |
149024 |
2744 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
549 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
3293184 |
0 |
0 |
T1 |
10903 |
124 |
0 |
0 |
T2 |
1395 |
7 |
0 |
0 |
T3 |
270594 |
1789 |
0 |
0 |
T7 |
143120 |
14205 |
0 |
0 |
T8 |
70145 |
825 |
0 |
0 |
T9 |
9410 |
132 |
0 |
0 |
T10 |
32334 |
79 |
0 |
0 |
T11 |
149024 |
2744 |
0 |
0 |
T12 |
1684 |
7 |
0 |
0 |
T13 |
116864 |
549 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
268854 |
0 |
0 |
T1 |
10903 |
64 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
1567 |
0 |
0 |
T7 |
143120 |
305 |
0 |
0 |
T8 |
70145 |
106 |
0 |
0 |
T9 |
9410 |
72 |
0 |
0 |
T10 |
32334 |
49 |
0 |
0 |
T11 |
149024 |
532 |
0 |
0 |
T12 |
1684 |
1 |
0 |
0 |
T13 |
116864 |
129 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
2739574 |
0 |
0 |
T1 |
10903 |
57 |
0 |
0 |
T2 |
1395 |
3 |
0 |
0 |
T3 |
270594 |
1259 |
0 |
0 |
T7 |
143120 |
14064 |
0 |
0 |
T8 |
70145 |
745 |
0 |
0 |
T9 |
9410 |
63 |
0 |
0 |
T10 |
32334 |
53 |
0 |
0 |
T11 |
149024 |
2412 |
0 |
0 |
T12 |
1684 |
1 |
0 |
0 |
T13 |
116864 |
323 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
358028 |
0 |
0 |
T1 |
10903 |
67 |
0 |
0 |
T2 |
1395 |
4 |
0 |
0 |
T3 |
270594 |
1552 |
0 |
0 |
T7 |
143120 |
681 |
0 |
0 |
T8 |
70145 |
118 |
0 |
0 |
T9 |
9410 |
69 |
0 |
0 |
T10 |
32334 |
26 |
0 |
0 |
T11 |
149024 |
2453 |
0 |
0 |
T12 |
1684 |
6 |
0 |
0 |
T13 |
116864 |
186 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
553610 |
0 |
0 |
T1 |
10903 |
67 |
0 |
0 |
T2 |
1395 |
4 |
0 |
0 |
T3 |
270594 |
530 |
0 |
0 |
T7 |
143120 |
141 |
0 |
0 |
T8 |
70145 |
80 |
0 |
0 |
T9 |
9410 |
69 |
0 |
0 |
T10 |
32334 |
26 |
0 |
0 |
T11 |
149024 |
332 |
0 |
0 |
T12 |
1684 |
6 |
0 |
0 |
T13 |
116864 |
226 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456130957 |
455998313 |
0 |
0 |
T1 |
10903 |
10826 |
0 |
0 |
T2 |
1395 |
1379 |
0 |
0 |
T3 |
270594 |
270454 |
0 |
0 |
T7 |
143120 |
143119 |
0 |
0 |
T8 |
70145 |
70097 |
0 |
0 |
T9 |
9410 |
9353 |
0 |
0 |
T10 |
32334 |
31060 |
0 |
0 |
T11 |
149024 |
149016 |
0 |
0 |
T12 |
1684 |
1654 |
0 |
0 |
T13 |
116864 |
116806 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |