Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7596988	0	0
GntImpliesValid_A	2147483647	7596988	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7596988	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	488227360	0	0
ReadyAndValidImplyGrant_A	2147483647	7596988	0	0
ReqAndReadyImplyGrant_A	2147483647	7596988	0	0
ReqImpliesValid_A	2147483647	33842092	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	38358	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7596988	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261672	259824	0	0
T2	33480	33096	0	0
T3	6494256	6490896	0	0
T7	3434880	3434856	0	0
T8	1683480	1682328	0	0
T9	225840	224472	0	0
T10	776016	745440	0	0
T11	3576576	3576384	0	0
T12	40416	39696	0	0
T13	2804736	2803344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7596988	0	0
T1	261672	3919	0	0
T2	33480	372	0	0
T3	6494256	23431	0	0
T7	3434880	2943	0	0
T8	1683480	6213	0	0
T9	225840	5242	0	0
T10	776016	3193	0	0
T11	3576576	4046	0	0
T12	40416	393	0	0
T13	2804736	8453	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7596988	0	0
T1	261672	3919	0	0
T2	33480	372	0	0
T3	6494256	23431	0	0
T7	3434880	2943	0	0
T8	1683480	6213	0	0
T9	225840	5242	0	0
T10	776016	3193	0	0
T11	3576576	4046	0	0
T12	40416	393	0	0
T13	2804736	8453	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261672	259824	0	0
T2	33480	33096	0	0
T3	6494256	6490896	0	0
T7	3434880	3434856	0	0
T8	1683480	1682328	0	0
T9	225840	224472	0	0
T10	776016	745440	0	0
T11	3576576	3576384	0	0
T12	40416	39696	0	0
T13	2804736	2803344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261672	259824	0	0
T2	33480	33096	0	0
T3	6494256	6490896	0	0
T7	3434880	3434856	0	0
T8	1683480	1682328	0	0
T9	225840	224472	0	0
T10	776016	745440	0	0
T11	3576576	3576384	0	0
T12	40416	39696	0	0
T13	2804736	2803344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7596988	0	0
T1	261672	3919	0	0
T2	33480	372	0	0
T3	6494256	23431	0	0
T7	3434880	2943	0	0
T8	1683480	6213	0	0
T9	225840	5242	0	0
T10	776016	3193	0	0
T11	3576576	4046	0	0
T12	40416	393	0	0
T13	2804736	8453	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	488227360	0	0
T1	261672	5967	0	0
T2	33480	365	0	0
T3	6494256	407746	0	0
T7	3434880	925008	0	0
T8	1683480	105380	0	0
T9	225840	6704	0	0
T10	776016	47901	0	0
T11	3576576	1365407	0	0
T12	40416	455	0	0
T13	2804736	191047	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7596988	0	0
T1	261672	3919	0	0
T2	33480	372	0	0
T3	6494256	23431	0	0
T7	3434880	2943	0	0
T8	1683480	6213	0	0
T9	225840	5242	0	0
T10	776016	3193	0	0
T11	3576576	4046	0	0
T12	40416	393	0	0
T13	2804736	8453	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7596988	0	0
T1	261672	3919	0	0
T2	33480	372	0	0
T3	6494256	23431	0	0
T7	3434880	2943	0	0
T8	1683480	6213	0	0
T9	225840	5242	0	0
T10	776016	3193	0	0
T11	3576576	4046	0	0
T12	40416	393	0	0
T13	2804736	8453	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33842092	0	0
T1	261672	4503	0	0
T2	33480	407	0	0
T3	6494256	73728	0	0
T7	3434880	188992	0	0
T8	1683480	15153	0	0
T9	225840	6257	0	0
T10	776016	8384	0	0
T11	3576576	271818	0	0
T12	40416	421	0	0
T13	2804736	23170	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38358	0	21600
T1	21806	14	0	2
T2	2790	0	0	2
T3	541188	0	0	2
T7	286240	0	0	2
T8	140290	0	0	2
T9	18820	26	0	2
T10	64668	0	0	2
T11	298048	0	0	2
T12	3368	0	0	2
T13	233728	2	0	2
T14	0	146	0	0
T15	0	19	0	0
T16	0	6	0	0
T17	0	23	0	0
T18	0	26	0	0
T19	0	68	0	0
T20	0	1	0	0
T21	0	21	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	261672	259824	0	0
T2	33480	33096	0	0
T3	6494256	6490896	0	0
T7	3434880	3434856	0	0
T8	1683480	1682328	0	0
T9	225840	224472	0	0
T10	776016	745440	0	0
T11	3576576	3576384	0	0
T12	40416	39696	0	0
T13	2804736	2803344	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7596988	0	0
T1	261672	3919	0	0
T2	33480	372	0	0
T3	6494256	23431	0	0
T7	3434880	2943	0	0
T8	1683480	6213	0	0
T9	225840	5242	0	0
T10	776016	3193	0	0
T11	3576576	4046	0	0
T12	40416	393	0	0
T13	2804736	8453	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	829601	0	0
GntImpliesValid_A	456130957	829601	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	829601	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	12286263	0	0
ReadyAndValidImplyGrant_A	456130957	829601	0	0
ReqAndReadyImplyGrant_A	456130957	829601	0	0
ReqImpliesValid_A	456130957	2412066	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	829601	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	829601	0	0
T1	10903	420	0	0
T2	1395	38	0	0
T3	270594	2910	0	0
T7	143120	379	0	0
T8	70145	686	0	0
T9	9410	570	0	0
T10	32334	374	0	0
T11	149024	403	0	0
T12	1684	34	0	0
T13	116864	941	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	829601	0	0
T1	10903	420	0	0
T2	1395	38	0	0
T3	270594	2910	0	0
T7	143120	379	0	0
T8	70145	686	0	0
T9	9410	570	0	0
T10	32334	374	0	0
T11	149024	403	0	0
T12	1684	34	0	0
T13	116864	941	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	829601	0	0
T1	10903	420	0	0
T2	1395	38	0	0
T3	270594	2910	0	0
T7	143120	379	0	0
T8	70145	686	0	0
T9	9410	570	0	0
T10	32334	374	0	0
T11	149024	403	0	0
T12	1684	34	0	0
T13	116864	941	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	12286263	0	0
T1	10903	334	0	0
T2	1395	30	0	0
T3	270594	18841	0	0
T7	143120	124989	0	0
T8	70145	4995	0	0
T9	9410	431	0	0
T10	32334	2819	0	0
T11	149024	136162	0	0
T12	1684	29	0	0
T13	116864	7084	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	829601	0	0
T1	10903	420	0	0
T2	1395	38	0	0
T3	270594	2910	0	0
T7	143120	379	0	0
T8	70145	686	0	0
T9	9410	570	0	0
T10	32334	374	0	0
T11	149024	403	0	0
T12	1684	34	0	0
T13	116864	941	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	829601	0	0
T1	10903	420	0	0
T2	1395	38	0	0
T3	270594	2910	0	0
T7	143120	379	0	0
T8	70145	686	0	0
T9	9410	570	0	0
T10	32334	374	0	0
T11	149024	403	0	0
T12	1684	34	0	0
T13	116864	941	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	2412066	0	0
T1	10903	507	0	0
T2	1395	47	0	0
T3	270594	8560	0	0
T7	143120	14159	0	0
T8	70145	1356	0	0
T9	9410	710	0	0
T10	32334	642	0	0
T11	149024	18272	0	0
T12	1684	40	0	0
T13	116864	1600	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	829601	0	0
T1	10903	420	0	0
T2	1395	38	0	0
T3	270594	2910	0	0
T7	143120	379	0	0
T8	70145	686	0	0
T9	9410	570	0	0
T10	32334	374	0	0
T11	149024	403	0	0
T12	1684	34	0	0
T13	116864	941	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	841926	0	0
GntImpliesValid_A	456130957	841926	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	841926	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	12381759	0	0
ReadyAndValidImplyGrant_A	456130957	841926	0	0
ReqAndReadyImplyGrant_A	456130957	841926	0	0
ReqImpliesValid_A	456130957	2393827	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	841926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	841926	0	0
T1	10903	426	0	0
T2	1395	46	0	0
T3	270594	2981	0	0
T7	143120	350	0	0
T8	70145	684	0	0
T9	9410	587	0	0
T10	32334	359	0	0
T11	149024	433	0	0
T12	1684	49	0	0
T13	116864	947	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	841926	0	0
T1	10903	426	0	0
T2	1395	46	0	0
T3	270594	2981	0	0
T7	143120	350	0	0
T8	70145	684	0	0
T9	9410	587	0	0
T10	32334	359	0	0
T11	149024	433	0	0
T12	1684	49	0	0
T13	116864	947	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	841926	0	0
T1	10903	426	0	0
T2	1395	46	0	0
T3	270594	2981	0	0
T7	143120	350	0	0
T8	70145	684	0	0
T9	9410	587	0	0
T10	32334	359	0	0
T11	149024	433	0	0
T12	1684	49	0	0
T13	116864	947	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	12381759	0	0
T1	10903	351	0	0
T2	1395	35	0	0
T3	270594	19941	0	0
T7	143120	115633	0	0
T8	70145	4806	0	0
T9	9410	432	0	0
T10	32334	2753	0	0
T11	149024	134473	0	0
T12	1684	43	0	0
T13	116864	6326	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	841926	0	0
T1	10903	426	0	0
T2	1395	46	0	0
T3	270594	2981	0	0
T7	143120	350	0	0
T8	70145	684	0	0
T9	9410	587	0	0
T10	32334	359	0	0
T11	149024	433	0	0
T12	1684	49	0	0
T13	116864	947	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	841926	0	0
T1	10903	426	0	0
T2	1395	46	0	0
T3	270594	2981	0	0
T7	143120	350	0	0
T8	70145	684	0	0
T9	9410	587	0	0
T10	32334	359	0	0
T11	149024	433	0	0
T12	1684	49	0	0
T13	116864	947	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	2393827	0	0
T1	10903	502	0	0
T2	1395	58	0	0
T3	270594	7834	0	0
T7	143120	9873	0	0
T8	70145	1377	0	0
T9	9410	743	0	0
T10	32334	685	0	0
T11	149024	15937	0	0
T12	1684	56	0	0
T13	116864	1584	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	841926	0	0
T1	10903	426	0	0
T2	1395	46	0	0
T3	270594	2981	0	0
T7	143120	350	0	0
T8	70145	684	0	0
T9	9410	587	0	0
T10	32334	359	0	0
T11	149024	433	0	0
T12	1684	49	0	0
T13	116864	947	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	211961	0	0
GntImpliesValid_A	456130957	211961	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	211961	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3092144	0	0
ReadyAndValidImplyGrant_A	456130957	211961	0	0
ReqAndReadyImplyGrant_A	456130957	211961	0	0
ReqImpliesValid_A	456130957	581075	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	211961	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211961	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	401	0	0
T7	143120	72	0	0
T8	70145	196	0	0
T9	9410	129	0	0
T10	32334	58	0	0
T11	149024	114	0	0
T12	1684	17	0	0
T13	116864	240	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211961	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	401	0	0
T7	143120	72	0	0
T8	70145	196	0	0
T9	9410	129	0	0
T10	32334	58	0	0
T11	149024	114	0	0
T12	1684	17	0	0
T13	116864	240	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211961	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	401	0	0
T7	143120	72	0	0
T8	70145	196	0	0
T9	9410	129	0	0
T10	32334	58	0	0
T11	149024	114	0	0
T12	1684	17	0	0
T13	116864	240	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3092144	0	0
T1	10903	96	0	0
T2	1395	8	0	0
T3	270594	3271	0	0
T7	143120	22925	0	0
T8	70145	1321	0	0
T9	9410	120	0	0
T10	32334	460	0	0
T11	149024	39079	0	0
T12	1684	18	0	0
T13	116864	1858	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211961	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	401	0	0
T7	143120	72	0	0
T8	70145	196	0	0
T9	9410	129	0	0
T10	32334	58	0	0
T11	149024	114	0	0
T12	1684	17	0	0
T13	116864	240	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211961	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	401	0	0
T7	143120	72	0	0
T8	70145	196	0	0
T9	9410	129	0	0
T10	32334	58	0	0
T11	149024	114	0	0
T12	1684	17	0	0
T13	116864	240	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	581075	0	0
T1	10903	101	0	0
T2	1395	7	0	0
T3	270594	462	0	0
T7	143120	2340	0	0
T8	70145	297	0	0
T9	9410	139	0	0
T10	32334	66	0	0
T11	149024	861	0	0
T12	1684	17	0	0
T13	116864	306	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211961	0	0
T1	10903	98	0	0
T2	1395	7	0	0
T3	270594	401	0	0
T7	143120	72	0	0
T8	70145	196	0	0
T9	9410	129	0	0
T10	32334	58	0	0
T11	149024	114	0	0
T12	1684	17	0	0
T13	116864	240	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	207348	0	0
GntImpliesValid_A	456130957	207348	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	207348	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3048706	0	0
ReadyAndValidImplyGrant_A	456130957	207348	0	0
ReqAndReadyImplyGrant_A	456130957	207348	0	0
ReqImpliesValid_A	456130957	519645	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	207348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207348	0	0
T1	10903	95	0	0
T2	1395	7	0	0
T3	270594	388	0	0
T7	143120	87	0	0
T8	70145	181	0	0
T9	9410	141	0	0
T10	32334	54	0	0
T11	149024	126	0	0
T12	1684	13	0	0
T13	116864	246	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207348	0	0
T1	10903	95	0	0
T2	1395	7	0	0
T3	270594	388	0	0
T7	143120	87	0	0
T8	70145	181	0	0
T9	9410	141	0	0
T10	32334	54	0	0
T11	149024	126	0	0
T12	1684	13	0	0
T13	116864	246	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207348	0	0
T1	10903	95	0	0
T2	1395	7	0	0
T3	270594	388	0	0
T7	143120	87	0	0
T8	70145	181	0	0
T9	9410	141	0	0
T10	32334	54	0	0
T11	149024	126	0	0
T12	1684	13	0	0
T13	116864	246	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3048706	0	0
T1	10903	94	0	0
T2	1395	8	0	0
T3	270594	2931	0	0
T7	143120	25653	0	0
T8	70145	1336	0	0
T9	9410	138	0	0
T10	32334	411	0	0
T11	149024	44063	0	0
T12	1684	14	0	0
T13	116864	1921	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207348	0	0
T1	10903	95	0	0
T2	1395	7	0	0
T3	270594	388	0	0
T7	143120	87	0	0
T8	70145	181	0	0
T9	9410	141	0	0
T10	32334	54	0	0
T11	149024	126	0	0
T12	1684	13	0	0
T13	116864	246	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207348	0	0
T1	10903	95	0	0
T2	1395	7	0	0
T3	270594	388	0	0
T7	143120	87	0	0
T8	70145	181	0	0
T9	9410	141	0	0
T10	32334	54	0	0
T11	149024	126	0	0
T12	1684	13	0	0
T13	116864	246	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	519645	0	0
T1	10903	97	0	0
T2	1395	7	0	0
T3	270594	435	0	0
T7	143120	2348	0	0
T8	70145	278	0	0
T9	9410	145	0	0
T10	32334	54	0	0
T11	149024	2764	0	0
T12	1684	13	0	0
T13	116864	352	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207348	0	0
T1	10903	95	0	0
T2	1395	7	0	0
T3	270594	388	0	0
T7	143120	87	0	0
T8	70145	181	0	0
T9	9410	141	0	0
T10	32334	54	0	0
T11	149024	126	0	0
T12	1684	13	0	0
T13	116864	246	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	205989	0	0
GntImpliesValid_A	456130957	205989	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	205989	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	4777731	0	0
ReadyAndValidImplyGrant_A	456130957	205989	0	0
ReqAndReadyImplyGrant_A	456130957	205989	0	0
ReqImpliesValid_A	456130957	1067503	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	205989	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205989	0	0
T1	10903	99	0	0
T2	1395	9	0	0
T3	270594	392	0	0
T7	143120	73	0	0
T8	70145	156	0	0
T9	9410	140	0	0
T10	32334	46	0	0
T11	149024	128	0	0
T12	1684	7	0	0
T13	116864	237	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205989	0	0
T1	10903	99	0	0
T2	1395	9	0	0
T3	270594	392	0	0
T7	143120	73	0	0
T8	70145	156	0	0
T9	9410	140	0	0
T10	32334	46	0	0
T11	149024	128	0	0
T12	1684	7	0	0
T13	116864	237	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205989	0	0
T1	10903	99	0	0
T2	1395	9	0	0
T3	270594	392	0	0
T7	143120	73	0	0
T8	70145	156	0	0
T9	9410	140	0	0
T10	32334	46	0	0
T11	149024	128	0	0
T12	1684	7	0	0
T13	116864	237	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4777731	0	0
T1	10903	940	0	0
T2	1395	27	0	0
T3	270594	8272	0	0
T7	143120	15232	0	0
T8	70145	4844	0	0
T9	9410	1205	0	0
T10	32334	466	0	0
T11	149024	40935	0	0
T12	1684	31	0	0
T13	116864	3085	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205989	0	0
T1	10903	99	0	0
T2	1395	9	0	0
T3	270594	392	0	0
T7	143120	73	0	0
T8	70145	156	0	0
T9	9410	140	0	0
T10	32334	46	0	0
T11	149024	128	0	0
T12	1684	7	0	0
T13	116864	237	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205989	0	0
T1	10903	99	0	0
T2	1395	9	0	0
T3	270594	392	0	0
T7	143120	73	0	0
T8	70145	156	0	0
T9	9410	140	0	0
T10	32334	46	0	0
T11	149024	128	0	0
T12	1684	7	0	0
T13	116864	237	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	1067503	0	0
T1	10903	255	0	0
T2	1395	12	0	0
T3	270594	612	0	0
T7	143120	73	0	0
T8	70145	876	0	0
T9	9410	330	0	0
T10	32334	62	0	0
T11	149024	2153	0	0
T12	1684	7	0	0
T13	116864	362	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205989	0	0
T1	10903	99	0	0
T2	1395	9	0	0
T3	270594	392	0	0
T7	143120	73	0	0
T8	70145	156	0	0
T9	9410	140	0	0
T10	32334	46	0	0
T11	149024	128	0	0
T12	1684	7	0	0
T13	116864	237	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	205294	0	0
GntImpliesValid_A	456130957	205294	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	205294	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	4777962	0	0
ReadyAndValidImplyGrant_A	456130957	205294	0	0
ReqAndReadyImplyGrant_A	456130957	205294	0	0
ReqImpliesValid_A	456130957	1051961	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	205294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205294	0	0
T1	10903	112	0	0
T2	1395	16	0	0
T3	270594	363	0	0
T7	143120	77	0	0
T8	70145	169	0	0
T9	9410	139	0	0
T10	32334	57	0	0
T11	149024	109	0	0
T12	1684	9	0	0
T13	116864	266	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205294	0	0
T1	10903	112	0	0
T2	1395	16	0	0
T3	270594	363	0	0
T7	143120	77	0	0
T8	70145	169	0	0
T9	9410	139	0	0
T10	32334	57	0	0
T11	149024	109	0	0
T12	1684	9	0	0
T13	116864	266	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205294	0	0
T1	10903	112	0	0
T2	1395	16	0	0
T3	270594	363	0	0
T7	143120	77	0	0
T8	70145	169	0	0
T9	9410	139	0	0
T10	32334	57	0	0
T11	149024	109	0	0
T12	1684	9	0	0
T13	116864	266	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4777962	0	0
T1	10903	951	0	0
T2	1395	59	0	0
T3	270594	3393	0	0
T7	143120	2705	0	0
T8	70145	2239	0	0
T9	9410	826	0	0
T10	32334	1449	0	0
T11	149024	42811	0	0
T12	1684	51	0	0
T13	116864	15517	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205294	0	0
T1	10903	112	0	0
T2	1395	16	0	0
T3	270594	363	0	0
T7	143120	77	0	0
T8	70145	169	0	0
T9	9410	139	0	0
T10	32334	57	0	0
T11	149024	109	0	0
T12	1684	9	0	0
T13	116864	266	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205294	0	0
T1	10903	112	0	0
T2	1395	16	0	0
T3	270594	363	0	0
T7	143120	77	0	0
T8	70145	169	0	0
T9	9410	139	0	0
T10	32334	57	0	0
T11	149024	109	0	0
T12	1684	9	0	0
T13	116864	266	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	1051961	0	0
T1	10903	209	0	0
T2	1395	19	0	0
T3	270594	407	0	0
T7	143120	171	0	0
T8	70145	348	0	0
T9	9410	259	0	0
T10	32334	121	0	0
T11	149024	3676	0	0
T12	1684	13	0	0
T13	116864	2369	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	205294	0	0
T1	10903	112	0	0
T2	1395	16	0	0
T3	270594	363	0	0
T7	143120	77	0	0
T8	70145	169	0	0
T9	9410	139	0	0
T10	32334	57	0	0
T11	149024	109	0	0
T12	1684	9	0	0
T13	116864	266	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	207506	0	0
GntImpliesValid_A	456130957	207506	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	207506	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	4987562	0	0
ReadyAndValidImplyGrant_A	456130957	207506	0	0
ReqAndReadyImplyGrant_A	456130957	207506	0	0
ReqImpliesValid_A	456130957	1056076	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	207506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	115	0	0
T2	1395	10	0	0
T3	270594	932	0	0
T7	143120	73	0	0
T8	70145	161	0	0
T9	9410	157	0	0
T10	32334	47	0	0
T11	149024	116	0	0
T12	1684	13	0	0
T13	116864	199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	115	0	0
T2	1395	10	0	0
T3	270594	932	0	0
T7	143120	73	0	0
T8	70145	161	0	0
T9	9410	157	0	0
T10	32334	47	0	0
T11	149024	116	0	0
T12	1684	13	0	0
T13	116864	199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	115	0	0
T2	1395	10	0	0
T3	270594	932	0	0
T7	143120	73	0	0
T8	70145	161	0	0
T9	9410	157	0	0
T10	32334	47	0	0
T11	149024	116	0	0
T12	1684	13	0	0
T13	116864	199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4987562	0	0
T1	10903	757	0	0
T2	1395	38	0	0
T3	270594	25924	0	0
T7	143120	5227	0	0
T8	70145	2025	0	0
T9	9410	817	0	0
T10	32334	537	0	0
T11	149024	90254	0	0
T12	1684	50	0	0
T13	116864	3881	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	115	0	0
T2	1395	10	0	0
T3	270594	932	0	0
T7	143120	73	0	0
T8	70145	161	0	0
T9	9410	157	0	0
T10	32334	47	0	0
T11	149024	116	0	0
T12	1684	13	0	0
T13	116864	199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	115	0	0
T2	1395	10	0	0
T3	270594	932	0	0
T7	143120	73	0	0
T8	70145	161	0	0
T9	9410	157	0	0
T10	32334	47	0	0
T11	149024	116	0	0
T12	1684	13	0	0
T13	116864	199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	1056076	0	0
T1	10903	169	0	0
T2	1395	10	0	0
T3	270594	9285	0	0
T7	143120	251	0	0
T8	70145	328	0	0
T9	9410	308	0	0
T10	32334	55	0	0
T11	149024	5833	0	0
T12	1684	19	0	0
T13	116864	503	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	115	0	0
T2	1395	10	0	0
T3	270594	932	0	0
T7	143120	73	0	0
T8	70145	161	0	0
T9	9410	157	0	0
T10	32334	47	0	0
T11	149024	116	0	0
T12	1684	13	0	0
T13	116864	199	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	210719	0	0
GntImpliesValid_A	456130957	210719	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	210719	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	4736974	0	0
ReadyAndValidImplyGrant_A	456130957	210719	0	0
ReqAndReadyImplyGrant_A	456130957	210719	0	0
ReqImpliesValid_A	456130957	967331	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	210719	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210719	0	0
T1	10903	95	0	0
T2	1395	6	0	0
T3	270594	414	0	0
T7	143120	80	0	0
T8	70145	171	0	0
T9	9410	149	0	0
T10	32334	57	0	0
T11	149024	111	0	0
T12	1684	8	0	0
T13	116864	222	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210719	0	0
T1	10903	95	0	0
T2	1395	6	0	0
T3	270594	414	0	0
T7	143120	80	0	0
T8	70145	171	0	0
T9	9410	149	0	0
T10	32334	57	0	0
T11	149024	111	0	0
T12	1684	8	0	0
T13	116864	222	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210719	0	0
T1	10903	95	0	0
T2	1395	6	0	0
T3	270594	414	0	0
T7	143120	80	0	0
T8	70145	171	0	0
T9	9410	149	0	0
T10	32334	57	0	0
T11	149024	111	0	0
T12	1684	8	0	0
T13	116864	222	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	4736974	0	0
T1	10903	919	0	0
T2	1395	16	0	0
T3	270594	16730	0	0
T7	143120	7854	0	0
T8	70145	2804	0	0
T9	9410	850	0	0
T10	32334	1533	0	0
T11	149024	37391	0	0
T12	1684	35	0	0
T13	116864	20033	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210719	0	0
T1	10903	95	0	0
T2	1395	6	0	0
T3	270594	414	0	0
T7	143120	80	0	0
T8	70145	171	0	0
T9	9410	149	0	0
T10	32334	57	0	0
T11	149024	111	0	0
T12	1684	8	0	0
T13	116864	222	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210719	0	0
T1	10903	95	0	0
T2	1395	6	0	0
T3	270594	414	0	0
T7	143120	80	0	0
T8	70145	171	0	0
T9	9410	149	0	0
T10	32334	57	0	0
T11	149024	111	0	0
T12	1684	8	0	0
T13	116864	222	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	967331	0	0
T1	10903	138	0	0
T2	1395	10	0	0
T3	270594	1247	0	0
T7	143120	367	0	0
T8	70145	327	0	0
T9	9410	274	0	0
T10	32334	68	0	0
T11	149024	2626	0	0
T12	1684	8	0	0
T13	116864	2928	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210719	0	0
T1	10903	95	0	0
T2	1395	6	0	0
T3	270594	414	0	0
T7	143120	80	0	0
T8	70145	171	0	0
T9	9410	149	0	0
T10	32334	57	0	0
T11	149024	111	0	0
T12	1684	8	0	0
T13	116864	222	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	204680	0	0
GntImpliesValid_A	456130957	204680	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	204680	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3071998	0	0
ReadyAndValidImplyGrant_A	456130957	204680	0	0
ReqAndReadyImplyGrant_A	456130957	204680	0	0
ReqImpliesValid_A	456130957	527505	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	204680	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204680	0	0
T1	10903	94	0	0
T2	1395	7	0	0
T3	270594	395	0	0
T7	143120	80	0	0
T8	70145	170	0	0
T9	9410	159	0	0
T10	32334	61	0	0
T11	149024	105	0	0
T12	1684	12	0	0
T13	116864	258	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204680	0	0
T1	10903	94	0	0
T2	1395	7	0	0
T3	270594	395	0	0
T7	143120	80	0	0
T8	70145	170	0	0
T9	9410	159	0	0
T10	32334	61	0	0
T11	149024	105	0	0
T12	1684	12	0	0
T13	116864	258	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204680	0	0
T1	10903	94	0	0
T2	1395	7	0	0
T3	270594	395	0	0
T7	143120	80	0	0
T8	70145	170	0	0
T9	9410	159	0	0
T10	32334	61	0	0
T11	149024	105	0	0
T12	1684	12	0	0
T13	116864	258	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3071998	0	0
T1	10903	89	0	0
T2	1395	8	0	0
T3	270594	3197	0	0
T7	143120	28420	0	0
T8	70145	1278	0	0
T9	9410	152	0	0
T10	32334	487	0	0
T11	149024	35507	0	0
T12	1684	13	0	0
T13	116864	1952	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204680	0	0
T1	10903	94	0	0
T2	1395	7	0	0
T3	270594	395	0	0
T7	143120	80	0	0
T8	70145	170	0	0
T9	9410	159	0	0
T10	32334	61	0	0
T11	149024	105	0	0
T12	1684	12	0	0
T13	116864	258	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204680	0	0
T1	10903	94	0	0
T2	1395	7	0	0
T3	270594	395	0	0
T7	143120	80	0	0
T8	70145	170	0	0
T9	9410	159	0	0
T10	32334	61	0	0
T11	149024	105	0	0
T12	1684	12	0	0
T13	116864	258	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	527505	0	0
T1	10903	100	0	0
T2	1395	7	0	0
T3	270594	459	0	0
T7	143120	2382	0	0
T8	70145	271	0	0
T9	9410	167	0	0
T10	32334	63	0	0
T11	149024	2637	0	0
T12	1684	12	0	0
T13	116864	328	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204680	0	0
T1	10903	94	0	0
T2	1395	7	0	0
T3	270594	395	0	0
T7	143120	80	0	0
T8	70145	170	0	0
T9	9410	159	0	0
T10	32334	61	0	0
T11	149024	105	0	0
T12	1684	12	0	0
T13	116864	258	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	207506	0	0
GntImpliesValid_A	456130957	207506	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	207506	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3121149	0	0
ReadyAndValidImplyGrant_A	456130957	207506	0	0
ReqAndReadyImplyGrant_A	456130957	207506	0	0
ReqImpliesValid_A	456130957	533783	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	207506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	124	0	0
T2	1395	7	0	0
T3	270594	935	0	0
T7	143120	67	0	0
T8	70145	172	0	0
T9	9410	132	0	0
T10	32334	47	0	0
T11	149024	111	0	0
T12	1684	7	0	0
T13	116864	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	124	0	0
T2	1395	7	0	0
T3	270594	935	0	0
T7	143120	67	0	0
T8	70145	172	0	0
T9	9410	132	0	0
T10	32334	47	0	0
T11	149024	111	0	0
T12	1684	7	0	0
T13	116864	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	124	0	0
T2	1395	7	0	0
T3	270594	935	0	0
T7	143120	67	0	0
T8	70145	172	0	0
T9	9410	132	0	0
T10	32334	47	0	0
T11	149024	111	0	0
T12	1684	7	0	0
T13	116864	236	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3121149	0	0
T1	10903	119	0	0
T2	1395	8	0	0
T3	270594	5978	0	0
T7	143120	22203	0	0
T8	70145	1193	0	0
T9	9410	124	0	0
T10	32334	371	0	0
T11	149024	38621	0	0
T12	1684	8	0	0
T13	116864	1701	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	124	0	0
T2	1395	7	0	0
T3	270594	935	0	0
T7	143120	67	0	0
T8	70145	172	0	0
T9	9410	132	0	0
T10	32334	47	0	0
T11	149024	111	0	0
T12	1684	7	0	0
T13	116864	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	124	0	0
T2	1395	7	0	0
T3	270594	935	0	0
T7	143120	67	0	0
T8	70145	172	0	0
T9	9410	132	0	0
T10	32334	47	0	0
T11	149024	111	0	0
T12	1684	7	0	0
T13	116864	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	533783	0	0
T1	10903	130	0	0
T2	1395	7	0	0
T3	270594	2769	0	0
T7	143120	986	0	0
T8	70145	224	0	0
T9	9410	141	0	0
T10	32334	75	0	0
T11	149024	2985	0	0
T12	1684	7	0	0
T13	116864	315	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	207506	0	0
T1	10903	124	0	0
T2	1395	7	0	0
T3	270594	935	0	0
T7	143120	67	0	0
T8	70145	172	0	0
T9	9410	132	0	0
T10	32334	47	0	0
T11	149024	111	0	0
T12	1684	7	0	0
T13	116864	236	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	200309	0	0
GntImpliesValid_A	456130957	200309	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	200309	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3126994	0	0
ReadyAndValidImplyGrant_A	456130957	200309	0	0
ReqAndReadyImplyGrant_A	456130957	200309	0	0
ReqImpliesValid_A	456130957	521624	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	200309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	200309	0	0
T1	10903	107	0	0
T2	1395	11	0	0
T3	270594	893	0	0
T7	143120	66	0	0
T8	70145	187	0	0
T9	9410	133	0	0
T10	32334	99	0	0
T11	149024	123	0	0
T12	1684	8	0	0
T13	116864	228	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	200309	0	0
T1	10903	107	0	0
T2	1395	11	0	0
T3	270594	893	0	0
T7	143120	66	0	0
T8	70145	187	0	0
T9	9410	133	0	0
T10	32334	99	0	0
T11	149024	123	0	0
T12	1684	8	0	0
T13	116864	228	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	200309	0	0
T1	10903	107	0	0
T2	1395	11	0	0
T3	270594	893	0	0
T7	143120	66	0	0
T8	70145	187	0	0
T9	9410	133	0	0
T10	32334	99	0	0
T11	149024	123	0	0
T12	1684	8	0	0
T13	116864	228	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3126994	0	0
T1	10903	102	0	0
T2	1395	11	0	0
T3	270594	6478	0	0
T7	143120	18949	0	0
T8	70145	1441	0	0
T9	9410	123	0	0
T10	32334	442	0	0
T11	149024	35802	0	0
T12	1684	9	0	0
T13	116864	1671	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	200309	0	0
T1	10903	107	0	0
T2	1395	11	0	0
T3	270594	893	0	0
T7	143120	66	0	0
T8	70145	187	0	0
T9	9410	133	0	0
T10	32334	99	0	0
T11	149024	123	0	0
T12	1684	8	0	0
T13	116864	228	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	200309	0	0
T1	10903	107	0	0
T2	1395	11	0	0
T3	270594	893	0	0
T7	143120	66	0	0
T8	70145	187	0	0
T9	9410	133	0	0
T10	32334	99	0	0
T11	149024	123	0	0
T12	1684	8	0	0
T13	116864	228	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	521624	0	0
T1	10903	113	0	0
T2	1395	12	0	0
T3	270594	1954	0	0
T7	143120	1344	0	0
T8	70145	238	0	0
T9	9410	144	0	0
T10	32334	359	0	0
T11	149024	2118	0	0
T12	1684	8	0	0
T13	116864	297	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	200309	0	0
T1	10903	107	0	0
T2	1395	11	0	0
T3	270594	893	0	0
T7	143120	66	0	0
T8	70145	187	0	0
T9	9410	133	0	0
T10	32334	99	0	0
T11	149024	123	0	0
T12	1684	8	0	0
T13	116864	228	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	206138	0	0
GntImpliesValid_A	456130957	206138	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	206138	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3127100	0	0
ReadyAndValidImplyGrant_A	456130957	206138	0	0
ReqAndReadyImplyGrant_A	456130957	206138	0	0
ReqImpliesValid_A	456130957	561829	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	206138	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	206138	0	0
T1	10903	100	0	0
T2	1395	10	0	0
T3	270594	423	0	0
T7	143120	97	0	0
T8	70145	165	0	0
T9	9410	161	0	0
T10	32334	62	0	0
T11	149024	113	0	0
T12	1684	16	0	0
T13	116864	275	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	206138	0	0
T1	10903	100	0	0
T2	1395	10	0	0
T3	270594	423	0	0
T7	143120	97	0	0
T8	70145	165	0	0
T9	9410	161	0	0
T10	32334	62	0	0
T11	149024	113	0	0
T12	1684	16	0	0
T13	116864	275	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	206138	0	0
T1	10903	100	0	0
T2	1395	10	0	0
T3	270594	423	0	0
T7	143120	97	0	0
T8	70145	165	0	0
T9	9410	161	0	0
T10	32334	62	0	0
T11	149024	113	0	0
T12	1684	16	0	0
T13	116864	275	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3127100	0	0
T1	10903	96	0	0
T2	1395	11	0	0
T3	270594	3118	0	0
T7	143120	30568	0	0
T8	70145	1150	0	0
T9	9410	148	0	0
T10	32334	507	0	0
T11	149024	36814	0	0
T12	1684	17	0	0
T13	116864	2184	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	206138	0	0
T1	10903	100	0	0
T2	1395	10	0	0
T3	270594	423	0	0
T7	143120	97	0	0
T8	70145	165	0	0
T9	9410	161	0	0
T10	32334	62	0	0
T11	149024	113	0	0
T12	1684	16	0	0
T13	116864	275	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	206138	0	0
T1	10903	100	0	0
T2	1395	10	0	0
T3	270594	423	0	0
T7	143120	97	0	0
T8	70145	165	0	0
T9	9410	161	0	0
T10	32334	62	0	0
T11	149024	113	0	0
T12	1684	16	0	0
T13	116864	275	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	561829	0	0
T1	10903	105	0	0
T2	1395	10	0	0
T3	270594	478	0	0
T7	143120	1197	0	0
T8	70145	260	0	0
T9	9410	175	0	0
T10	32334	71	0	0
T11	149024	1763	0	0
T12	1684	16	0	0
T13	116864	401	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	206138	0	0
T1	10903	100	0	0
T2	1395	10	0	0
T3	270594	423	0	0
T7	143120	97	0	0
T8	70145	165	0	0
T9	9410	161	0	0
T10	32334	62	0	0
T11	149024	113	0	0
T12	1684	16	0	0
T13	116864	275	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	211075	0	0
GntImpliesValid_A	456130957	211075	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	211075	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3181124	0	0
ReadyAndValidImplyGrant_A	456130957	211075	0	0
ReqAndReadyImplyGrant_A	456130957	211075	0	0
ReqImpliesValid_A	456130957	542031	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	211075	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211075	0	0
T1	10903	106	0	0
T2	1395	10	0	0
T3	270594	370	0	0
T7	143120	68	0	0
T8	70145	162	0	0
T9	9410	127	0	0
T10	32334	74	0	0
T11	149024	123	0	0
T12	1684	14	0	0
T13	116864	239	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211075	0	0
T1	10903	106	0	0
T2	1395	10	0	0
T3	270594	370	0	0
T7	143120	68	0	0
T8	70145	162	0	0
T9	9410	127	0	0
T10	32334	74	0	0
T11	149024	123	0	0
T12	1684	14	0	0
T13	116864	239	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211075	0	0
T1	10903	106	0	0
T2	1395	10	0	0
T3	270594	370	0	0
T7	143120	68	0	0
T8	70145	162	0	0
T9	9410	127	0	0
T10	32334	74	0	0
T11	149024	123	0	0
T12	1684	14	0	0
T13	116864	239	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3181124	0	0
T1	10903	105	0	0
T2	1395	11	0	0
T3	270594	2865	0	0
T7	143120	25662	0	0
T8	70145	1182	0	0
T9	9410	116	0	0
T10	32334	607	0	0
T11	149024	39705	0	0
T12	1684	15	0	0
T13	116864	1786	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211075	0	0
T1	10903	106	0	0
T2	1395	10	0	0
T3	270594	370	0	0
T7	143120	68	0	0
T8	70145	162	0	0
T9	9410	127	0	0
T10	32334	74	0	0
T11	149024	123	0	0
T12	1684	14	0	0
T13	116864	239	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211075	0	0
T1	10903	106	0	0
T2	1395	10	0	0
T3	270594	370	0	0
T7	143120	68	0	0
T8	70145	162	0	0
T9	9410	127	0	0
T10	32334	74	0	0
T11	149024	123	0	0
T12	1684	14	0	0
T13	116864	239	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	542031	0	0
T1	10903	108	0	0
T2	1395	10	0	0
T3	270594	433	0	0
T7	143120	678	0	0
T8	70145	214	0	0
T9	9410	139	0	0
T10	32334	113	0	0
T11	149024	1803	0	0
T12	1684	14	0	0
T13	116864	331	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	211075	0	0
T1	10903	106	0	0
T2	1395	10	0	0
T3	270594	370	0	0
T7	143120	68	0	0
T8	70145	162	0	0
T9	9410	127	0	0
T10	32334	74	0	0
T11	149024	123	0	0
T12	1684	14	0	0
T13	116864	239	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	204646	0	0
GntImpliesValid_A	456130957	204646	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	204646	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3016212	0	0
ReadyAndValidImplyGrant_A	456130957	204646	0	0
ReqAndReadyImplyGrant_A	456130957	204646	0	0
ReqImpliesValid_A	456130957	536627	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	204646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204646	0	0
T1	10903	99	0	0
T2	1395	10	0	0
T3	270594	443	0	0
T7	143120	75	0	0
T8	70145	173	0	0
T9	9410	149	0	0
T10	32334	53	0	0
T11	149024	127	0	0
T12	1684	7	0	0
T13	116864	228	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204646	0	0
T1	10903	99	0	0
T2	1395	10	0	0
T3	270594	443	0	0
T7	143120	75	0	0
T8	70145	173	0	0
T9	9410	149	0	0
T10	32334	53	0	0
T11	149024	127	0	0
T12	1684	7	0	0
T13	116864	228	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204646	0	0
T1	10903	99	0	0
T2	1395	10	0	0
T3	270594	443	0	0
T7	143120	75	0	0
T8	70145	173	0	0
T9	9410	149	0	0
T10	32334	53	0	0
T11	149024	127	0	0
T12	1684	7	0	0
T13	116864	228	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3016212	0	0
T1	10903	99	0	0
T2	1395	9	0	0
T3	270594	3346	0	0
T7	143120	25170	0	0
T8	70145	1137	0	0
T9	9410	142	0	0
T10	32334	412	0	0
T11	149024	32535	0	0
T12	1684	8	0	0
T13	116864	1552	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204646	0	0
T1	10903	99	0	0
T2	1395	10	0	0
T3	270594	443	0	0
T7	143120	75	0	0
T8	70145	173	0	0
T9	9410	149	0	0
T10	32334	53	0	0
T11	149024	127	0	0
T12	1684	7	0	0
T13	116864	228	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204646	0	0
T1	10903	99	0	0
T2	1395	10	0	0
T3	270594	443	0	0
T7	143120	75	0	0
T8	70145	173	0	0
T9	9410	149	0	0
T10	32334	53	0	0
T11	149024	127	0	0
T12	1684	7	0	0
T13	116864	228	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	536627	0	0
T1	10903	100	0	0
T2	1395	12	0	0
T3	270594	583	0	0
T7	143120	1457	0	0
T8	70145	230	0	0
T9	9410	157	0	0
T10	32334	62	0	0
T11	149024	3329	0	0
T12	1684	7	0	0
T13	116864	283	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204646	0	0
T1	10903	99	0	0
T2	1395	10	0	0
T3	270594	443	0	0
T7	143120	75	0	0
T8	70145	173	0	0
T9	9410	149	0	0
T10	32334	53	0	0
T11	149024	127	0	0
T12	1684	7	0	0
T13	116864	228	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	215476	0	0
GntImpliesValid_A	456130957	215476	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	215476	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3155224	0	0
ReadyAndValidImplyGrant_A	456130957	215476	0	0
ReqAndReadyImplyGrant_A	456130957	215476	0	0
ReqImpliesValid_A	456130957	596343	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	215476	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	215476	0	0
T1	10903	98	0	0
T2	1395	8	0	0
T3	270594	414	0	0
T7	143120	76	0	0
T8	70145	172	0	0
T9	9410	126	0	0
T10	32334	51	0	0
T11	149024	115	0	0
T12	1684	12	0	0
T13	116864	243	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	215476	0	0
T1	10903	98	0	0
T2	1395	8	0	0
T3	270594	414	0	0
T7	143120	76	0	0
T8	70145	172	0	0
T9	9410	126	0	0
T10	32334	51	0	0
T11	149024	115	0	0
T12	1684	12	0	0
T13	116864	243	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	215476	0	0
T1	10903	98	0	0
T2	1395	8	0	0
T3	270594	414	0	0
T7	143120	76	0	0
T8	70145	172	0	0
T9	9410	126	0	0
T10	32334	51	0	0
T11	149024	115	0	0
T12	1684	12	0	0
T13	116864	243	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3155224	0	0
T1	10903	93	0	0
T2	1395	8	0	0
T3	270594	3084	0	0
T7	143120	25724	0	0
T8	70145	1183	0	0
T9	9410	120	0	0
T10	32334	419	0	0
T11	149024	38067	0	0
T12	1684	12	0	0
T13	116864	1795	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	215476	0	0
T1	10903	98	0	0
T2	1395	8	0	0
T3	270594	414	0	0
T7	143120	76	0	0
T8	70145	172	0	0
T9	9410	126	0	0
T10	32334	51	0	0
T11	149024	115	0	0
T12	1684	12	0	0
T13	116864	243	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	215476	0	0
T1	10903	98	0	0
T2	1395	8	0	0
T3	270594	414	0	0
T7	143120	76	0	0
T8	70145	172	0	0
T9	9410	126	0	0
T10	32334	51	0	0
T11	149024	115	0	0
T12	1684	12	0	0
T13	116864	243	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	596343	0	0
T1	10903	104	0	0
T2	1395	9	0	0
T3	270594	503	0	0
T7	143120	2107	0	0
T8	70145	261	0	0
T9	9410	133	0	0
T10	32334	62	0	0
T11	149024	3797	0	0
T12	1684	13	0	0
T13	116864	344	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	215476	0	0
T1	10903	98	0	0
T2	1395	8	0	0
T3	270594	414	0	0
T7	143120	76	0	0
T8	70145	172	0	0
T9	9410	126	0	0
T10	32334	51	0	0
T11	149024	115	0	0
T12	1684	12	0	0
T13	116864	243	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	217829	0	0
GntImpliesValid_A	456130957	217829	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	217829	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3129046	0	0
ReadyAndValidImplyGrant_A	456130957	217829	0	0
ReqAndReadyImplyGrant_A	456130957	217829	0	0
ReqImpliesValid_A	456130957	570894	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	217829	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	217829	0	0
T1	10903	127	0	0
T2	1395	15	0	0
T3	270594	398	0	0
T7	143120	71	0	0
T8	70145	177	0	0
T9	9410	170	0	0
T10	32334	54	0	0
T11	149024	95	0	0
T12	1684	10	0	0
T13	116864	261	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	217829	0	0
T1	10903	127	0	0
T2	1395	15	0	0
T3	270594	398	0	0
T7	143120	71	0	0
T8	70145	177	0	0
T9	9410	170	0	0
T10	32334	54	0	0
T11	149024	95	0	0
T12	1684	10	0	0
T13	116864	261	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	217829	0	0
T1	10903	127	0	0
T2	1395	15	0	0
T3	270594	398	0	0
T7	143120	71	0	0
T8	70145	177	0	0
T9	9410	170	0	0
T10	32334	54	0	0
T11	149024	95	0	0
T12	1684	10	0	0
T13	116864	261	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3129046	0	0
T1	10903	122	0	0
T2	1395	16	0	0
T3	270594	2972	0	0
T7	143120	23575	0	0
T8	70145	1230	0	0
T9	9410	164	0	0
T10	32334	371	0	0
T11	149024	27644	0	0
T12	1684	10	0	0
T13	116864	1948	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	217829	0	0
T1	10903	127	0	0
T2	1395	15	0	0
T3	270594	398	0	0
T7	143120	71	0	0
T8	70145	177	0	0
T9	9410	170	0	0
T10	32334	54	0	0
T11	149024	95	0	0
T12	1684	10	0	0
T13	116864	261	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	217829	0	0
T1	10903	127	0	0
T2	1395	15	0	0
T3	270594	398	0	0
T7	143120	71	0	0
T8	70145	177	0	0
T9	9410	170	0	0
T10	32334	54	0	0
T11	149024	95	0	0
T12	1684	10	0	0
T13	116864	261	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	570894	0	0
T1	10903	133	0	0
T2	1395	15	0	0
T3	270594	427	0	0
T7	143120	1964	0	0
T8	70145	248	0	0
T9	9410	177	0	0
T10	32334	70	0	0
T11	149024	973	0	0
T12	1684	11	0	0
T13	116864	376	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	217829	0	0
T1	10903	127	0	0
T2	1395	15	0	0
T3	270594	398	0	0
T7	143120	71	0	0
T8	70145	177	0	0
T9	9410	170	0	0
T10	32334	54	0	0
T11	149024	95	0	0
T12	1684	10	0	0
T13	116864	261	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	230717	0	0
GntImpliesValid_A	456130957	230717	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	230717	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3219931	0	0
ReadyAndValidImplyGrant_A	456130957	230717	0	0
ReqAndReadyImplyGrant_A	456130957	230717	0	0
ReqImpliesValid_A	456130957	609391	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	230717	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	230717	0	0
T1	10903	165	0	0
T2	1395	5	0	0
T3	270594	526	0	0
T7	143120	86	0	0
T8	70145	166	0	0
T9	9410	123	0	0
T10	32334	362	0	0
T11	149024	120	0	0
T12	1684	8	0	0
T13	116864	247	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	230717	0	0
T1	10903	165	0	0
T2	1395	5	0	0
T3	270594	526	0	0
T7	143120	86	0	0
T8	70145	166	0	0
T9	9410	123	0	0
T10	32334	362	0	0
T11	149024	120	0	0
T12	1684	8	0	0
T13	116864	247	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	230717	0	0
T1	10903	165	0	0
T2	1395	5	0	0
T3	270594	526	0	0
T7	143120	86	0	0
T8	70145	166	0	0
T9	9410	123	0	0
T10	32334	362	0	0
T11	149024	120	0	0
T12	1684	8	0	0
T13	116864	247	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3219931	0	0
T1	10903	159	0	0
T2	1395	6	0	0
T3	270594	4299	0	0
T7	143120	30886	0	0
T8	70145	1240	0	0
T9	9410	118	0	0
T10	32334	2237	0	0
T11	149024	38969	0	0
T12	1684	9	0	0
T13	116864	1786	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	230717	0	0
T1	10903	165	0	0
T2	1395	5	0	0
T3	270594	526	0	0
T7	143120	86	0	0
T8	70145	166	0	0
T9	9410	123	0	0
T10	32334	362	0	0
T11	149024	120	0	0
T12	1684	8	0	0
T13	116864	247	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	230717	0	0
T1	10903	165	0	0
T2	1395	5	0	0
T3	270594	526	0	0
T7	143120	86	0	0
T8	70145	166	0	0
T9	9410	123	0	0
T10	32334	362	0	0
T11	149024	120	0	0
T12	1684	8	0	0
T13	116864	247	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	609391	0	0
T1	10903	172	0	0
T2	1395	5	0	0
T3	270594	588	0	0
T7	143120	1984	0	0
T8	70145	192	0	0
T9	9410	129	0	0
T10	32334	1213	0	0
T11	149024	2467	0	0
T12	1684	8	0	0
T13	116864	366	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	230717	0	0
T1	10903	165	0	0
T2	1395	5	0	0
T3	270594	526	0	0
T7	143120	86	0	0
T8	70145	166	0	0
T9	9410	123	0	0
T10	32334	362	0	0
T11	149024	120	0	0
T12	1684	8	0	0
T13	116864	247	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	210295	0	0
GntImpliesValid_A	456130957	210295	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	210295	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3153871	0	0
ReadyAndValidImplyGrant_A	456130957	210295	0	0
ReqAndReadyImplyGrant_A	456130957	210295	0	0
ReqImpliesValid_A	456130957	540458	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	210295	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210295	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	847	0	0
T7	143120	68	0	0
T8	70145	184	0	0
T9	9410	132	0	0
T10	32334	54	0	0
T11	149024	111	0	0
T12	1684	18	0	0
T13	116864	220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210295	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	847	0	0
T7	143120	68	0	0
T8	70145	184	0	0
T9	9410	132	0	0
T10	32334	54	0	0
T11	149024	111	0	0
T12	1684	18	0	0
T13	116864	220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210295	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	847	0	0
T7	143120	68	0	0
T8	70145	184	0	0
T9	9410	132	0	0
T10	32334	54	0	0
T11	149024	111	0	0
T12	1684	18	0	0
T13	116864	220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3153871	0	0
T1	10903	106	0	0
T2	1395	12	0	0
T3	270594	3388	0	0
T7	143120	20806	0	0
T8	70145	1278	0	0
T9	9410	130	0	0
T10	32334	495	0	0
T11	149024	40681	0	0
T12	1684	18	0	0
T13	116864	1602	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210295	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	847	0	0
T7	143120	68	0	0
T8	70145	184	0	0
T9	9410	132	0	0
T10	32334	54	0	0
T11	149024	111	0	0
T12	1684	18	0	0
T13	116864	220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210295	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	847	0	0
T7	143120	68	0	0
T8	70145	184	0	0
T9	9410	132	0	0
T10	32334	54	0	0
T11	149024	111	0	0
T12	1684	18	0	0
T13	116864	220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	540458	0	0
T1	10903	121	0	0
T2	1395	11	0	0
T3	270594	5159	0	0
T7	143120	1242	0	0
T8	70145	304	0	0
T9	9410	135	0	0
T10	32334	69	0	0
T11	149024	1840	0	0
T12	1684	19	0	0
T13	116864	276	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	210295	0	0
T1	10903	113	0	0
T2	1395	11	0	0
T3	270594	847	0	0
T7	143120	68	0	0
T8	70145	184	0	0
T9	9410	132	0	0
T10	32334	54	0	0
T11	149024	111	0	0
T12	1684	18	0	0
T13	116864	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	204903	0	0
GntImpliesValid_A	456130957	204903	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	204903	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3123651	0	0
ReadyAndValidImplyGrant_A	456130957	204903	0	0
ReqAndReadyImplyGrant_A	456130957	204903	0	0
ReqImpliesValid_A	456130957	522293	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	204903	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204903	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	894	0	0
T7	143120	68	0	0
T8	70145	186	0	0
T9	9410	153	0	0
T10	32334	53	0	0
T11	149024	125	0	0
T12	1684	18	0	0
T13	116864	222	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204903	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	894	0	0
T7	143120	68	0	0
T8	70145	186	0	0
T9	9410	153	0	0
T10	32334	53	0	0
T11	149024	125	0	0
T12	1684	18	0	0
T13	116864	222	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204903	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	894	0	0
T7	143120	68	0	0
T8	70145	186	0	0
T9	9410	153	0	0
T10	32334	53	0	0
T11	149024	125	0	0
T12	1684	18	0	0
T13	116864	222	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3123651	0	0
T1	10903	108	0	0
T2	1395	15	0	0
T3	270594	6119	0	0
T7	143120	23682	0	0
T8	70145	1373	0	0
T9	9410	147	0	0
T10	32334	376	0	0
T11	149024	42645	0	0
T12	1684	19	0	0
T13	116864	1654	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204903	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	894	0	0
T7	143120	68	0	0
T8	70145	186	0	0
T9	9410	153	0	0
T10	32334	53	0	0
T11	149024	125	0	0
T12	1684	18	0	0
T13	116864	222	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204903	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	894	0	0
T7	143120	68	0	0
T8	70145	186	0	0
T9	9410	153	0	0
T10	32334	53	0	0
T11	149024	125	0	0
T12	1684	18	0	0
T13	116864	222	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	522293	0	0
T1	10903	113	0	0
T2	1395	14	0	0
T3	270594	1600	0	0
T7	143120	388	0	0
T8	70145	300	0	0
T9	9410	160	0	0
T10	32334	54	0	0
T11	149024	1397	0	0
T12	1684	18	0	0
T13	116864	292	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	204903	0	0
T1	10903	110	0	0
T2	1395	14	0	0
T3	270594	894	0	0
T7	143120	68	0	0
T8	70145	186	0	0
T9	9410	153	0	0
T10	32334	53	0	0
T11	149024	125	0	0
T12	1684	18	0	0
T13	116864	222	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	214845	0	0
GntImpliesValid_A	456130957	214845	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	214845	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3053063	0	0
ReadyAndValidImplyGrant_A	456130957	214845	0	0
ReqAndReadyImplyGrant_A	456130957	214845	0	0
ReqImpliesValid_A	456130957	547305	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	214845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	214845	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	1327	0	0
T7	143120	85	0	0
T8	70145	173	0	0
T9	9410	134	0	0
T10	32334	354	0	0
T11	149024	134	0	0
T12	1684	15	0	0
T13	116864	261	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	214845	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	1327	0	0
T7	143120	85	0	0
T8	70145	173	0	0
T9	9410	134	0	0
T10	32334	354	0	0
T11	149024	134	0	0
T12	1684	15	0	0
T13	116864	261	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	214845	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	1327	0	0
T7	143120	85	0	0
T8	70145	173	0	0
T9	9410	134	0	0
T10	32334	354	0	0
T11	149024	134	0	0
T12	1684	15	0	0
T13	116864	261	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3053063	0	0
T1	10903	123	0	0
T2	1395	7	0	0
T3	270594	8021	0	0
T7	143120	30367	0	0
T8	70145	1285	0	0
T9	9410	124	0	0
T10	32334	2115	0	0
T11	149024	39679	0	0
T12	1684	16	0	0
T13	116864	1978	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	214845	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	1327	0	0
T7	143120	85	0	0
T8	70145	173	0	0
T9	9410	134	0	0
T10	32334	354	0	0
T11	149024	134	0	0
T12	1684	15	0	0
T13	116864	261	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	214845	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	1327	0	0
T7	143120	85	0	0
T8	70145	173	0	0
T9	9410	134	0	0
T10	32334	354	0	0
T11	149024	134	0	0
T12	1684	15	0	0
T13	116864	261	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	547305	0	0
T1	10903	126	0	0
T2	1395	6	0	0
T3	270594	2858	0	0
T7	143120	974	0	0
T8	70145	214	0	0
T9	9410	145	0	0
T10	32334	679	0	0
T11	149024	2774	0	0
T12	1684	15	0	0
T13	116864	359	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	214845	0	0
T1	10903	124	0	0
T2	1395	6	0	0
T3	270594	1327	0	0
T7	143120	85	0	0
T8	70145	173	0	0
T9	9410	134	0	0
T10	32334	354	0	0
T11	149024	134	0	0
T12	1684	15	0	0
T13	116864	261	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	212316	0	0
GntImpliesValid_A	456130957	212316	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	212316	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3106256	0	0
ReadyAndValidImplyGrant_A	456130957	212316	0	0
ReqAndReadyImplyGrant_A	456130957	212316	0	0
ReqImpliesValid_A	456130957	548736	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	212316	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	212316	0	0
T1	10903	112	0	0
T2	1395	12	0	0
T3	270594	909	0	0
T7	143120	72	0	0
T8	70145	181	0	0
T9	9410	155	0	0
T10	32334	39	0	0
T11	149024	114	0	0
T12	1684	11	0	0
T13	116864	229	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	212316	0	0
T1	10903	112	0	0
T2	1395	12	0	0
T3	270594	909	0	0
T7	143120	72	0	0
T8	70145	181	0	0
T9	9410	155	0	0
T10	32334	39	0	0
T11	149024	114	0	0
T12	1684	11	0	0
T13	116864	229	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	212316	0	0
T1	10903	112	0	0
T2	1395	12	0	0
T3	270594	909	0	0
T7	143120	72	0	0
T8	70145	181	0	0
T9	9410	155	0	0
T10	32334	39	0	0
T11	149024	114	0	0
T12	1684	11	0	0
T13	116864	229	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3106256	0	0
T1	10903	107	0	0
T2	1395	13	0	0
T3	270594	6008	0	0
T7	143120	23819	0	0
T8	70145	1352	0	0
T9	9410	151	0	0
T10	32334	285	0	0
T11	149024	37995	0	0
T12	1684	11	0	0
T13	116864	1781	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	212316	0	0
T1	10903	112	0	0
T2	1395	12	0	0
T3	270594	909	0	0
T7	143120	72	0	0
T8	70145	181	0	0
T9	9410	155	0	0
T10	32334	39	0	0
T11	149024	114	0	0
T12	1684	11	0	0
T13	116864	229	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	212316	0	0
T1	10903	112	0	0
T2	1395	12	0	0
T3	270594	909	0	0
T7	143120	72	0	0
T8	70145	181	0	0
T9	9410	155	0	0
T10	32334	39	0	0
T11	149024	114	0	0
T12	1684	11	0	0
T13	116864	229	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	548736	0	0
T1	10903	118	0	0
T2	1395	12	0	0
T3	270594	2444	0	0
T7	143120	1774	0	0
T8	70145	217	0	0
T9	9410	160	0	0
T10	32334	39	0	0
T11	149024	3512	0	0
T12	1684	12	0	0
T13	116864	318	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	212316	0	0
T1	10903	112	0	0
T2	1395	12	0	0
T3	270594	909	0	0
T7	143120	72	0	0
T8	70145	181	0	0
T9	9410	155	0	0
T10	32334	39	0	0
T11	149024	114	0	0
T12	1684	11	0	0
T13	116864	229	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	222092	0	0
GntImpliesValid_A	456130957	222092	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	222092	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	3188512	0	0
ReadyAndValidImplyGrant_A	456130957	222092	0	0
ReqAndReadyImplyGrant_A	456130957	222092	0	0
ReqImpliesValid_A	456130957	571409	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	0	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	222092	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	222092	0	0
T1	10903	96	0	0
T2	1395	6	0	0
T3	270594	1521	0	0
T7	143120	71	0	0
T8	70145	188	0	0
T9	9410	134	0	0
T10	32334	43	0	0
T11	149024	102	0	0
T12	1684	17	0	0
T13	116864	265	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	222092	0	0
T1	10903	96	0	0
T2	1395	6	0	0
T3	270594	1521	0	0
T7	143120	71	0	0
T8	70145	188	0	0
T9	9410	134	0	0
T10	32334	43	0	0
T11	149024	102	0	0
T12	1684	17	0	0
T13	116864	265	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	222092	0	0
T1	10903	96	0	0
T2	1395	6	0	0
T3	270594	1521	0	0
T7	143120	71	0	0
T8	70145	188	0	0
T9	9410	134	0	0
T10	32334	43	0	0
T11	149024	102	0	0
T12	1684	17	0	0
T13	116864	265	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	3188512	0	0
T1	10903	95	0	0
T2	1395	7	0	0
T3	270594	9589	0	0
T7	143120	26316	0	0
T8	70145	1496	0	0
T9	9410	124	0	0
T10	32334	341	0	0
T11	149024	35285	0	0
T12	1684	17	0	0
T13	116864	1781	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	222092	0	0
T1	10903	96	0	0
T2	1395	6	0	0
T3	270594	1521	0	0
T7	143120	71	0	0
T8	70145	188	0	0
T9	9410	134	0	0
T10	32334	43	0	0
T11	149024	102	0	0
T12	1684	17	0	0
T13	116864	265	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	222092	0	0
T1	10903	96	0	0
T2	1395	6	0	0
T3	270594	1521	0	0
T7	143120	71	0	0
T8	70145	188	0	0
T9	9410	134	0	0
T10	32334	43	0	0
T11	149024	102	0	0
T12	1684	17	0	0
T13	116864	265	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	571409	0	0
T1	10903	98	0	0
T2	1395	6	0	0
T3	270594	5426	0	0
T7	143120	921	0	0
T8	70145	256	0	0
T9	9410	145	0	0
T10	32334	55	0	0
T11	149024	2248	0	0
T12	1684	18	0	0
T13	116864	349	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	222092	0	0
T1	10903	96	0	0
T2	1395	6	0	0
T3	270594	1521	0	0
T7	143120	71	0	0
T8	70145	188	0	0
T9	9410	134	0	0
T10	32334	43	0	0
T11	149024	102	0	0
T12	1684	17	0	0
T13	116864	265	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	862729	0	0
GntImpliesValid_A	456130957	862729	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	862729	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	11579813	0	0
ReadyAndValidImplyGrant_A	456130957	862729	0	0
ReqAndReadyImplyGrant_A	456130957	862729	0	0
ReqImpliesValid_A	456130957	2339035	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	16856	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	862729	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	862729	0	0
T1	10903	480	0	0
T2	1395	44	0	0
T3	270594	2180	0	0
T7	143120	357	0	0
T8	70145	664	0	0
T9	9410	603	0	0
T10	32334	369	0	0
T11	149024	446	0	0
T12	1684	37	0	0
T13	116864	923	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	862729	0	0
T1	10903	480	0	0
T2	1395	44	0	0
T3	270594	2180	0	0
T7	143120	357	0	0
T8	70145	664	0	0
T9	9410	603	0	0
T10	32334	369	0	0
T11	149024	446	0	0
T12	1684	37	0	0
T13	116864	923	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	862729	0	0
T1	10903	480	0	0
T2	1395	44	0	0
T3	270594	2180	0	0
T7	143120	357	0	0
T8	70145	664	0	0
T9	9410	603	0	0
T10	32334	369	0	0
T11	149024	446	0	0
T12	1684	37	0	0
T13	116864	923	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	11579813	0	0
T1	10903	1	0	0
T2	1395	1	0	0
T3	270594	14488	0	0
T7	143120	118583	0	0
T8	70145	4235	0	0
T9	9410	1	0	0
T10	32334	2377	0	0
T11	149024	148401	0	0
T12	1684	1	0	0
T13	116864	6161	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	862729	0	0
T1	10903	480	0	0
T2	1395	44	0	0
T3	270594	2180	0	0
T7	143120	357	0	0
T8	70145	664	0	0
T9	9410	603	0	0
T10	32334	369	0	0
T11	149024	446	0	0
T12	1684	37	0	0
T13	116864	923	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	862729	0	0
T1	10903	480	0	0
T2	1395	44	0	0
T3	270594	2180	0	0
T7	143120	357	0	0
T8	70145	664	0	0
T9	9410	603	0	0
T10	32334	369	0	0
T11	149024	446	0	0
T12	1684	37	0	0
T13	116864	923	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	2339035	0	0
T1	10903	480	0	0
T2	1395	44	0	0
T3	270594	3094	0	0
T7	143120	11961	0	0
T8	70145	1089	0	0
T9	9410	603	0	0
T10	32334	624	0	0
T11	149024	17276	0	0
T12	1684	37	0	0
T13	116864	1446	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	16856	0	900
T1	10903	11	0	1
T2	1395	0	0	1
T3	270594	0	0	1
T7	143120	0	0	1
T8	70145	0	0	1
T9	9410	16	0	1
T10	32334	0	0	1
T11	149024	0	0	1
T12	1684	0	0	1
T13	116864	1	0	1
T15	0	8	0	0
T16	0	4	0	0
T17	0	13	0	0
T18	0	12	0	0
T19	0	32	0	0
T20	0	1	0	0
T21	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	862729	0	0
T1	10903	480	0	0
T2	1395	44	0	0
T3	270594	2180	0	0
T7	143120	357	0	0
T8	70145	664	0	0
T9	9410	603	0	0
T10	32334	369	0	0
T11	149024	446	0	0
T12	1684	37	0	0
T13	116864	923	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456130957	455998313	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456130957	851088	0	0
GntImpliesValid_A	456130957	851088	0	0
GrantKnown_A	456130957	455998313	0	0
IdxKnown_A	456130957	455998313	0	0
IndexIsCorrect_A	456130957	851088	0	0
LockArbDecision_A	456130957	0	0	0
NoReadyValidNoGrant_A	456130957	382784315	0	0
ReadyAndValidImplyGrant_A	456130957	851088	0	0
ReqAndReadyImplyGrant_A	456130957	851088	0	0
ReqImpliesValid_A	456130957	13723345	0	0
ReqStaysHighUntilGranted0_M	456130957	0	0	0
RoundRobin_A	456130957	21502	0	900
ValidKnown_A	456130957	455998313	0	0
gen_data_port_assertion.DataFlow_A	456130957	851088	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	851088	0	0
T1	10903	404	0	0
T2	1395	57	0	0
T3	270594	2175	0	0
T7	143120	345	0	0
T8	70145	689	0	0
T9	9410	639	0	0
T10	32334	366	0	0
T11	149024	442	0	0
T12	1684	33	0	0
T13	116864	820	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	851088	0	0
T1	10903	404	0	0
T2	1395	57	0	0
T3	270594	2175	0	0
T7	143120	345	0	0
T8	70145	689	0	0
T9	9410	639	0	0
T10	32334	366	0	0
T11	149024	442	0	0
T12	1684	33	0	0
T13	116864	820	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	851088	0	0
T1	10903	404	0	0
T2	1395	57	0	0
T3	270594	2175	0	0
T7	143120	345	0	0
T8	70145	689	0	0
T9	9410	639	0	0
T10	32334	366	0	0
T11	149024	442	0	0
T12	1684	33	0	0
T13	116864	820	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	382784315	0	0
T1	10903	1	0	0
T2	1395	1	0	0
T3	270594	225493	0	0
T7	143120	130060	0	0
T8	70145	58957	0	0
T9	9410	1	0	0
T10	32334	25631	0	0
T11	149024	131889	0	0
T12	1684	1	0	0
T13	116864	100010	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	851088	0	0
T1	10903	404	0	0
T2	1395	57	0	0
T3	270594	2175	0	0
T7	143120	345	0	0
T8	70145	689	0	0
T9	9410	639	0	0
T10	32334	366	0	0
T11	149024	442	0	0
T12	1684	33	0	0
T13	116864	820	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	851088	0	0
T1	10903	404	0	0
T2	1395	57	0	0
T3	270594	2175	0	0
T7	143120	345	0	0
T8	70145	689	0	0
T9	9410	639	0	0
T10	32334	366	0	0
T11	149024	442	0	0
T12	1684	33	0	0
T13	116864	820	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	13723345	0	0
T1	10903	404	0	0
T2	1395	57	0	0
T3	270594	16111	0	0
T7	143120	128051	0	0
T8	70145	5448	0	0
T9	9410	639	0	0
T10	32334	3023	0	0
T11	149024	168777	0	0
T12	1684	33	0	0
T13	116864	7085	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	21502	0	900
T1	10903	3	0	1
T2	1395	0	0	1
T3	270594	0	0	1
T7	143120	0	0	1
T8	70145	0	0	1
T9	9410	10	0	1
T10	32334	0	0	1
T11	149024	0	0	1
T12	1684	0	0	1
T13	116864	1	0	1
T14	0	146	0	0
T15	0	11	0	0
T16	0	2	0	0
T17	0	10	0	0
T18	0	14	0	0
T19	0	36	0	0
T21	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	455998313	0	0
T1	10903	10826	0	0
T2	1395	1379	0	0
T3	270594	270454	0	0
T7	143120	143119	0	0
T8	70145	70097	0	0
T9	9410	9353	0	0
T10	32334	31060	0	0
T11	149024	149016	0	0
T12	1684	1654	0	0
T13	116864	116806	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456130957	851088	0	0
T1	10903	404	0	0
T2	1395	57	0	0
T3	270594	2175	0	0
T7	143120	345	0	0
T8	70145	689	0	0
T9	9410	639	0	0
T10	32334	366	0	0
T11	149024	442	0	0
T12	1684	33	0	0
T13	116864	820	0	0