Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1496516	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238896

1

T1

159

T2

16

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	588282	1			T1	366		T2	40		T3	62
values[0x0]	557794	1			T1	336		T2	39		T3	70
values[0x1]	589336	1			T1	376		T2	47		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1156674	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

578738

1

T1

362

T2

34

T3

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26334	1			T1	18		T3	2		T7	19
valid_sources[0x01]	28114	1			T1	12		T3	5		T7	11
valid_sources[0x02]	27365	1			T1	15		T3	1		T7	12
valid_sources[0x03]	28582	1			T1	14		T3	4		T7	16
valid_sources[0x04]	27763	1			T1	23		T3	1		T7	10
valid_sources[0x05]	27198	1			T1	22		T3	2		T7	10
valid_sources[0x06]	27223	1			T1	9		T3	4		T7	14
valid_sources[0x07]	27465	1			T1	14		T2	7		T3	3
valid_sources[0x08]	25709	1			T1	14		T7	12		T8	2
valid_sources[0x09]	26959	1			T1	25		T3	3		T7	18
valid_sources[0x0a]	28476	1			T1	19		T3	1		T7	13
valid_sources[0x0b]	26256	1			T1	14		T3	7		T7	20
valid_sources[0x0c]	26039	1			T1	18		T3	1		T7	6
valid_sources[0x0d]	27483	1			T1	19		T2	2		T3	2
valid_sources[0x0e]	26317	1			T1	17		T3	8		T7	20
valid_sources[0x0f]	26627	1			T1	15		T7	21		T9	1
valid_sources[0x10]	28022	1			T1	16		T2	12		T3	6
valid_sources[0x11]	27276	1			T1	16		T7	19		T9	2
valid_sources[0x12]	27154	1			T1	22		T2	4		T3	5
valid_sources[0x13]	27219	1			T1	19		T2	3		T3	2
valid_sources[0x14]	26311	1			T1	11		T3	3		T7	20
valid_sources[0x15]	26750	1			T1	17		T2	4		T3	4
valid_sources[0x16]	26402	1			T1	22		T2	2		T7	10
valid_sources[0x17]	27913	1			T1	12		T3	8		T7	15
valid_sources[0x18]	26953	1			T1	14		T3	1		T7	11
valid_sources[0x19]	27068	1			T1	22		T3	4		T7	9
valid_sources[0x1a]	27188	1			T1	17		T2	15		T3	1
valid_sources[0x1b]	26808	1			T1	24		T3	4		T7	20
valid_sources[0x1c]	26950	1			T1	18		T3	1		T7	8
valid_sources[0x1d]	27374	1			T1	17		T3	3		T7	8
valid_sources[0x1e]	27753	1			T1	17		T3	1		T7	12
valid_sources[0x1f]	26931	1			T1	18		T3	2		T7	16
valid_sources[0x20]	27538	1			T1	19		T3	3		T7	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25262

1

T1

18

T2

3

T3

3

values[0x0]

all_enables

biggest_size

188612

1

T1

126

T2

12

T3

29

values[0x1]

all_enables

biggest_size

25022

1

T1

15

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1508939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244684

1

T1

123

T2

22

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	600790	1			T1	298		T2	40		T3	52
values[0x0]	551393	1			T1	277		T2	41		T3	55
values[0x1]	601440	1			T1	315		T2	36		T3	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1157093	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596530

1

T1

302

T2

48

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26670	1			T1	13		T2	1		T7	10
valid_sources[0x01]	28309	1			T1	11		T2	2		T7	15
valid_sources[0x02]	27079	1			T1	13		T2	2		T3	6
valid_sources[0x03]	27714	1			T1	16		T3	15		T7	14
valid_sources[0x04]	27542	1			T1	14		T2	4		T7	16
valid_sources[0x05]	27797	1			T1	12		T7	9		T8	8
valid_sources[0x06]	27514	1			T1	9		T2	1		T7	22
valid_sources[0x07]	27591	1			T1	16		T7	10		T8	1
valid_sources[0x08]	26302	1			T1	13		T3	1		T7	14
valid_sources[0x09]	27622	1			T1	12		T2	1		T7	10
valid_sources[0x0a]	27578	1			T1	12		T2	4		T7	16
valid_sources[0x0b]	27269	1			T1	10		T2	2		T3	1
valid_sources[0x0c]	27115	1			T1	5		T2	1		T7	7
valid_sources[0x0d]	28014	1			T1	17		T2	2		T3	12
valid_sources[0x0e]	26567	1			T1	14		T2	1		T7	20
valid_sources[0x0f]	27410	1			T1	14		T2	2		T7	19
valid_sources[0x10]	28063	1			T1	11		T2	3		T7	23
valid_sources[0x11]	27389	1			T1	13		T2	3		T3	14
valid_sources[0x12]	27549	1			T1	13		T2	5		T3	5
valid_sources[0x13]	28233	1			T1	7		T7	11		T8	3
valid_sources[0x14]	26693	1			T1	14		T2	1		T7	16
valid_sources[0x15]	27603	1			T1	9		T2	3		T3	6
valid_sources[0x16]	27647	1			T1	13		T2	2		T7	17
valid_sources[0x17]	27620	1			T1	15		T2	1		T7	9
valid_sources[0x18]	27511	1			T1	16		T2	1		T7	14
valid_sources[0x19]	27473	1			T1	17		T2	2		T7	9
valid_sources[0x1a]	26961	1			T1	8		T2	1		T7	10
valid_sources[0x1b]	28134	1			T1	15		T2	3		T7	15
valid_sources[0x1c]	26759	1			T1	21		T2	1		T7	16
valid_sources[0x1d]	27290	1			T1	18		T2	1		T7	15
valid_sources[0x1e]	27316	1			T1	10		T2	1		T3	3
valid_sources[0x1f]	26851	1			T1	15		T2	2		T3	6
valid_sources[0x20]	27484	1			T1	19		T2	3		T7	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25557

1

T1

15

T2

2

T3

1

values[0x0]

all_enables

biggest_size

193387

1

T1

99

T2

18

T3

17

values[0x1]

all_enables

biggest_size

25740

1

T1

9

T2

2

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1504869	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239495

1

T1

134

T2

16

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	592353	1			T1	360		T2	41		T3	61
values[0x0]	559658	1			T1	298		T2	36		T3	51
values[0x1]	592353	1			T1	316		T2	44		T3	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1161846	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

582518

1

T1

360

T2

41

T3

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26903	1			T1	3		T2	2		T3	6
valid_sources[0x01]	27059	1			T1	18		T7	16		T8	6
valid_sources[0x02]	27875	1			T2	1		T7	17		T10	16
valid_sources[0x03]	27667	1			T1	16		T2	3		T7	14
valid_sources[0x04]	27107	1			T1	8		T2	4		T3	11
valid_sources[0x05]	27450	1			T2	1		T7	17		T8	3
valid_sources[0x06]	28335	1			T1	8		T2	3		T7	15
valid_sources[0x07]	26674	1			T1	4		T7	15		T8	3
valid_sources[0x08]	26877	1			T1	15		T2	1		T3	5
valid_sources[0x09]	28037	1			T1	30		T2	2		T7	6
valid_sources[0x0a]	26739	1			T1	17		T2	2		T3	4
valid_sources[0x0b]	26651	1			T1	28		T3	8		T7	14
valid_sources[0x0c]	27332	1			T1	22		T2	1		T3	2
valid_sources[0x0d]	27275	1			T1	33		T2	1		T7	13
valid_sources[0x0e]	26535	1			T1	34		T7	23		T9	2
valid_sources[0x0f]	26781	1			T1	29		T2	1		T3	10
valid_sources[0x10]	27775	1			T2	2		T7	10		T8	6
valid_sources[0x11]	27040	1			T1	7		T2	2		T7	10
valid_sources[0x12]	27471	1			T1	16		T2	2		T3	9
valid_sources[0x13]	26894	1			T2	3		T3	3		T7	17
valid_sources[0x14]	27383	1			T1	16		T2	3		T7	13
valid_sources[0x15]	26490	1			T1	17		T2	2		T7	10
valid_sources[0x16]	27095	1			T1	16		T2	4		T3	15
valid_sources[0x17]	27281	1			T1	4		T2	1		T3	4
valid_sources[0x18]	27117	1			T1	30		T2	1		T7	13
valid_sources[0x19]	27989	1			T1	12		T2	3		T7	8
valid_sources[0x1a]	27703	1			T1	16		T2	1		T3	1
valid_sources[0x1b]	28102	1			T1	17		T2	1		T3	3
valid_sources[0x1c]	27381	1			T1	3		T2	4		T7	8
valid_sources[0x1d]	27487	1			T1	22		T2	2		T7	16
valid_sources[0x1e]	27106	1			T1	5		T2	4		T7	13
valid_sources[0x1f]	27041	1			T1	27		T2	1		T7	18
valid_sources[0x20]	27371	1			T1	16		T2	1		T7	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25184

1

T1

13

T2

1

T3

3

values[0x0]

all_enables

biggest_size

189171

1

T1

108

T2

15

T3

17

values[0x1]

all_enables

biggest_size

25140

1

T1

13

T3

6

T7

22