Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_27.fifo_h.reqfifo

Module Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	97.50	84.09			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	173632042	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	173632042	0	0
T1	30773	13511	0	0
T2	253077	90170	0	0
T3	170782	65740	0	0
T7	595894	255369	0	0
T8	447015	88823	0	0
T9	9335	5150	0	0
T10	797180	592912	0	0
T11	7686	5578	0	0
T12	9549	4703	0	0
T13	915814	377133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	62245694	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	62245694	0	0
T1	30773	6769	0	0
T2	253077	45479	0	0
T3	170782	14863	0	0
T7	595894	158988	0	0
T8	447015	40097	0	0
T9	9335	2059	0	0
T10	797180	6338	0	0
T11	7686	2103	0	0
T12	9549	1630	0	0
T13	915814	234633	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	1635308	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1635308	0	0
T1	30773	378	0	0
T2	253077	51	0	0
T3	170782	1029	0	0
T7	595894	10806	0	0
T8	447015	32	0	0
T9	9335	272	0	0
T10	797180	409	0	0
T11	7686	490	0	0
T12	9549	416	0	0
T13	915814	4161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	15619291	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	15619291	0	0
T1	30773	1623	0	0
T2	253077	13771	0	0
T3	170782	2253	0	0
T7	595894	37460	0	0
T8	447015	9488	0	0
T9	9335	268	0	0
T10	797180	653	0	0
T11	7686	483	0	0
T12	9549	409	0	0
T13	915814	57041	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	1775240	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1775240	0	0
T1	30773	464	0	0
T2	253077	32	0	0
T3	170782	1573	0	0
T7	595894	10192	0	0
T8	447015	40	0	0
T9	9335	315	0	0
T10	797180	452	0	0
T11	7686	598	0	0
T12	9549	620	0	0
T13	915814	4778	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	14767082	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	14767082	0	0
T1	30773	1667	0	0
T2	253077	9746	0	0
T3	170782	3015	0	0
T7	595894	36681	0	0
T8	447015	8677	0	0
T9	9335	260	0	0
T10	797180	1193	0	0
T11	7686	489	0	0
T12	9549	454	0	0
T13	915814	60696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	9030241	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	9030241	0	0
T1	30773	1994	0	0
T2	253077	90	0	0
T3	170782	12305	0	0
T7	595894	33033	0	0
T8	447015	105	0	0
T9	9335	248	0	0
T10	797180	1273	0	0
T11	7686	507	0	0
T12	9549	390	0	0
T13	915814	59078	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	15804970	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	15804970	0	0
T1	30773	1777	0	0
T2	253077	6011	0	0
T3	170782	5780	0	0
T7	595894	36436	0	0
T8	447015	8810	0	0
T9	9335	246	0	0
T10	797180	866	0	0
T11	7686	504	0	0
T12	9549	380	0	0
T13	915814	54918	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	1741246	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1741246	0	0
T1	30773	427	0	0
T2	253077	48	0	0
T3	170782	1120	0	0
T7	595894	15623	0	0
T8	447015	72	0	0
T9	9335	291	0	0
T10	797180	351	0	0
T11	7686	616	0	0
T12	9549	498	0	0
T13	915814	3181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	15128764	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	15128764	0	0
T1	30773	1691	0	0
T2	253077	15951	0	0
T3	170782	3815	0	0
T7	595894	34370	0	0
T8	447015	13122	0	0
T9	9335	251	0	0
T10	797180	3626	0	0
T11	7686	492	0	0
T12	9549	386	0	0
T13	915814	61173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	2	2	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Excluded	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	12414909	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	396906024	12414909	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	12414909	0	0
T1	30773	2454	0	0
T2	253077	202	0	0
T3	170782	19338	0	0
T7	595894	54803	0	0
T8	447015	169	0	0
T9	9335	364	0	0
T10	797180	1793	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	72605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	12414909	0	0
T1	30773	2454	0	0
T2	253077	202	0	0
T3	170782	19338	0	0
T7	595894	54803	0	0
T8	447015	169	0	0
T9	9335	364	0	0
T10	797180	1793	0	0
T11	7686	570	0	0
T12	9549	557	0	0
T13	915814	72605	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	19578737	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	396906024	19578737	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	19578737	0	0
T1	30773	2069	0	0
T2	253077	15652	0	0
T3	170782	3748	0	0
T7	595894	44752	0	0
T8	447015	12087	0	0
T9	9335	364	0	0
T10	797180	9745	0	0
T11	7686	569	0	0
T12	9549	557	0	0
T13	915814	58509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	19578737	0	0
T1	30773	2069	0	0
T2	253077	15652	0	0
T3	170782	3748	0	0
T7	595894	44752	0	0
T8	447015	12087	0	0
T9	9335	364	0	0
T10	797180	9745	0	0
T11	7686	569	0	0
T12	9549	557	0	0
T13	915814	58509	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	1635308	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	1635308	0	0
T1	30773	378	0	0
T2	253077	51	0	0
T3	170782	1029	0	0
T7	595894	10806	0	0
T8	447015	32	0	0
T9	9335	272	0	0
T10	797180	409	0	0
T11	7686	490	0	0
T12	9549	416	0	0
T13	915814	4161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	15619291	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	15619291	0	0
T1	30773	1623	0	0
T2	253077	13771	0	0
T3	170782	2253	0	0
T7	595894	37460	0	0
T8	447015	9488	0	0
T9	9335	268	0	0
T10	797180	653	0	0
T11	7686	483	0	0
T12	9549	409	0	0
T13	915814	57041	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0