SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.31 | 100.00 | 81.25 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.57 | 97.50 | 80.56 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.75 | 100.00 | 75.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.88 | 97.50 | 77.78 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[2].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 449305 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 449305 | 0 | 0 |
T1 | 30773 | 58 | 0 | 0 |
T2 | 253077 | 6 | 0 | 0 |
T3 | 170782 | 859 | 0 | 0 |
T7 | 595894 | 2938 | 0 | 0 |
T8 | 447015 | 6 | 0 | 0 |
T9 | 9335 | 40 | 0 | 0 |
T10 | 797180 | 50 | 0 | 0 |
T11 | 7686 | 51 | 0 | 0 |
T12 | 9549 | 72 | 0 | 0 |
T13 | 915814 | 764 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 3438201 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 3438201 | 0 | 0 |
T1 | 30773 | 372 | 0 | 0 |
T2 | 253077 | 1875 | 0 | 0 |
T3 | 170782 | 322 | 0 | 0 |
T7 | 595894 | 6098 | 0 | 0 |
T8 | 447015 | 2384 | 0 | 0 |
T9 | 9335 | 40 | 0 | 0 |
T10 | 797180 | 48 | 0 | 0 |
T11 | 7686 | 49 | 0 | 0 |
T12 | 9549 | 70 | 0 | 0 |
T13 | 915814 | 954 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 574727 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 574727 | 0 | 0 |
T1 | 30773 | 61 | 0 | 0 |
T2 | 253077 | 8 | 0 | 0 |
T3 | 170782 | 982 | 0 | 0 |
T7 | 595894 | 6682 | 0 | 0 |
T8 | 447015 | 8 | 0 | 0 |
T9 | 9335 | 56 | 0 | 0 |
T10 | 797180 | 74 | 0 | 0 |
T11 | 7686 | 38 | 0 | 0 |
T12 | 9549 | 78 | 0 | 0 |
T13 | 915814 | 1046 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 521245 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 521245 | 0 | 0 |
T1 | 30773 | 74 | 0 | 0 |
T2 | 253077 | 6 | 0 | 0 |
T3 | 170782 | 1173 | 0 | 0 |
T7 | 595894 | 1194 | 0 | 0 |
T8 | 447015 | 215 | 0 | 0 |
T9 | 9335 | 56 | 0 | 0 |
T10 | 797180 | 9044 | 0 | 0 |
T11 | 7686 | 37 | 0 | 0 |
T12 | 9549 | 78 | 0 | 0 |
T13 | 915814 | 514 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 12311076 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 396906024 | 12311076 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 12311076 | 0 | 0 |
T1 | 30773 | 2391 | 0 | 0 |
T2 | 253077 | 165 | 0 | 0 |
T3 | 170782 | 19550 | 0 | 0 |
T7 | 595894 | 45943 | 0 | 0 |
T8 | 447015 | 157 | 0 | 0 |
T9 | 9335 | 354 | 0 | 0 |
T10 | 797180 | 1917 | 0 | 0 |
T11 | 7686 | 550 | 0 | 0 |
T12 | 9549 | 603 | 0 | 0 |
T13 | 915814 | 74767 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 12311076 | 0 | 0 |
T1 | 30773 | 2391 | 0 | 0 |
T2 | 253077 | 165 | 0 | 0 |
T3 | 170782 | 19550 | 0 | 0 |
T7 | 595894 | 45943 | 0 | 0 |
T8 | 447015 | 157 | 0 | 0 |
T9 | 9335 | 354 | 0 | 0 |
T10 | 797180 | 1917 | 0 | 0 |
T11 | 7686 | 550 | 0 | 0 |
T12 | 9549 | 603 | 0 | 0 |
T13 | 915814 | 74767 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 17800032 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 396906024 | 17800032 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 17800032 | 0 | 0 |
T1 | 30773 | 2036 | 0 | 0 |
T2 | 253077 | 10285 | 0 | 0 |
T3 | 170782 | 3825 | 0 | 0 |
T7 | 595894 | 44999 | 0 | 0 |
T8 | 447015 | 12647 | 0 | 0 |
T9 | 9335 | 354 | 0 | 0 |
T10 | 797180 | 7071 | 0 | 0 |
T11 | 7686 | 549 | 0 | 0 |
T12 | 9549 | 603 | 0 | 0 |
T13 | 915814 | 64151 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 17800032 | 0 | 0 |
T1 | 30773 | 2036 | 0 | 0 |
T2 | 253077 | 10285 | 0 | 0 |
T3 | 170782 | 3825 | 0 | 0 |
T7 | 595894 | 44999 | 0 | 0 |
T8 | 447015 | 12647 | 0 | 0 |
T9 | 9335 | 354 | 0 | 0 |
T10 | 797180 | 7071 | 0 | 0 |
T11 | 7686 | 549 | 0 | 0 |
T12 | 9549 | 603 | 0 | 0 |
T13 | 915814 | 64151 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 1775240 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 1775240 | 0 | 0 |
T1 | 30773 | 464 | 0 | 0 |
T2 | 253077 | 32 | 0 | 0 |
T3 | 170782 | 1573 | 0 | 0 |
T7 | 595894 | 10192 | 0 | 0 |
T8 | 447015 | 40 | 0 | 0 |
T9 | 9335 | 315 | 0 | 0 |
T10 | 797180 | 452 | 0 | 0 |
T11 | 7686 | 598 | 0 | 0 |
T12 | 9549 | 620 | 0 | 0 |
T13 | 915814 | 4778 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 14767082 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 14767082 | 0 | 0 |
T1 | 30773 | 1667 | 0 | 0 |
T2 | 253077 | 9746 | 0 | 0 |
T3 | 170782 | 3015 | 0 | 0 |
T7 | 595894 | 36681 | 0 | 0 |
T8 | 447015 | 8677 | 0 | 0 |
T9 | 9335 | 260 | 0 | 0 |
T10 | 797180 | 1193 | 0 | 0 |
T11 | 7686 | 489 | 0 | 0 |
T12 | 9549 | 454 | 0 | 0 |
T13 | 915814 | 60696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 516929 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 516929 | 0 | 0 |
T1 | 30773 | 101 | 0 | 0 |
T2 | 253077 | 2 | 0 | 0 |
T3 | 170782 | 91 | 0 | 0 |
T7 | 595894 | 4453 | 0 | 0 |
T8 | 447015 | 8 | 0 | 0 |
T9 | 9335 | 45 | 0 | 0 |
T10 | 797180 | 67 | 0 | 0 |
T11 | 7686 | 35 | 0 | 0 |
T12 | 9549 | 98 | 0 | 0 |
T13 | 915814 | 561 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 2639089 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 2639089 | 0 | 0 |
T1 | 30773 | 304 | 0 | 0 |
T2 | 253077 | 532 | 0 | 0 |
T3 | 170782 | 804 | 0 | 0 |
T7 | 595894 | 7020 | 0 | 0 |
T8 | 447015 | 3361 | 0 | 0 |
T9 | 9335 | 42 | 0 | 0 |
T10 | 797180 | 58 | 0 | 0 |
T11 | 7686 | 30 | 0 | 0 |
T12 | 9549 | 75 | 0 | 0 |
T13 | 915814 | 1567 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 652224 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 652224 | 0 | 0 |
T1 | 30773 | 80 | 0 | 0 |
T2 | 253077 | 9 | 0 | 0 |
T3 | 170782 | 430 | 0 | 0 |
T7 | 595894 | 5031 | 0 | 0 |
T8 | 447015 | 4 | 0 | 0 |
T9 | 9335 | 55 | 0 | 0 |
T10 | 797180 | 54 | 0 | 0 |
T11 | 7686 | 30 | 0 | 0 |
T12 | 9549 | 87 | 0 | 0 |
T13 | 915814 | 1523 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 393861 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 393861 | 0 | 0 |
T1 | 30773 | 65 | 0 | 0 |
T2 | 253077 | 7 | 0 | 0 |
T3 | 170782 | 6 | 0 | 0 |
T7 | 595894 | 1298 | 0 | 0 |
T8 | 447015 | 609 | 0 | 0 |
T9 | 9335 | 52 | 0 | 0 |
T10 | 797180 | 5820 | 0 | 0 |
T11 | 7686 | 30 | 0 | 0 |
T12 | 9549 | 74 | 0 | 0 |
T13 | 915814 | 1888 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 11839260 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 11839260 | 0 | 0 |
T1 | 30773 | 2704 | 0 | 0 |
T2 | 253077 | 149 | 0 | 0 |
T3 | 170782 | 16155 | 0 | 0 |
T7 | 595894 | 44126 | 0 | 0 |
T8 | 447015 | 158 | 0 | 0 |
T9 | 9335 | 326 | 0 | 0 |
T10 | 797180 | 1676 | 0 | 0 |
T11 | 7686 | 571 | 0 | 0 |
T12 | 9549 | 532 | 0 | 0 |
T13 | 915814 | 71596 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 19951835 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 19951835 | 0 | 0 |
T1 | 30773 | 2165 | 0 | 0 |
T2 | 253077 | 7380 | 0 | 0 |
T3 | 170782 | 6793 | 0 | 0 |
T7 | 595894 | 44068 | 0 | 0 |
T8 | 447015 | 11192 | 0 | 0 |
T9 | 9335 | 326 | 0 | 0 |
T10 | 797180 | 7294 | 0 | 0 |
T11 | 7686 | 571 | 0 | 0 |
T12 | 9549 | 532 | 0 | 0 |
T13 | 915814 | 57415 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |