Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
271264 |
0 |
0 |
T1 |
30773 |
45 |
0 |
0 |
T2 |
253077 |
2 |
0 |
0 |
T3 |
170782 |
9 |
0 |
0 |
T7 |
595894 |
4540 |
0 |
0 |
T8 |
447015 |
5 |
0 |
0 |
T9 |
9335 |
37 |
0 |
0 |
T10 |
797180 |
43 |
0 |
0 |
T11 |
7686 |
270 |
0 |
0 |
T12 |
9549 |
84 |
0 |
0 |
T13 |
915814 |
1016 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3075221 |
0 |
0 |
T1 |
30773 |
249 |
0 |
0 |
T2 |
253077 |
544 |
0 |
0 |
T3 |
170782 |
432 |
0 |
0 |
T7 |
595894 |
4696 |
0 |
0 |
T8 |
447015 |
2486 |
0 |
0 |
T9 |
9335 |
36 |
0 |
0 |
T10 |
797180 |
43 |
0 |
0 |
T11 |
7686 |
228 |
0 |
0 |
T12 |
9549 |
72 |
0 |
0 |
T13 |
915814 |
3179 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
354968 |
0 |
0 |
T1 |
30773 |
61 |
0 |
0 |
T2 |
253077 |
6 |
0 |
0 |
T3 |
170782 |
5 |
0 |
0 |
T7 |
595894 |
5717 |
0 |
0 |
T8 |
447015 |
4 |
0 |
0 |
T9 |
9335 |
46 |
0 |
0 |
T10 |
797180 |
53 |
0 |
0 |
T11 |
7686 |
413 |
0 |
0 |
T12 |
9549 |
72 |
0 |
0 |
T13 |
915814 |
522 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
614439 |
0 |
0 |
T1 |
30773 |
72 |
0 |
0 |
T2 |
253077 |
6 |
0 |
0 |
T3 |
170782 |
5 |
0 |
0 |
T7 |
595894 |
887 |
0 |
0 |
T8 |
447015 |
1416 |
0 |
0 |
T9 |
9335 |
45 |
0 |
0 |
T10 |
797180 |
7326 |
0 |
0 |
T11 |
7686 |
283 |
0 |
0 |
T12 |
9549 |
68 |
0 |
0 |
T13 |
915814 |
1782 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2980788 |
0 |
0 |
T1 |
30773 |
700 |
0 |
0 |
T2 |
253077 |
39 |
0 |
0 |
T3 |
170782 |
8715 |
0 |
0 |
T7 |
595894 |
10230 |
0 |
0 |
T8 |
447015 |
78 |
0 |
0 |
T9 |
9335 |
88 |
0 |
0 |
T10 |
797180 |
457 |
0 |
0 |
T11 |
7686 |
90 |
0 |
0 |
T12 |
9549 |
144 |
0 |
0 |
T13 |
915814 |
15845 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2980788 |
0 |
0 |
T1 |
30773 |
700 |
0 |
0 |
T2 |
253077 |
39 |
0 |
0 |
T3 |
170782 |
8715 |
0 |
0 |
T7 |
595894 |
10230 |
0 |
0 |
T8 |
447015 |
78 |
0 |
0 |
T9 |
9335 |
88 |
0 |
0 |
T10 |
797180 |
457 |
0 |
0 |
T11 |
7686 |
90 |
0 |
0 |
T12 |
9549 |
144 |
0 |
0 |
T13 |
915814 |
15845 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3420003 |
0 |
0 |
T1 |
30773 |
433 |
0 |
0 |
T2 |
253077 |
1876 |
0 |
0 |
T3 |
170782 |
1094 |
0 |
0 |
T7 |
595894 |
5011 |
0 |
0 |
T8 |
447015 |
3289 |
0 |
0 |
T9 |
9335 |
88 |
0 |
0 |
T10 |
797180 |
8556 |
0 |
0 |
T11 |
7686 |
89 |
0 |
0 |
T12 |
9549 |
144 |
0 |
0 |
T13 |
915814 |
3812 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3420003 |
0 |
0 |
T1 |
30773 |
433 |
0 |
0 |
T2 |
253077 |
1876 |
0 |
0 |
T3 |
170782 |
1094 |
0 |
0 |
T7 |
595894 |
5011 |
0 |
0 |
T8 |
447015 |
3289 |
0 |
0 |
T9 |
9335 |
88 |
0 |
0 |
T10 |
797180 |
8556 |
0 |
0 |
T11 |
7686 |
89 |
0 |
0 |
T12 |
9549 |
144 |
0 |
0 |
T13 |
915814 |
3812 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
289416 |
0 |
0 |
T1 |
30773 |
66 |
0 |
0 |
T2 |
253077 |
5 |
0 |
0 |
T3 |
170782 |
11 |
0 |
0 |
T7 |
595894 |
931 |
0 |
0 |
T8 |
447015 |
8 |
0 |
0 |
T9 |
9335 |
47 |
0 |
0 |
T10 |
797180 |
67 |
0 |
0 |
T11 |
7686 |
49 |
0 |
0 |
T12 |
9549 |
84 |
0 |
0 |
T13 |
915814 |
209 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2843417 |
0 |
0 |
T1 |
30773 |
341 |
0 |
0 |
T2 |
253077 |
1872 |
0 |
0 |
T3 |
170782 |
653 |
0 |
0 |
T7 |
595894 |
4227 |
0 |
0 |
T8 |
447015 |
2943 |
0 |
0 |
T9 |
9335 |
44 |
0 |
0 |
T10 |
797180 |
566 |
0 |
0 |
T11 |
7686 |
47 |
0 |
0 |
T12 |
9549 |
74 |
0 |
0 |
T13 |
915814 |
2117 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
388062 |
0 |
0 |
T1 |
30773 |
57 |
0 |
0 |
T2 |
253077 |
4 |
0 |
0 |
T3 |
170782 |
10 |
0 |
0 |
T7 |
595894 |
1331 |
0 |
0 |
T8 |
447015 |
15 |
0 |
0 |
T9 |
9335 |
44 |
0 |
0 |
T10 |
797180 |
68 |
0 |
0 |
T11 |
7686 |
43 |
0 |
0 |
T12 |
9549 |
71 |
0 |
0 |
T13 |
915814 |
20 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
576586 |
0 |
0 |
T1 |
30773 |
92 |
0 |
0 |
T2 |
253077 |
4 |
0 |
0 |
T3 |
170782 |
441 |
0 |
0 |
T7 |
595894 |
784 |
0 |
0 |
T8 |
447015 |
346 |
0 |
0 |
T9 |
9335 |
44 |
0 |
0 |
T10 |
797180 |
7990 |
0 |
0 |
T11 |
7686 |
42 |
0 |
0 |
T12 |
9549 |
70 |
0 |
0 |
T13 |
915814 |
1695 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3046524 |
0 |
0 |
T1 |
30773 |
722 |
0 |
0 |
T2 |
253077 |
49 |
0 |
0 |
T3 |
170782 |
4915 |
0 |
0 |
T7 |
595894 |
19894 |
0 |
0 |
T8 |
447015 |
56 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
421 |
0 |
0 |
T11 |
7686 |
76 |
0 |
0 |
T12 |
9549 |
178 |
0 |
0 |
T13 |
915814 |
14986 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3046524 |
0 |
0 |
T1 |
30773 |
722 |
0 |
0 |
T2 |
253077 |
49 |
0 |
0 |
T3 |
170782 |
4915 |
0 |
0 |
T7 |
595894 |
19894 |
0 |
0 |
T8 |
447015 |
56 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
421 |
0 |
0 |
T11 |
7686 |
76 |
0 |
0 |
T12 |
9549 |
178 |
0 |
0 |
T13 |
915814 |
14986 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3626445 |
0 |
0 |
T1 |
30773 |
434 |
0 |
0 |
T2 |
253077 |
1622 |
0 |
0 |
T3 |
170782 |
494 |
0 |
0 |
T7 |
595894 |
9272 |
0 |
0 |
T8 |
447015 |
4251 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
5016 |
0 |
0 |
T11 |
7686 |
75 |
0 |
0 |
T12 |
9549 |
178 |
0 |
0 |
T13 |
915814 |
4201 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3626445 |
0 |
0 |
T1 |
30773 |
434 |
0 |
0 |
T2 |
253077 |
1622 |
0 |
0 |
T3 |
170782 |
494 |
0 |
0 |
T7 |
595894 |
9272 |
0 |
0 |
T8 |
447015 |
4251 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
5016 |
0 |
0 |
T11 |
7686 |
75 |
0 |
0 |
T12 |
9549 |
178 |
0 |
0 |
T13 |
915814 |
4201 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
290361 |
0 |
0 |
T1 |
30773 |
65 |
0 |
0 |
T2 |
253077 |
8 |
0 |
0 |
T3 |
170782 |
8 |
0 |
0 |
T7 |
595894 |
3876 |
0 |
0 |
T8 |
447015 |
6 |
0 |
0 |
T9 |
9335 |
47 |
0 |
0 |
T10 |
797180 |
45 |
0 |
0 |
T11 |
7686 |
43 |
0 |
0 |
T12 |
9549 |
88 |
0 |
0 |
T13 |
915814 |
22 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3010751 |
0 |
0 |
T1 |
30773 |
396 |
0 |
0 |
T2 |
253077 |
1617 |
0 |
0 |
T3 |
170782 |
166 |
0 |
0 |
T7 |
595894 |
7872 |
0 |
0 |
T8 |
447015 |
3077 |
0 |
0 |
T9 |
9335 |
47 |
0 |
0 |
T10 |
797180 |
45 |
0 |
0 |
T11 |
7686 |
40 |
0 |
0 |
T12 |
9549 |
78 |
0 |
0 |
T13 |
915814 |
3416 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |