Unified Coverage Report :: Module Instance :: tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo

Module Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	375338	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	375338	0	0
T1	30773	70	0	0
T2	253077	5	0	0
T3	170782	53	0	0
T7	595894	4955	0	0
T8	447015	6	0	0
T9	9335	44	0	0
T10	797180	49	0	0
T11	7686	36	0	0
T12	9549	102	0	0
T13	915814	449	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	615694	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	615694	0	0
T1	30773	38	0	0
T2	253077	5	0	0
T3	170782	328	0	0
T7	595894	1400	0	0
T8	447015	1174	0	0
T9	9335	43	0	0
T10	797180	4971	0	0
T11	7686	35	0	0
T12	9549	100	0	0
T13	915814	785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3017274	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	396906024	3017274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3017274	0	0
T1	30773	631	0	0
T2	253077	31	0	0
T3	170782	2313	0	0
T7	595894	6094	0	0
T8	447015	68	0	0
T9	9335	89	0	0
T10	797180	401	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	17537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3017274	0	0
T1	30773	631	0	0
T2	253077	31	0	0
T3	170782	2313	0	0
T7	595894	6094	0	0
T8	447015	68	0	0
T9	9335	89	0	0
T10	797180	401	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	17537	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	4080374	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	396906024	4080374	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4080374	0	0
T1	30773	357	0	0
T2	253077	1538	0	0
T3	170782	353	0	0
T7	595894	3501	0	0
T8	447015	3756	0	0
T9	9335	89	0	0
T10	797180	8119	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	2931	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	4080374	0	0
T1	30773	357	0	0
T2	253077	1538	0	0
T3	170782	353	0	0
T7	595894	3501	0	0
T8	447015	3756	0	0
T9	9335	89	0	0
T10	797180	8119	0	0
T11	7686	78	0	0
T12	9549	126	0	0
T13	915814	2931	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	323451	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	323451	0	0
T1	30773	61	0	0
T2	253077	4	0	0
T3	170782	4	0	0
T7	595894	421	0	0
T8	447015	9	0	0
T9	9335	49	0	0
T10	797180	77	0	0
T11	7686	40	0	0
T12	9549	61	0	0
T13	915814	543	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3409058	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3409058	0	0
T1	30773	295	0	0
T2	253077	1533	0	0
T3	170782	348	0	0
T7	595894	3064	0	0
T8	447015	3221	0	0
T9	9335	47	0	0
T10	797180	56	0	0
T11	7686	39	0	0
T12	9549	60	0	0
T13	915814	1646	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	411576	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	411576	0	0
T1	30773	61	0	0
T2	253077	5	0	0
T3	170782	5	0	0
T7	595894	515	0	0
T8	447015	5	0	0
T9	9335	42	0	0
T10	797180	53	0	0
T11	7686	40	0	0
T12	9549	67	0	0
T13	915814	737	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	671316	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	671316	0	0
T1	30773	62	0	0
T2	253077	5	0	0
T3	170782	5	0	0
T7	595894	437	0	0
T8	447015	535	0	0
T9	9335	42	0	0
T10	797180	8063	0	0
T11	7686	39	0	0
T12	9549	66	0	0
T13	915814	1285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3001572	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	396906024	3001572	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3001572	0	0
T1	30773	804	0	0
T2	253077	41	0	0
T3	170782	3196	0	0
T7	595894	13689	0	0
T8	447015	35	0	0
T9	9335	157	0	0
T10	797180	484	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	18016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3001572	0	0
T1	30773	804	0	0
T2	253077	41	0	0
T3	170782	3196	0	0
T7	595894	13689	0	0
T8	447015	35	0	0
T9	9335	157	0	0
T10	797180	484	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	18016	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3781954	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	396906024	3781954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3781954	0	0
T1	30773	436	0	0
T2	253077	579	0	0
T3	170782	2047	0	0
T7	595894	8083	0	0
T8	447015	1539	0	0
T9	9335	157	0	0
T10	797180	5580	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	3043	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3781954	0	0
T1	30773	436	0	0
T2	253077	579	0	0
T3	170782	2047	0	0
T7	595894	8083	0	0
T8	447015	1539	0	0
T9	9335	157	0	0
T10	797180	5580	0	0
T11	7686	104	0	0
T12	9549	156	0	0
T13	915814	3043	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	304535	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	304535	0	0
T1	30773	66	0	0
T2	253077	3	0	0
T3	170782	11	0	0
T7	595894	1601	0	0
T8	447015	8	0	0
T9	9335	85	0	0
T10	797180	58	0	0
T11	7686	54	0	0
T12	9549	83	0	0
T13	915814	568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3127715	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3127715	0	0
T1	30773	364	0	0
T2	253077	573	0	0
T3	170782	2042	0	0
T7	595894	6534	0	0
T8	447015	1067	0	0
T9	9335	78	0	0
T10	797180	684	0	0
T11	7686	47	0	0
T12	9549	75	0	0
T13	915814	2556	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	389789	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	389789	0	0
T1	30773	55	0	0
T2	253077	6	0	0
T3	170782	5	0	0
T7	595894	1953	0	0
T8	447015	3	0	0
T9	9335	79	0	0
T10	797180	60	0	0
T11	7686	57	0	0
T12	9549	81	0	0
T13	915814	429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	654239	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	654239	0	0
T1	30773	72	0	0
T2	253077	6	0	0
T3	170782	5	0	0
T7	595894	1549	0	0
T8	447015	472	0	0
T9	9335	79	0	0
T10	797180	4896	0	0
T11	7686	57	0	0
T12	9549	81	0	0
T13	915814	487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0