Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2971337 |
0 |
0 |
T1 |
30773 |
532 |
0 |
0 |
T2 |
253077 |
64 |
0 |
0 |
T3 |
170782 |
5105 |
0 |
0 |
T7 |
595894 |
11874 |
0 |
0 |
T8 |
447015 |
81 |
0 |
0 |
T9 |
9335 |
92 |
0 |
0 |
T10 |
797180 |
374 |
0 |
0 |
T11 |
7686 |
68 |
0 |
0 |
T12 |
9549 |
146 |
0 |
0 |
T13 |
915814 |
19988 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2971337 |
0 |
0 |
T1 |
30773 |
532 |
0 |
0 |
T2 |
253077 |
64 |
0 |
0 |
T3 |
170782 |
5105 |
0 |
0 |
T7 |
595894 |
11874 |
0 |
0 |
T8 |
447015 |
81 |
0 |
0 |
T9 |
9335 |
92 |
0 |
0 |
T10 |
797180 |
374 |
0 |
0 |
T11 |
7686 |
68 |
0 |
0 |
T12 |
9549 |
146 |
0 |
0 |
T13 |
915814 |
19988 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3565116 |
0 |
0 |
T1 |
30773 |
331 |
0 |
0 |
T2 |
253077 |
3232 |
0 |
0 |
T3 |
170782 |
100 |
0 |
0 |
T7 |
595894 |
5931 |
0 |
0 |
T8 |
447015 |
7393 |
0 |
0 |
T9 |
9335 |
92 |
0 |
0 |
T10 |
797180 |
6114 |
0 |
0 |
T11 |
7686 |
68 |
0 |
0 |
T12 |
9549 |
146 |
0 |
0 |
T13 |
915814 |
4830 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3565116 |
0 |
0 |
T1 |
30773 |
331 |
0 |
0 |
T2 |
253077 |
3232 |
0 |
0 |
T3 |
170782 |
100 |
0 |
0 |
T7 |
595894 |
5931 |
0 |
0 |
T8 |
447015 |
7393 |
0 |
0 |
T9 |
9335 |
92 |
0 |
0 |
T10 |
797180 |
6114 |
0 |
0 |
T11 |
7686 |
68 |
0 |
0 |
T12 |
9549 |
146 |
0 |
0 |
T13 |
915814 |
4830 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
279982 |
0 |
0 |
T1 |
30773 |
65 |
0 |
0 |
T2 |
253077 |
8 |
0 |
0 |
T3 |
170782 |
7 |
0 |
0 |
T7 |
595894 |
1158 |
0 |
0 |
T8 |
447015 |
11 |
0 |
0 |
T9 |
9335 |
45 |
0 |
0 |
T10 |
797180 |
54 |
0 |
0 |
T11 |
7686 |
38 |
0 |
0 |
T12 |
9549 |
83 |
0 |
0 |
T13 |
915814 |
577 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2976958 |
0 |
0 |
T1 |
30773 |
301 |
0 |
0 |
T2 |
253077 |
3227 |
0 |
0 |
T3 |
170782 |
91 |
0 |
0 |
T7 |
595894 |
4827 |
0 |
0 |
T8 |
447015 |
6114 |
0 |
0 |
T9 |
9335 |
39 |
0 |
0 |
T10 |
797180 |
456 |
0 |
0 |
T11 |
7686 |
34 |
0 |
0 |
T12 |
9549 |
75 |
0 |
0 |
T13 |
915814 |
2699 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
386999 |
0 |
0 |
T1 |
30773 |
36 |
0 |
0 |
T2 |
253077 |
5 |
0 |
0 |
T3 |
170782 |
9 |
0 |
0 |
T7 |
595894 |
3022 |
0 |
0 |
T8 |
447015 |
11 |
0 |
0 |
T9 |
9335 |
53 |
0 |
0 |
T10 |
797180 |
41 |
0 |
0 |
T11 |
7686 |
35 |
0 |
0 |
T12 |
9549 |
72 |
0 |
0 |
T13 |
915814 |
1497 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
588158 |
0 |
0 |
T1 |
30773 |
30 |
0 |
0 |
T2 |
253077 |
5 |
0 |
0 |
T3 |
170782 |
9 |
0 |
0 |
T7 |
595894 |
1104 |
0 |
0 |
T8 |
447015 |
1279 |
0 |
0 |
T9 |
9335 |
53 |
0 |
0 |
T10 |
797180 |
5658 |
0 |
0 |
T11 |
7686 |
34 |
0 |
0 |
T12 |
9549 |
71 |
0 |
0 |
T13 |
915814 |
2131 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2932515 |
0 |
0 |
T1 |
30773 |
746 |
0 |
0 |
T2 |
253077 |
59 |
0 |
0 |
T3 |
170782 |
3526 |
0 |
0 |
T7 |
595894 |
11803 |
0 |
0 |
T8 |
447015 |
49 |
0 |
0 |
T9 |
9335 |
84 |
0 |
0 |
T10 |
797180 |
404 |
0 |
0 |
T11 |
7686 |
78 |
0 |
0 |
T12 |
9549 |
147 |
0 |
0 |
T13 |
915814 |
22040 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2932515 |
0 |
0 |
T1 |
30773 |
746 |
0 |
0 |
T2 |
253077 |
59 |
0 |
0 |
T3 |
170782 |
3526 |
0 |
0 |
T7 |
595894 |
11803 |
0 |
0 |
T8 |
447015 |
49 |
0 |
0 |
T9 |
9335 |
84 |
0 |
0 |
T10 |
797180 |
404 |
0 |
0 |
T11 |
7686 |
78 |
0 |
0 |
T12 |
9549 |
147 |
0 |
0 |
T13 |
915814 |
22040 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3627622 |
0 |
0 |
T1 |
30773 |
514 |
0 |
0 |
T2 |
253077 |
1273 |
0 |
0 |
T3 |
170782 |
500 |
0 |
0 |
T7 |
595894 |
5377 |
0 |
0 |
T8 |
447015 |
3485 |
0 |
0 |
T9 |
9335 |
84 |
0 |
0 |
T10 |
797180 |
4929 |
0 |
0 |
T11 |
7686 |
78 |
0 |
0 |
T12 |
9549 |
147 |
0 |
0 |
T13 |
915814 |
2253 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3627622 |
0 |
0 |
T1 |
30773 |
514 |
0 |
0 |
T2 |
253077 |
1273 |
0 |
0 |
T3 |
170782 |
500 |
0 |
0 |
T7 |
595894 |
5377 |
0 |
0 |
T8 |
447015 |
3485 |
0 |
0 |
T9 |
9335 |
84 |
0 |
0 |
T10 |
797180 |
4929 |
0 |
0 |
T11 |
7686 |
78 |
0 |
0 |
T12 |
9549 |
147 |
0 |
0 |
T13 |
915814 |
2253 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
249159 |
0 |
0 |
T1 |
30773 |
79 |
0 |
0 |
T2 |
253077 |
6 |
0 |
0 |
T3 |
170782 |
6 |
0 |
0 |
T7 |
595894 |
3814 |
0 |
0 |
T8 |
447015 |
7 |
0 |
0 |
T9 |
9335 |
45 |
0 |
0 |
T10 |
797180 |
53 |
0 |
0 |
T11 |
7686 |
42 |
0 |
0 |
T12 |
9549 |
76 |
0 |
0 |
T13 |
915814 |
27 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2986555 |
0 |
0 |
T1 |
30773 |
426 |
0 |
0 |
T2 |
253077 |
1264 |
0 |
0 |
T3 |
170782 |
355 |
0 |
0 |
T7 |
595894 |
4598 |
0 |
0 |
T8 |
447015 |
2841 |
0 |
0 |
T9 |
9335 |
41 |
0 |
0 |
T10 |
797180 |
348 |
0 |
0 |
T11 |
7686 |
40 |
0 |
0 |
T12 |
9549 |
69 |
0 |
0 |
T13 |
915814 |
1232 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
332503 |
0 |
0 |
T1 |
30773 |
54 |
0 |
0 |
T2 |
253077 |
9 |
0 |
0 |
T3 |
170782 |
8 |
0 |
0 |
T7 |
595894 |
4966 |
0 |
0 |
T8 |
447015 |
6 |
0 |
0 |
T9 |
9335 |
43 |
0 |
0 |
T10 |
797180 |
44 |
0 |
0 |
T11 |
7686 |
38 |
0 |
0 |
T12 |
9549 |
78 |
0 |
0 |
T13 |
915814 |
1804 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
641067 |
0 |
0 |
T1 |
30773 |
88 |
0 |
0 |
T2 |
253077 |
9 |
0 |
0 |
T3 |
170782 |
145 |
0 |
0 |
T7 |
595894 |
779 |
0 |
0 |
T8 |
447015 |
644 |
0 |
0 |
T9 |
9335 |
43 |
0 |
0 |
T10 |
797180 |
4581 |
0 |
0 |
T11 |
7686 |
38 |
0 |
0 |
T12 |
9549 |
78 |
0 |
0 |
T13 |
915814 |
1021 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2950277 |
0 |
0 |
T1 |
30773 |
714 |
0 |
0 |
T2 |
253077 |
33 |
0 |
0 |
T3 |
170782 |
4409 |
0 |
0 |
T7 |
595894 |
10810 |
0 |
0 |
T8 |
447015 |
64 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
495 |
0 |
0 |
T11 |
7686 |
187 |
0 |
0 |
T12 |
9549 |
142 |
0 |
0 |
T13 |
915814 |
11888 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
2950277 |
0 |
0 |
T1 |
30773 |
714 |
0 |
0 |
T2 |
253077 |
33 |
0 |
0 |
T3 |
170782 |
4409 |
0 |
0 |
T7 |
595894 |
10810 |
0 |
0 |
T8 |
447015 |
64 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
495 |
0 |
0 |
T11 |
7686 |
187 |
0 |
0 |
T12 |
9549 |
142 |
0 |
0 |
T13 |
915814 |
11888 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3366632 |
0 |
0 |
T1 |
30773 |
385 |
0 |
0 |
T2 |
253077 |
1141 |
0 |
0 |
T3 |
170782 |
233 |
0 |
0 |
T7 |
595894 |
5251 |
0 |
0 |
T8 |
447015 |
4670 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
5424 |
0 |
0 |
T11 |
7686 |
186 |
0 |
0 |
T12 |
9549 |
142 |
0 |
0 |
T13 |
915814 |
2214 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
396790949 |
0 |
0 |
T1 |
30773 |
30753 |
0 |
0 |
T2 |
253077 |
253035 |
0 |
0 |
T3 |
170782 |
170738 |
0 |
0 |
T7 |
595894 |
595871 |
0 |
0 |
T8 |
447015 |
446967 |
0 |
0 |
T9 |
9335 |
9268 |
0 |
0 |
T10 |
797180 |
797169 |
0 |
0 |
T11 |
7686 |
7366 |
0 |
0 |
T12 |
9549 |
9507 |
0 |
0 |
T13 |
915814 |
915736 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396906024 |
3366632 |
0 |
0 |
T1 |
30773 |
385 |
0 |
0 |
T2 |
253077 |
1141 |
0 |
0 |
T3 |
170782 |
233 |
0 |
0 |
T7 |
595894 |
5251 |
0 |
0 |
T8 |
447015 |
4670 |
0 |
0 |
T9 |
9335 |
90 |
0 |
0 |
T10 |
797180 |
5424 |
0 |
0 |
T11 |
7686 |
186 |
0 |
0 |
T12 |
9549 |
142 |
0 |
0 |
T13 |
915814 |
2214 |
0 |
0 |